Readings

Handout on Phase 2 readings and discussion

Phase 1 (pre midterm)

• D. Wall, "Limits of Instruction-Level Parallelism", WRL Technical Note TN-15, Dec. 1990
• J. Smith and G. Sohi, "The microarchitecture of superscalar processors", Proceedings of the IEEE, pages 1609-1624, December 1995.
• S. McFarling, "Combining Branch Predictors", WRL Technical Note TN-36, June 1993
• P. DeMone, "The Battle in 64 bit Land, 2003 and Beyond", Real World Technologies, January 2003
• T. Juan et al, "Data Caches for Superscalar Processors", ICS 1997.
• E. Rothberg et al, "Working sets, cache sizes, and node granularity issues for large-scale multiprocessors", ACM Sigarch Computer Architecture News, Vol 21, Issue 2.
• P. Stenstrom. A Survey of Cache Coherence Schemes for Multiprocessors. IEEE Computer, Vol. 23, No. 6, June 1990.
• K. Gharachorloo et al, "Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors", ASPLOS IV, 1991.

Phase 2 (post midterm)

• Task of the Referee

1. Multithreaded Architectures (March 19)}
   • Chip Multiprocessors: "Exploring the design space of future CMPs", J. Huh, D. Burger and S. Keckler, PACT 2001.
   • Simultaneous Multithreading: "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo and Rebecca L. Stamm, ISCA 1996.
2. Using Threads (March 26)}
   • Thread-Level Speculation: ``A Scalable Approach to Thread-Level Speculation'', J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry, ISCA 2000.
   • Pre-Execution: "Tolerating Memory Latency through {Software-Controlled} {Pre-Execution} in Simultaneous Multithreading Processors", C.K. Luk, ISCA 2001.
3. Domain-Specific Processors (April 2)}
   • Network Processors: "Characterizing processor architectures for programmable network interfaces", Patrick Crowley and Marc E. Fluczynski and Jean-Loup Baer and Brian N. Bershad, Supercomputing 2000.
   • Cryptographic Processors: ``CryptoManiac: A Fast Flexible Architecture for Secure Communication'', Lisa Wu, Chris Weaver, and Todd Austin, ISCA 2001.
4. Reconfigurable Computing (April 9)}
   • Streaming: ``PipeRench: A Coprocessor for Streaming multimedia Acceleration'', "Seth Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, and Ronald Laufer, ISCA 1999.
   • Hybrid: ``CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit'', Zhi Alex Ye, Andreas Moshovos, Scott Hauck, and Prithviraj Banerjee, ISCA 2000.
5. Future Possibilities (April 16)}
   • Grid Processors: "A design space evaluation of grid processor architectures", R. Nagarajan, K. Sankaralingam, D. Burger and S. Keckler, MICRO 2001.
   • Nanotechnology: ``NanoFabrics: Spatial Computing Using Molecular Electronics'', Seth Goldstein and Mihai Budiu, ISCA 2001.