ECE341 Practice Question Website


Main Assembly Programming Input/Output Memory Computer Architecture Advanced Topics


Question 1

Input/Output Questions





Question 1

Two devices are connected by a asynchronous serial link (UART) as discussed in class and in the text and lab manual. For all parts of this question, the sender is configured at 28000 baud, 7 data bits, 2 stop bits. Note that ASCII codes are in Appendix E, page 791.
The sender device sends an ASCII code of ‘M’ to the other device.

Draw the logic level bit stream of this transmission including all the control bits and idle line levels before and after the transmission. Label each bit in the transmission. Reminder: The LSBit of the data is the first piece of data to be transmitted.

Answer

Transmited Bit stream as a graph



Question 2

Input/Output Questions





Question 2

Two devices are connected by a asynchronous serial link (UART) as discussed in class and in the text and lab manual. For all parts of this question, the sender is configured at 28000 baud, 7 data bits, 2 stop bits. Note that ASCII codes are in Appendix E, page 791.
The sender device sends an ASCII code of ‘M’ to the other device.

If the receiving device is configured at 56000 baud, what will it receive as a character?

Answer

f

Full Solution

This is double the transmit rate so the reciever will get bad information. Expected data transfer rate is shown at the bottom of the answer from Question 1. It will Read (LSB first) 0110011 [First zero is in start bit of transmission]

This is an ‘f’ in ASCII



Question 3

Input/Output Questions





Question 3

Two devices are connected by a asynchronous serial link (UART) as discussed in class and in the text and lab manual. For all parts of this question, the sender is configured at 28000 baud, 7 data bits, 2 stop bits. Note that ASCII codes are in Appendix E, page 791.
The sender device sends an ASCII code of ‘M’ to the other device.

If the receiving device is configured at 56000 baud, can the receiver ever tell that the baud rates are different over the course of a multiple character message transmission?

When or why not?

Answer

Yes

Full Solution

Yes: By looking at the stop bit and looking for framing errors



Question 4

Input/Output Questions





Question 4

Two devices are connected by a asynchronous serial link (UART) as discussed in class and in the text and lab manual. For all parts of this question, the sender is configured at 28000 baud, 7 data bits, 2 stop bits. Note that ASCII codes are in Appendix E, page 791.

How long would it take to transmit the phrase
        “YOUR HOUSE IS ON FIRE”
from this sender at full speed? (Ignore the quotation marks)

Answer

1/1400 sec

Full Solution

20 characters at 2800 characters per second = 1/1400 sec



Question 5

Input/Output Questions





Question 5

Two devices are connected by a asynchronous serial link (UART) as discussed in class and in the text and lab manual. For all parts of this question, the sender is configured at 28000 baud, 7 data bits, 2 stop bits. Note that ASCII codes are in Appendix E, page 791.

The ASCII code of a ‘B’ is send continuously from this same sender using the following 68000 code:

	TXBSY	equ	$FFFFFA00
	TXOUT 	equ 	$FFFFFA02
	.
	. 	;initialization etc. in here
	.
		moveq 	#$42,d0		;’B’ to d0
	chkser	btst.b 	#0,TXBSY	;check busy bit
		bne 	chkser		;back if still busy
		move.b 	d0,TXOUT	;the ‘B’ output
		bra 	chkser		;back until again not busy
	
If the timing of the instructions can be determined by the number of memory cycles, calculate the approximate proportion of time actually spent putting data into the UART to the amount of time just testing to see if the UART is busy. Assume each memory cycle takes 100nsec.

Answer

btstb 5 memory cycles = 500 nsec
bne 1 mem cycle = 100 nsec
move.b 4 mem cycles = 100 nsec
bra 1 mem cycle = 100 nsec

time for each transmit = 1/2800 sec = 3.6*10-4 sec = 360 usec

Approx proportion of time for transmit (and we are using the fact that it is approximate so we can avoid worrying about averaging things in – in the marking we were very liberal here so you didn’t even have to calculate the number of cycles of the first 2 instructions):

In an interval of 360 usec we spend 200 nsec transmitting and the rest polling, so the proportion is 200:360000 or 2:3600 or 1:1800



Question 6

Input/Output Questions





Question 6

Which requires the device to directly specify what device-specific entry in the interrupt vector table to use?

Vectored Interrupts
or
Autovectored Interrupts

Answer

Vectored Interrupts



Question 7

Input/Output Questions





Question 7

If we are using autovectored interrupts and a device with priority 3 causes an interrupt, at what address in the Interrupt Vector Table will the M68K find the starting address of the Interrupt Service Routine?

Answer

The address is 108 (0x6c)

Full Solution

(3+24)*4 = 108 (0x6C) is the address



Question 8

Input/Output Questions





Question 8

Say you design a micro-programmed processor that has 4 distinct steps for each instruction: Instruction Fetch, Instruction Decode & Fetch Operands, Execute, and Writeback. In what step should the micro-program check if there is a pending interrupt?

Answer

In the writeback step because the processor must determine whether the next step is a fetch or interrupt handler.

or

At the fetch step address determination, because this is where the usual fetch microaddress will be modified to the interrupt handler microaddress.



Question 9

Input/Output Questions





Question 9

The following are steps the CPU takes in an interrupt. Put the steps in order and write down the order below. We realize there are several correct answers and getting just one of them will suffice.

  1. CPU: completes the current instruction
  2. CPU: grants the interrupt for the device
    1. sends interrupt acknowledge to the device (IACK)
  3. ISR: Restore saved registers from the stack and executes return from exception instruction
  4. CPU: must save the state of the cpu before servicing the interrupt (pushing on the stack)
    1. current PC
    2. condition codes (CCR of status register)
  5. Program: CPU configures device for interrupts
  6. Device: sends a vector number to the cpu
  7. CPU: figures out what ISR to run
    1. uses vector to look up the address of that routine in the interrupt vector table
  8. CPU: Executes ISR
  9. CPU: return to point of execution where interrupted
  10. Program: CPU makes a request from device, and works on something else while waiting
  11. ISR: Saves Registers onto the stack (Callee Save) and execute
  12. Device: when device is ready, it sends an interrupt request to the cpu
  13. CPU: temporarily disables other interrupts
  14. CPU: restores PC and CCR

Answer

One order: EJL -> AB -> BFG -> M -> HKCNI There are 3 sequences here that can come in any order. So, for example, F must come after B and before G but can come before or after M, A and D. Similarly M can come at any time as long as it is after L and before H.




Question 10

Input/Output Questions





Question 10

Baud Rates
300
600
1200
2400
4800
9600
19200
A processor uses a serial link to communicate with a keyboard for word processing. A typist using this keyboard can type at rates peaking at 120 words per minute, where a word is 6 characters (including spaces and punctuation). The characters will be transmitted from the keyboard in 8-bit ASCII with one stop bit and no parity. Only consider these and no special characters.
If the processor allows selections of baud rates from the table at the right, circle the minimum baud rate that can be selected and still have the keyboard work for all typists?

Answer

300 Baud

Full Solution

120 wpm -> 120*6/60 cps = 12 cps
Each character requires 10 bits sent (8 bits for the character, 1 start, 1 stop)
Thus the minimum baud rate is 12*10=120 baud
Thus 300 baud is the setting to use.

Note that this is a fast typist!




Question 11

Input/Output Questions





Question 11

Baud Rates
300
600
1200
2400
4800
9600
19200
A processor uses a serial link to communicate with a keyboard for word processing. A typist using this keyboard can type at rates peaking at 120 words per minute, where a word is 6 characters (including spaces and punctuation). The characters will be transmitted from the keyboard in 8-bit ASCII with one stop bit and no parity. Only consider these and no special characters.
The programmer writes setup and polling service routines based on a minimum baud rate, but then finds that the keyboard will only interface at 19.2 Kbaud. Will the polling service routine have to change? Why or why not?

Answer

No it wont need to change.

Full Solution

No it won’t have to change. The interrupts will not come more frequently, just slightly faster after every keystroke. This is not something that necessitates change to the polling service routine.
Note that the setup routine would have to change to match the different baud rate




Question 12

Input/Output Questions





Question 12

A simple microprocessor is to have a watchdog timer installed. This timer will interrupt the processor unless it is constantly reset by the processor which it would normally do. This interrupt would happen if the processor went ‘off the rails’ because of a software problem, a power spike or something like that.
A circuit diagram is started below. The timer in the diagram gives a single positivegoing pulse which can be extended by ‘retriggering’ using the reset line. Some information about the timer and use are given on the diagrams.
The interrupt line is shared by other devices and is active when low.
In the scheme to be used, the processor will reset the timer (and thus avoid the interrupt) by accessing a specific address, $FFE0, faster than the pulse time of the timer, thus restarting the pulse without an interrupt being generated.

Timer: Relationship between reset input and the output:
T = pulse time
Graph showing relationship between reset input and the output
Use of watchdog:
Graph showing the use of the watchdog

Attach the timer to the 16-bit address bus and to the interrupt line so it will respond as required using supporting logic. For full marks, use ands /ors / nots and other gate-level devices only.

Diagram to be filled in

Answer

Diagram showing completed circuit



Question 13

Input/Output Questions





Question 13

A simple microprocessor is to have a watchdog timer installed. This timer will interrupt the processor unless it is constantly reset by the processor which it would normally do. This interrupt would happen if the processor went ‘off the rails’ because of a software problem, a power spike or something like that.
A circuit diagram is started below. The timer in the diagram gives a single positivegoing pulse which can be extended by ‘retriggering’ using the reset line. Some information about the timer and use are given on the diagrams.
The interrupt line is shared by other devices and is active when low.
In the scheme to be used, the processor will reset the timer (and thus avoid the interrupt) by accessing a specific address, $FFE0, faster than the pulse time of the timer, thus restarting the pulse without an interrupt being generated.

Address lines do not change instantaneously or absolutely at the same time. They may drift when not being driven by some source. These factors could cause accidental triggering of the watchdog if the address lines even momentarily have the value $FFE0. Describe briefly or show a method that might be used to greatly reduce or to eliminate this problem.

Answer

Possibilities:

  1. use MRDY or processor clock or bus clock to indicate when the address is valid
  2. use consecutive writes to 2 different (best non-consecutive) addresses to reset the timer
  3. write a specific value of data to lower the probability of problem.
  4. use a delay and and gate or other debounce circuit (see below)
    Debounce circuit