(October 2003)

Plan of Study
=============

I plan to conduct research in the area of operating systems.  The goal of my
research will be to improve operating system scalability on multiprocessor
computer systems.  In particular, I plan to study the impact of SMT
(simultaneous multithreading) and CMP (chip-multiprocessing) processor
technologies on operating system scalability.  SMT processors are becoming
increasingly economical and popular, while CMP processors are now becoming
available from companies such as IBM, Sun, Intel, and AMD.  Currently, SMT
processors typically consist of 2 to 4 hardware execution threads, while CMP
processors typically consist of 2 to 4 CPU cores.  In the future, these figures
will only increase.  In effect, these computer systems can be considered as
multiprocessors contained in a single processor package.  Currently, SMT and
CMP processors appear as small-scale multiprocessors but in the future, as the
level of chip integration increases, they will appear as large-scale
multiprocessors.  Therefore, operating system scalability is an important
property to maintain on these new breed of multiprocessors.

Enabling operating system support for such a hardware environment is typically
an after-thought rather than a fundamental design consideration.  Consequently,
operating system design and performance have not been adequately examined or
understood on these new hardware platforms.  Inefficiencies in the operating
system may be present since it fails to fully account for and exploit the
unique properties of SMT and CMP processors.  Further research is required to
understand the behaviour of various aspects of the operating system under this
new hardware environment.

Operating system design issues to examine include scheduling and memory
management.  SMT and CMP processors affect these aspects differently than
traditional multi-chip multiprocessors due to different hardware
characteristics.  On an SMT processor, micro-architectural resources such as
registers, arithmetic units, address translation-look-aside buffers, and L1 and
L2 caches are shared among the hardware execution threads.  Operating system
task scheduling and memory management must account for contention among these
shared hardware resources.  On a CMP processor, L2 caches may be shared and
there is a high-speed on-chip memory bus between CPU cores.  These new hardware
characteristics invalidate certain fundamental operating system design
assumptions.  For example, operating system design decisions made in the past
that were influenced by the presence of a traditional low-speed off-chip memory
bus between processors must be re-examined.  A high-speed on-chip memory bus
presents new optimization opportunities.