THESIS ABSTRACT

Ketan Shah

Dec. 2002

This thesis involved the design of a digital serial interface for integrated circuit testing. The thesis involved two components: a design of a serial interface using the JTAG standard and the design of a new standard based upon the JTAG standard.

The JTAG standard is an industry standard that allows test automation tools to interface with chips and apply test vectors to perform testing. This thesis involved the design of an interface to hide the underlying JTAG interface and the rules that govern it. The interface that hides the JTAG standard allows designers and testers more freedom in applying their test vectors. It also allows them to work with an easier interface as opposed to working with the JTAG standard.

The new standard designed is an extension of the JTAG standard. In the JTAG standard, four pins are used to interface with chips. The new standard designed here uses only three pins to interface with the chips. The reduction in pin count can result in more functionality being added by using the freed pin.

Both standards can easily be tested using a computer program. This thesis also designed a computer program that interfaces with the interface that hides the JTAG standard. The computer program communicates with the parallel port and allows the designer and tester to automate the test process. As a result, the computer program now takes care of sending test vectors to the digital serial interface and receive the results of the tests.

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