Low Power Error Control Coding
Introduction
Coding for data communication is a very active area of research. Codes are continuously under development to provide benefits such as improved spectral efficiency and decreased bit error rates. However, integrated circuit implementations of the most powerful codes being developed consume too much power for multi-Gb/s applications optical fibre communication.
Objective
The aim of this initiative is to develop hardware implementations for coding schemes that consume low-power while maintaining high throughput. Given the continued scaling of CMOS process technologies, one very promising direction is to use massive parallelism. It is well known that parallel computing architectures can be very power-efficient, but such approaches are often avoided due to the high hardware cost.. However, if the each of the parallel computing nodes can be made very small and simple this challenge can be overcome. The result is a computing engine comprising very many (thousands or more) exceedingly simple nodes that, together, are capable of remarkable computational throughput and energy efficiency, much like the simple neurons in the human brain.
Research
There are numerous research uncertainties that need to be answered. For example: what are the tradeoffs between the hardware cost of parallelism and the power advantages it offers? Practical implementations often impose restrictions on the amount of parallelism; what impact to do these constraints have on system performance? How can the interconnections between all of these computing nodes be managed efficiently?
The answers to some of these problems appear in our recent paper on this topic:
A. Darabiha, A. Chan Carusone, and F. Kschischang, "A 3.3-Gbps Bit-Serial Block-Interlaced Min-Sum LDPC Decoder in 0.13-um CMOS," Custom Integrated Circuits Conference, San Jose, California, September 2007. [PDF Format]
There, we describe an integrated circuit implementation of an error control decoder capable of both the highest throughput and the best energy efficiency of any implementation of a similar decoder ever reported.