Design Gallery

Designer: Horace Cheng

Technology: 0.13-um CMOS

This is the fastest 4-PAM transmitter ever demonstrated to date.  It incorporates an equalizer capable of compensating for up to 30-dB of cable loss.

Designer: Shahriar Shahramian

Technology: 0.18-um SiGe BiCMOS

This analog-to-digital converter has has 3.7 ENOB with an effective resolution bandwidth of 8-GHz at a full-scale input of only 270-mVpp differential.

Designer: Peter Park

Technology: 90-nm CMOS

This analog front end incorporates a variable gain of up to 31dB and an equalizer with sufficient bandwidth for 20Gb/s data while consuming only 138-mW.

Designer: George Ng

Technology: 0.13-um CMOS

This equalizer consumes only 30-mW from a 1.2-V supply and is capable of compensating for channel losses of more than 14-dB at one-half the data rate.

Designer:  Ahmad Darabiha

Technology:  0.13-um CMOS

This is the fastest iterative error control decoder reported to date.  It is also capable of decoding with only 150 pJ/bit.

A. Darabiha, A. Chan Carusone, and F. Kschischang, “Power Reduction Techniques for LDPC Decoders,” IEEE Journal of Solid-State Circuits, pp. 1835 - 1845, Aug. 2008. [PDF Format]

Designer:  Kentaro Yamamoto

Technology:  0.18-um CMOS

This design has a centre-frequency programmable from dc to 0.3f_s and a peak SNDR of 82 dB.

K. Yamamoto, A. Chan Carusone, and F. Dawson, “A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR,” IEEE Journal of Solid-State Circuits, pp. 1772 - 1782, Aug. 2008. [PDF Format]

Designer:  Masum Hossain

Technology:  90-nm CMOS

This is the highest-speed AC-coupled receiver reported to date with an integrated coupling capacitance below 100-fF.

M. Hossain and A. Chan Carusone, "A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS," VLSI Circuits Symposium, Kyoto, Japan, June 2007. [PDF Format]

Designer:  Masum Hossain

Technology:  0.18-um CMOS

With a gain of 10-dB, this amplifier has the highest measured bandwidth of any amplifier (with the exception of distributed amplifiers) ever reported in this technology.

M. Hossain and A. Chan Carusone, "A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS," Custom Integrated Circuits Conference, San Jose, California, September 2006. [PDF Format]

Designer:  Shahriar Shahramian

Technology:  0.13-um CMOS

With a 30-GHz clock frequency and 7-GHz bandwidth, this is the fastest track-and-hold amplifier ever reported in CMOS.  It has a measured THD of -29 dB.

Designer:  Faisal Musa

Technology:  0.18-um CMOS

This filter has a Q>3 and can be used for equalization and timing recovery at data rates above 3-Gb/s.

Designer:  Adesh Garg

Technology:  SiGe BiCMOS

This is the fastest DFE ever reported, tested up to 40-Gb/s.  It occupies an area of 1.5mmX1mm and operates from a 3.3V supply with 230mA current.

Designer:  Jonathan Sewter

Technology:  0.18-um CMOS

This is remains the fastest linear equalizer ever reported in any CMOS process.  It consumes 70 mW from a 1.8 V supply in an area 1 mm x 1 mm.

Designer:  Jonathan Sewter

Technology:  90-nm CMOS

At the time of its publication, this was the fastest linear equalizer reported in any CMOS technology.  Consuming only 25 mW from a 1-V supply, and fitting into an area 0.3 mm², the equalizer has a a serial digital interface to set the tap gains.