- DDR SDRAM Memory Organization Addressing memory in a DDR SDRAM memory dimm requires four separate addresses:
- Chip Select
- Bank Select
- Row Address
- Column Address
- DDR SDRAM Memory Reads Under construction
- DDR SDRAM Memory Writes Under construction
- Additional Information
In a DDR SDRAM dimm there are usually two memory chips connected in parallel, with only their chip enable signals being unique. This configuration allows the two chips to share address and data lines. By selectively asserting only one chip enable single at a time, this configuration allows twice the memory depth compared with only a signal chip. The highest level of the memory addressing hierarchy controls these chip enable signals. This addressing level is called the chip selects.
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The remaining three addressing levels all take place within a single memory chip. Figure 1 shows a simplified block diagram of the internals of a DDR SDRAM memory chip.
At the core of the memory chip are four 2D memory array banks. Each of these memory banks is addressed by both a row and column address. To understand why this memory structure was selected it is necessary to first understand the process of reading from one of the 2D memory arrays.
To read from the 2D memory array involves several steps. The first step involves selecting which row in the memory array to address. This is accomplished by issuing an ACTIVE command to the memory. This results in the memory array outputing an entire row of data via the sense amplifiers, shown in figure 1. At this point the memory chip is ready to accept read commands. These read commands include a column address, which is decoded and used to select which piece of data, currently outputted by the sense amplifiers, to read. Once the transaction is completed the 2D memory array can be returned to an idle state. This is accomplished by issuing a PRECHARGE command to the memory.
The need to both activate and precharge the 2D memory array means that data can not be transmitted on every clock cycle, since the memory bank is busy handling other tasks. In order to provide a method to mask the time required to activate and precharge the memory array, DDR SDRAM memory chips contain four independent banks of memory. The idea is that while a given bank is being activated or precharged, transactions can still occur on the remaining banks.
DDR SDRAM Memory Module Manufacturers
MicronCorsair
Elpida
Kingston Technology
Datasheets
Micron 512Mb DDR SDRAM chip datasheetMicron 1GB DDR SDRAM module datasheet
Applicable Application Notes
Micron TN-46-05 General DDR SDRAM FunctionalityMicron TN-46-07 DDR333 Memory Design Guide for 2-DIMM Unbuffered Systems
Other Relevent Documents
Micron DDR SDRAM Functionality and Controller Read Data CaptureMicron DDR SDRAM Timing Revision Information
Altera DDR SDRAM Controller MegaCore User Guide
Micron DDR System Design Consideration Slides
Fairchild DDR SDRAM Signaling Design Notes
SSTL-2 Termination Regulators
LP2995 National 1.5A DDR Termination RegulatorLP2996 National 1.5A DDR Linear Termination Regulator w/Shutdown
MAX1957 Maxim IC 4A DDR Switching Termination Regulator
- Kingston Technology Value RAM KVR400X72RC3A/1GD
- 1GB PC3200 REG CL3 ECC 184pin DIMM
- Verified to operated at upto 133Mhz on the TM-4
- Addressing Hierarchy
- Chip Select: 1 bit
- Bank Select: 2 bits
- Row Address: 13 bits
- Column Address: 11 bits
A short-form datasheet for the Kingston memory can be found here.
A long-form datasheet of a similar, but non identical, module can be found here .
Note: A newer DDR SDRAM controller is available here
The TM-4 example directory includes a DDR SDRAM controller circuit which is designed to abstract away most of the complexity involved in interfacing with DDR SDRAM. The core is optimized to perform block transfers of consecutive data and is not appropriate for random memory access patterns. Figure 2 shows a block diagram of the memory controller.
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The entire controller system contains four different parts: The DDR SDRAM memory controller logic, an arbitor, and two dual ported SRAM. The SRAMs are used as on-FPGA memory buffers and are the sole data communication channel with the DDR SDRAM. The arbitor allows user requests for reads and writes between the SRAMs and the DDR SDRAMs to be submitted to the memory controller logic, and the controller logic contains all the necessary circuitry to initialize the memory, perform refreshes, and perform burst transactions.
The SRAM buffers are both independent true dual ported buffers. This means that the clocks used to access these buffers need not be related to the highspeed DDR SDRAM clock, and in addition, these clocks need not be related to each other either. Although the output port of these buffers are both configured to 16384x36 in the example circuit, the arrangement could easily be changed to any other Quartus supported organization (ie 8192x72, etc).
The arbitor circuit is designed to transfer control requests from the user clock domain to the DDR SDRAM controllers clock domain, while also sharing access to the memory. The algorithm employed is one in which a request on interface A always is serviced before a request on interface B. There is no guarantee that interface B will ever gain access to the memory. Once again this could be easily changed by the user.
The control signals necessary to initiate a transaction between the SRAM and the DDR SDRAM are listed below:
- transrequestA : STD_LOGIC;
- transaction_completeA : STD_LOGIC;
- readwritenA : STD_LOGIC;
- ddr_addressA : STD_LOGIC_VECTOR(16 downto 0);
- ddr_start_blockA : STD_LOGIC_VECTOR(6 downto 0);
- ddr_end_blockA : STD_LOGIC_VECTOR(6 downto 0);
- sram_start_addressA : STD_LOGIC_VECTOR(11 downto 0);
- clockA : STD_LOGIC;
The first two signals are asynchronous handshaking signals. TransrequestA is asserted by the user circuit when they wish to request a transaction. This signal is held asserted until such time as the arbitor asserts its transaction_completeA signal. At this time the user should deassert its transrequestA signal and must wait until the transaction_completeA signal is deasserted by the memory controller before another transaction can be initiated.
The readwritenA signal specifies if the transaction is a read, if 1, or a write, if 0. The read/write is taken from the point of view of the DDR SDRAM. That is that a read means data is transfered from the DDR SDRAM to the on-FPGA SRAM buffer.
The ddr_* signals specify what range of DDR SDRAM memory to access. ddr_addressA is a combination of the chip select, bank select, and row addresses described in the previous section. It is used to address a single row of the DDR SDRAM. The remaining address, ddr_start_blockA, and ddr_end_blockA, specify the where to start and stop the transfer in the specified row. The unit in which ddr_*_block is expressed in is one of 16 DDR SDRAM words (16x72bits). This means that a single row is divided into 128 different blocks. Figure 3 summarizes the block division information.
| An Entire SDRAM DDR Row | 2048 x 72bits |
| Block Size | 16 x 72bits |
| Total Blocks per Row | 128 |
| Smallest Transfer (Single Block) |
1152 bits 144 bytes 8 memory cycles |
| Largest Transfer (128 Blocks) |
147456 bits 18432 bytes 1024 memory cycles |
The final control signal is the sram_start_addressA. This signal specifies what starting address in the SRAM to use for the requested transaction. This address is specified for the SRAM memory when configured in 4096x144 mode (since this is the mode that the DDR controller uses). To understand the mapping between the 144 bit wide port of the memory and the 36 bit wide user port consult the Altera documentation on dual ported memory.
One final note in regards to the sram_start_addressA is that it is up to the designer to insure that there is sufficient space in the SRAM buffer to contain the entire data transfered between the DDR SDRAM. What I mean by this is that it is possible to set the sram_start_addressA to the last word of the SRAM buffer but request that the DDR controller transfer multiple words. This will result in unpredictable behaviour. It is not safe to assume that the sram address will wrap around to zero again.
- Board revision A extracted PCB trace delay data
- Used SSTL-2 Class I Altera IBIS driver model
- Transfers from the FPGA->DIMM are measured from the 50% voltage crossing of the FPGA output pin until the 50% voltage crossing of the memory chips on the DIMM (as per the DDR specification).
- Transfers from the DIMM->FPGA are measured from the 50% voltage crossing of the memory chips until the input voltage at the FPGA crosses either the Vhigh or Vlow thresholds of the receiver pin.
- Delay timing numbers include the effects of cross talk
- Typical IBIS models where used to calculate delays
- Nominal PCB dimensions / characteristics where used
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