Advanced TM-4 Memory Data


Memory Bank 0B

Extracted PCB trace delay data (Assuming SSTL-2 Class I)

Table 1: DDR Bank 0B Board Timing Delays
NetMin DelayMax Delay
A[0]2.03ns2.56ns
A[1]1.99ns2.63ns
A[2]2.11ns2.69ns
A[3]2.07ns2.67ns
A[4]1.95ns2.75ns
A[5]1.88ns2.67ns
A[6]2.12ns2.69ns
A[7]1.82ns2.82ns
A[8]1.90ns2.70ns
A[9]2.03ns2.64ns
A[10]1.99ns2.79ns
A[11]2.07ns2.60ns
A[12]2.08ns2.68ns
A[13]?.??ns?.??ns
BA[0]2.13ns2.83ns
BA[1]2.09ns2.93ns
CASn2.03ns2.74ns
CLKE[0]1.32ns1.99ns
CLKE[1]1.42ns1.98ns
RASn2.11ns2.73ns
SN[0]1.58ns2.22ns
SN[1]1.64ns2.27ns
WEn2.00ns2.79ns
Control Group1.32ns2.82ns
Table 2: DDR Bank 0B Board Timing Delays
Net Min Delay
(D->F)
Max Delay
(D->F)
Min Delay
(F->D)
Max Delay
(F->D)
DQ[0]0.83ns1.14ns0.63ns0.81ns
DQ[1]0.89ns1.19ns0.66ns0.84ns
DQ[2]0.83ns1.13ns0.62ns0.80ns
DQ[3]0.85ns1.15ns0.64ns0.82ns
DQ[4]0.84ns1.14ns0.62ns0.80ns
DQ[5]0.88ns1.17ns0.64ns0.82ns
DQ[6]0.84ns1.13ns0.62ns0.80ns
DQ[7]0.84ns1.13ns0.62ns0.79ns
DQ[8]0.84ns1.14ns0.63ns0.82ns
DQ[9]0.83ns1.13ns0.62ns0.80ns
DQ[10]?.??ns?.??ns?.??ns?.??ns
DQ[11]0.83ns1.13ns0.62ns0.80ns
DQ[12]0.81ns1.11ns0.58ns0.76ns
DQ[13]0.83ns1.13ns0.62ns0.80ns
DQ[14]0.84ns1.14ns0.61ns0.79ns
DQ[15]0.84ns1.14ns0.62ns0.80ns
DQ[16]0.86ns1.16ns0.64ns0.83ns
DQ[17]0.87ns1.17ns0.65ns0.83ns
DQ[18]0.84ns1.14ns0.62ns0.80ns
DQ[19]0.82ns1.13ns0.62ns0.80ns
DQ[20]0.84ns1.14ns0.61ns0.79ns
DQ[21]0.86ns1.15ns0.63ns0.81ns
DQ[22]0.85ns1.14ns0.62ns0.80ns
DQ[23]0.84ns1.14ns0.62ns0.80ns
DQ[24]0.83ns1.13ns0.62ns0.81ns
DQ[25]0.85ns1.16ns0.63ns0.81ns
DQ[26]0.86ns1.16ns0.64ns0.81ns
DQ[27]0.83ns1.14ns0.62ns0.80ns
DQ[28]0.84ns1.14ns0.62ns0.80ns
DQ[29]0.84ns1.14ns0.62ns0.79ns
DQ[30]0.85ns1.15ns0.62ns0.80ns
DQ[31]0.84ns1.14ns0.62ns0.80ns
DQ[32]0.83ns1.13ns0.63ns0.81ns
DQ[33]0.84ns1.14ns0.62ns0.80ns
DQ[34]0.84ns1.14ns0.62ns0.80ns
DQ[35]0.84ns1.14ns0.63ns0.82ns
DQ[36]0.85ns1.15ns0.62ns0.80ns
DQ[37]0.84ns1.14ns0.62ns0.79ns
DQ[38]0.85ns1.15ns0.62ns0.80ns
DQ[39]0.84ns1.14ns0.62ns0.80ns
DQ[40]0.83ns1.14ns0.62ns0.80ns
DQ[41]0.84ns1.14ns0.62ns0.80ns
DQ[42]0.83ns1.14ns0.61ns0.79ns
DQ[43]0.83ns1.14ns0.63ns0.82ns
DQ[44]0.84ns1.14ns0.61ns0.79ns
DQ[45]0.83ns1.13ns0.61ns0.79ns
DQ[46]0.84ns1.13ns0.61ns0.79ns
DQ[47]0.84ns1.14ns0.62ns0.80ns
DQ[48]0.84ns1.14ns0.63ns0.81ns
DQ[49]0.83ns1.13ns0.61ns0.79ns
DQ[50]0.84ns1.14ns0.62ns0.80ns
DQ[51]0.83ns1.13ns0.63ns0.81ns
DQ[52]0.84ns1.14ns0.62ns0.79ns
DQ[53]0.83ns1.13ns0.62ns0.80ns
DQ[54]0.84ns1.14ns0.61ns0.79ns
DQ[55]0.84ns1.14ns0.62ns0.79ns
DQ[56]0.83ns1.13ns0.63ns0.81ns
DQ[57]0.85ns1.15ns0.63ns0.80ns
DQ[58]0.83ns1.13ns0.62ns0.79ns
DQ[59]0.83ns1.14ns0.62ns0.80ns
DQ[60]0.84ns1.14ns0.62ns0.80ns
DQ[61]0.86ns1.16ns0.64ns0.82ns
DQ[62]0.85ns1.15ns0.62ns0.80ns
DQ[63]0.84ns1.14ns0.62ns0.80ns
CB[0]0.83ns1.14ns0.62ns0.80ns
CB[1]0.83ns1.13ns0.62ns0.80ns
CB[2]0.84ns1.14ns0.62ns0.80ns
CB[3]0.83ns1.14ns0.63ns0.82ns
CB[4]0.86ns1.16ns0.63ns0.81ns
CB[5]0.85ns1.15ns0.63ns0.80ns
CB[6]0.84ns1.14ns0.62ns0.79ns
CB[8]0.86ns1.15ns0.63ns0.80ns
DQ Group0.81ns1.19ns 0.58ns0.84ns
Rev B
Target
0.82ns1.17ns 0.61ns0.83ns
Table 3: DDR Bank 0B Board Timing Delays
Net Min Delay
(D->F)
Max Delay
(D->F)
Min Delay
(F->D)
Max Delay
(F->D)
DQS[0]0.86ns1.17ns0.62ns0.80ns
DQS[1]0.86ns1.17ns0.62ns0.80ns
DQS[2]0.91ns1.22ns0.66ns0.84ns
DQS[3]0.86ns1.17ns0.61ns0.79ns
DQS[4]0.86ns1.17ns0.61ns0.79ns
DQS[5]0.88ns1.18ns0.63ns0.81ns
DQS[6]0.87ns1.17ns0.62ns0.80ns
DQS[7]0.86ns1.16ns0.61ns0.79ns
DQS[8]0.87ns1.17ns0.61ns0.79ns
DQS Group0.86ns1.22ns 0.61ns0.84ns
Rev B
Target
0.86ns1.18ns 0.61ns0.81ns
Table 4: DDR Bank 0B Board Timing Delays
NetMin DelayMax Delay
DM[0]0.61ns0.79ns
DM[1]0.64ns0.82ns
DM[2]0.63ns0.81ns
DM[3]0.64ns0.82ns
DM[4]0.62ns0.80ns
DM[5]0.62ns0.80ns
DM[6]0.62ns0.79ns
DM[7]0.65ns0.82ns
DM[8]0.62ns0.79ns
DM Group0.61ns0.82ns
Rev B
Target
0.61ns0.82ns
Table 5: DDR Bank 0B Board Timing Delays
NetMin DelayMax Delay
Clk[0]1.04ns1.33ns
Clk[1]1.26ns1.36ns
Clk[2]1.27ns1.41ns
Clock Group1.04ns1.41ns
Table 6: DDR Bank 0B Board Timing Delays
GroupMin DelayMax Delay
Control1.32ns2.82ns
DQ/DM/CB (D->F)0.81ns1.19ns
DQ/DM/CB (F->D)0.58ns0.84ns
DQS (D->F)0.86ns1.22ns
DQS (F->D)0.61ns0.84ns
Clock1.04ns1.41ns