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clk

clock_source v10.0

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cpu

altera_nios2 v10.0

Parameters userDefinedSettings setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave mem.s1 resetOffset 0 muldiv_multiplierType DSPBlock muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false internalIrqMaskSystemInfo 0 instSlaveMapParam instAddrWidth 1 impl Fast icache_size _0 icache_ramBlockType Automatic icache_numTCIM _1 icache_burstType None exceptionSlave mem.s1 exceptionOffset 32 deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 1 MRAM_MEMORY 0 MLAB_MEMORY 1 ESB 0 EPCS 1 DSP 1 EMUL 0 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 1 deviceFamilyName Stratix III debug_triggerArming true debug_level NoDebug debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _0 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _1 dcache_lineSize _32 dcache_bursts false dataSlaveMapParam <address-map><slave name='ISP1761.slave' start='0x0' end='0x100000' /><slave name='ports.slave' start='0x102000' end='0x102040' /></address-map> dataAddrWidth 21 cpuReset false cpuID 0 clockFrequency 50000000 breakSlave mem.s1 breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 50000000u ICACHE_LINE_SIZE 0 ICACHE_LINE_SIZE_LOG2 0 ICACHE_SIZE 0 DCACHE_LINE_SIZE 0 DCACHE_LINE_SIZE_LOG2 0 DCACHE_SIZE 0 FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x400020 RESET_ADDR 0x400000 BREAK_ADDR 0x400020 HAS_DEBUG_STUB HAS_DEBUG_CORE 0 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 1 INST_ADDR_WIDTH 23 DATA_ADDR_WIDTH 23 NUM_OF_SHADOW_REG_SETS 0

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mem

altera_avalon_onchip_memory2 v10.0

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 deviceFamily Stratix III dualPort true initMemContent true initializationFileName mem instanceID NONE memorySize 6144 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "mem" NON_DEFAULT_INIT_FILE_ENABLED 0 GUI_RAM_BLOCK_TYPE "Automatic" WRITABLE 1 DUAL_PORT 1 SIZE_VALUE 6144u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "Auto" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

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ISP1761

ISP1761 v1.0

Parameters AUTO_GLOBAL_CLOCK_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Stratix III deviceFamily Stratix III generateLegacySim false

  

Software Assignments (none)

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ports

usb_portmux_iface v1.0

Parameters AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Stratix III deviceFamily Stratix III generateLegacySim false

  

Software Assignments (none)