Ph.D. Dissertation

M. van Ierssel, Circuit Techniques for High-Speed Serial and Backplane Signaling , University of Toronto, 2007.

Papers

M. van Ierssel, H. Yamaguchi, A. Sheikholeslami, H. Tamura, and W.W. Walker Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI, IEEE Trans. Circuits and Systems I (TCAS-I), Vol 55, issue 10, pp. 1306-1315, June 2008

M. van Ierssel, A. Sheikholeslami, H. Tamura, W.W. Walker A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance, IEEE J. Solid-State Circuits (JSSC), vol. 42, issue 10, pp. 2224-2234, Oct. 2007.

R. Yuen, M. van Ierssel, A. Sheikholeslami, W.W. Walker, and H. Tamura A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers, IEEE Custom Integrated Circuits Conference (CICC), pp. 413-416, Sept. 2006.

M. van Ierssel, A. Sheikholeslami, H. Tamura, and W.W. Walker, A 3.2Gb/s Semi-Blind-Oversampling CDR, IEEE ISSCC Dig. Tech. Papers, pp. 334-335, Feb. 2006.

M. van Ierssel, J. Wong, and A. Sheikholeslami, An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling, IEEE Proceedings of the International SOC Conference, pp. 297-300, Sept. 2004.

M. van Ierssel, T. Esmailian, A. Sheikholeslami, and P.S. Pasupathy, Signaling capacity of FR4 PCB traces for chip-to-chip communication, Proceedings of the International Symposium on Circuits and Systems (ISCAS), vol. 5, pp. V85-V88, May 2003.

M. van Ierssel and A. Sheikholeslami, Circuit Techniques for High-Speed Chip-to-Chip Signaling, Proceedings of International Symposium on New Paradigm VLSI Computing pp. 52-55, Dec. 2002.

D.M. Lewis, D.R. Galloway, M. van Ierssel, J. Rose, and P. Chow, The Transmogrifier-2: a 1 million gate rapid-prototyping system, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 6, issue 2, pp. 188-198, June 1998.

D. M. Lewis, M. van Ierssel, and D.H. Wong, A field programmable accelerator for compiled-code applications, IEEE Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD), pp. 491-496, Oct. 1993.

D.M. Lewis, M. van Ierssel, and D.H. Wong, A field programmable accelerator for compiled-code applications, IEEE Proceedings of the Workshop on FPGAs for Custom Computing Machines (FCCM), pp. 60-67, April 1993.

Patents

H. Tamura, H. Yamaguchi, M. van Ierssel Circuit analysis method and circuit analysis apparatus, , US Patent Application No. 20060047494, filed on Aug. 30, 2004.

1