Vaughn Betz -- Home Page

Vaughn Betz

Academic Bio

In late 1998 I finished my Phd in the Department of Electrical and Computer Engineering at the University of Toronto under the supervision of Professor Jonathan Rose. My research consisted of developing advanced CAD tools for placement and routing in FPGAs and devising logic block and routing architectures which improve the speed and density of FPGAs.

Since I finished my PhD I've been working on FPGA CAD and architecture commercially. In late 1998 I co-founded Right Track CAD Corp., which was acquired by Altera Corp. in May 2000. So now I'm a member of Altera's Toronto Technology Centre.

Aside from FPGAs and CAD, my other main research interests are computer architecture and VLSI design, particularly microprocessor, memory and graphics subsystem architecture.

In what now seems a former life, I spent a lot of time (sixteen months at a commercial CAD company, and a Master's Degree) writing electromagnetic field solvers for the analysis of various structures, particularly circuit boards and chip packaging at very high frequencies. One of the more interesting field solvers I worked on was a program to analyze the half-mile tall antennas used to communicate with submerged submarines (very low frequencies!).

I received my M.S. degree from the University of Illinois at Urbana-Champaign in 1993, and my B.Sc. from the University of Manitoba in 1991, from the Department of Electrical and Computer Engineering in each case.

Email

v b e t z (at) altera.com [delete spaces and use real @]

Free Software:

VPR: A placement and routing tool for FPGA research. (Also includes the T-VPACK FPGA logic block packing program). Latest version: 4.30. Includes timing-driven packing, placement and routing.
New utility available: nettovqm converts a VPR format netlist to the format needed by Altera's Quartus CAD suite, letting you interface VPack output to a commercial CAD system.
VPR is part of the SPEC 2000 suite of computer benchmarks (the standard benchmarks used to determine the speed of various workstations). This let's me check how fast VPR runs on pretty much every type of computer hardware, which is pretty cool.

EasyGL: An easy-to-use graphics interface for programming X11, PostScript, and now Win32 displays.

The "FPGA Place-and-Route Challenge":

A contest for the FPGA community: compare the routing area achieved by your CAD tools against the best results reported thus far.

Books and Book Chapters

Architecture and CAD for Deep-Submicron FPGAs, V. Betz, J. Rose, and A. Marquardt, Kluwer Academic Publishers, February 1999. 264 pages.
ISBN 0-7923-8460-1

This book covers the research of Jonathan Rose, Alexander (Sandy) Marquardt and myself into both FPGA architecture and Computer-Aided Design tools. As well, Architecture and CAD for Deep-Submicron FPGAs explains and explores the circuit and layout issues that are crucial in the design of real-world FPGAs. Read the text from the back cover of the book.

Order online from Springer.com.

V. Betz, "Placement for General Purpose FPGAs," Chapter 14, in Reconfigurable Computing, A. DeHon and S. Hauck, Eds., Morgan Kauffman, 2007.
M. Hutton and V. Betz, "FPGA Synthesis and Physical Design," Volume 1, Chapter 13, in Electronic Design Automation for Integrated Circuits Handbook, L. Scheffer, L. Lavagno, and G. Martin, Eds., Taylor and Francis CRC Press, 2006, pp. 13-1 to 13-32.

Journal and Conference Papers:

R. Fung, V. Betz, and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations," IEEE Trans. on Computer-Aided Design of Circuits and Systems, April 2008, pp. 686 - 697. [Abstract] [PDF]
A. Ludwin, V. Betz and K. Padalia, "High-Quality, Deterministic Parallel Placement for FPGAs on Commodity Hardware," ACM / Sigda Int. Symp. on FPGAs, 2008, pp. 14 - 23. [Abstract] [PDF]
R. Tessier, V. Betz, D. Neto, A. Egier and T. Gopalsamy, "Power-efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks," IEEE Trans. on Computer-Aided Design of Circuits and Systems, Feb. 2007, pp. 278 - 290. [Abstract] [PDF]
R. Tessier, V. Betz, D. Neto and T. Gopalsamy, "Power-Aware RAM Mapping for FPGA Embedded Memory Blocks," ACM/Sigda International Symposium on Field Programmable Gate Arrays, 2006, pp. 189 - 198. [Abstract] [PDF]
D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff and J. Rose, "The Stratix II Logic and Routing Architecture," ACM/Sigda International Symposium on Field Programmable Gate Arrays, 2005, pp. 14 - 20. [Abstract] [PDF]
R. Fung, V. Betz and W. Chow, "Simultaneous Short-Path and Long-Path Timing Optimization for FPGAs," IEEE International Conference on Computer-Aided Design, November 2004, 838 - 845. [Abstract] [PDF]
D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, S. Marquardt, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff and J. Rose, ``The Stratix Routing and Logic Architecture,'' ACM/Sigda International Symposium on Field-Programmable Gate Arrays, February 2003, pp. 12 - 20. [Abstract] [PDF]
A. Marquardt, V. Betz and J. Rose, ``Speed and Area Tradeoffs in Cluster-Based FPGA Architectures,'' IEEE Transactions on VLSI Systems, February 2000, pp. 84 - 93. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``Automatic Generation of FPGA Routing Architectures from High-Level Descriptions,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 175 - 184. [Abstract] [PDF] [Gzipped Postscript]
A. Marquardt, V. Betz and J. Rose, ``Timing-Driven Placement for FPGAs,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 203 - 213. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect,'' IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1999, pp. 171 - 174. [Abstract] [PDF] [Gzipped PostScript]
V. Betz and J. Rose, ``FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density,''ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 59 - 68. [Abstract] [PDF] [Gzipped Postscript]
A. Marquardt, V. Betz and J. Rose, ``Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 37 - 46. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency,'' IEEE Transactions on VLSI Systems, September 1998, pp. 445 - 456. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``How Much Logic Should Go in an FPGA Logic Block?,'' IEEE Design and Test Magazine, Spring 1998, pp. 10 - 15. [Abstract] [PDF] [Gzipped Postscript]
J. Swartz, V. Betz and J. Rose, ``A Fast Routability-Driven Router for FPGAs,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, 1998, pp. 140 - 149. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``VPR: A New Packing, Placement and Routing Tool for FPGA Research,'' Seventh International Workshop on Field-Programmable Logic and Applications, London, UK, 1997, pp. 213 - 222. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size,'' IEEE Custom Integrated Circuits Conference, Santa Clara, CA, 1997, pp. 551 - 554. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,'' IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 1996, pp. 652 - 659. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and J. Rose, ``Using Architectural Families to Increase FPGA Speed and Density,'' ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, 1995, pp. 10 - 16. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and R. Mittra, ``A Boundary Condition to Absorb Both Propagating and Evanescent Waves in a Finite-Difference Time-Domain Simulation,'' IEEE Microwave and Guided Wave Letters, June 1993, pp. 182 - 184.
V. Betz and R. Mittra, ``Comparison and Evaluation of Boundary Conditions for the Absorption of Guided Waves in an FDTD Simulation,'' IEEE Microwave and Guided Wave Letters, Dec. 1992, pp. 499 - 501.
V. Betz, N. P. East and A. Sebak, ``Applications of Planar Near-Field Measurements to Electromagnetic Radiation and Interference Problems,'' Canadian Conference on Electrical and Computer Engineering, Montreal, PQ, 1991, pp. 72.1.1 - 72.1.4.

Theses and Technical Reports:

V. Betz and J. Rose, ``Architecture and CAD for the Speed and Area Optimization of FPGAs,'' Ph.D. Dissertation University of Toronto, 1998.
V. Betz and J. Rose, ``On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs,'' CSRI Technical Report #358, Department of Electrical and Computer Engineering, University of Toronto, 1996. [Abstract] [PDF] [Gzipped Postscript]
V. Betz and R. Mittra, ``Absorbing Boundary Conditions for the Finite-Difference Time-Domain Analysis of Guided-Wave Structures,'' M.S. Thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1993.
V. Betz, N. P. East, and A. Sebak, ``Calculation of Far-Field Radiation Pattern from Near-Field Antenna Measurements,'' B.Sc. Thesis, Department of Electrical and Computer Engineering, University of Manitoba, 1991.

Interesting Courses:

TRPOS: A 56 000 transistor full-custom VLSI design.

Integrated Circuit Fabrication: A wafer I processed and patterned from initial degreasing (cleaning) to final metallization and performance test.

The Package Deal:

A quantum leap in collective bargaining!

Photo Album

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