.input my_pad
pinlist: my_net
The lines above indicate that there is an input pad named my_pad which drives a net called my_net. Pads can have the same name as signal nets with no conflicts.
.input alpha
pinlist: alpha # No conflict between pad and net name.
.output my_opad
pinlist: some_net
The lines above declare a pad named my_opad. It is connected to net some_net.
.clb my_logic_block
pinlist: in_a in_b in_c in_d out_net clk
subblock: sb_one 0 1 2 3 4 5 # Ignore this line.
Recall that the logic block contains a 4-input LUT and a flip flop. The lines above declare a logic block named my_logic_block. The pinlist line lists the nets connected to this logic block. The nets connected to the four LUT inputs are listed first, followed by the net connected to the logic block output and then the net connected to the logic block clock pin. The subblock line gives information that is useful for timing analysis -- for the purposes of the place-and-route challenge it is irrelevant and should be completely ignored.
A logic block may not need signals connected to all of its LUT inputs or to its clock pin. In this case the unconnected pins are marked as open.
.clb my_logic_block
pinlist: in_a open open in_d out_net open
# Only 2 LUT inputs, no clock
subblock: sb_one 0 1 2 3 4 5 # Ignore this line.
Global signals are indicated in the netlist file by .global lines:
.global clk # Don't route clk net.
For the place-and-route challenge, the only net marked as global is the clock net.
All the following lines have the format:
block_name x y subblock_number
The block name is the name of this block, as given in the input netlist. X and y are the row and column in which the block is placed, respectively. The subblock number is meaningful only for pads. Since we can place two pads in a row or column (see the FPGA architecture description) the subblock number specifies which of the possible pad locations (either location 0 or location 1) in row x and column y contains this pad. Note that the first pad occupied at some (x, y) location is always that with subblock number 0. For logic blocks (.clbs), the subblock number is always zero.
The placement files output by VPR also include a fifth field as a comment. You can ignore this field.
The figure below shows the coordinate system used by VPR via a small 2 x 2 (logic block array) FPGA. Logic blocks all go in the area with x between 1 and 2 and y between 1 and 2, inclusive. All pads either have x equal to 0 or 3 or y equal to 0 or 3. Notice that there are no pads in the chip corners, so no I/O pins can be placed there.
A sample placement file is given below. The first six blocks are I/O pads, while the last two blocks are logic blocks.
Netlist file: xor5.net Architecture file: sample.arch
Array size: 2 x 2 logic blocks
#block name x y subblk block number
#---------- -- -- ------ ------------
a 0 1 0 #0 NB: block number
b 1 0 0 #1 is a comment.
c 0 2 1 #2 Ignore it.
d 1 3 0 #3
e 1 3 1 #4
out:xor5 0 2 0 #5
xor5 1 2 0 #6
[1] 1 1 0 #7