The VPR routing file format is described below. If you wish, you can use it as your output file format for the FPGA challenge. For the FPGA challenge it is not necessary to output any routing for global nets.

VPR Routing File Format (.r)

The first line of the routing file gives the array size, nx x ny. The remainder of the routing file lists the global or the detailed routing for each net, one by one. Each routing begins with the word net, followed by the net index used internally by VPR to identify the net and, in brackets, the name of the net given in the netlist file. The following lines define the routing of the net. Each begins with a keyword that identifies a type of routing segment. The possible keywords are SOURCE (the source of a certain output pin class), SINK (the sink of a certain input pin class), OPIN (output pin), IPIN (input pin), CHANX (horizontal channel), and CHANY (vertical channel). Each routing begins on a SOURCE and ends on a SINK. In brackets after the keyword is the (x, y) location of this routing resource. Finally, the pad number (if the SOURCE, SINK, IPIN or OPIN was on an I/O pad), pin number (if the IPIN or OPIN was on a clb), class number (if the SOURCE or SINK was on a clb) or track number (for CHANX or CHANY) is listed -- whichever one is appropriate. The meaning of these numbers should be fairly obvious in each case. If we are attaching to a pad, the pad number given for a resource is the subblock number defining to which pad at location (x, y) we are attached. See Figure 10 for a diagram of the coordinate system used by VPR. In a horizontal channel (CHANX) track 0 is the bottommost track, while in a vertical channel (CHANY) track 0 is the leftmost track. Note that if only global routing was performed the track number for each of the CHANX and CHANY resources listed in the routing will be 0, as global routing does not assign tracks to the various nets.

For an N-pin net, we need N-1 distinct wiring “paths” to connect all the pins. The first wiring path will always go from a SOURCE to a SINK. The routing segment listed immediately after the SINK is the part of the existing routing to which the new path attaches. It is important to realize that the first pin after a SINK is the connection into the already specified routing tree; when computing routing statistics be sure that you do not count the same segment several times by ignoring this fact. An example routing for one net is listed below.

Net 5 (xor5)

SOURCE (1,2)  Class: 1        # Source for pins of class 1.
  OPIN (1,2)  Pin: 4
 CHANX (1,1)  Track: 1
 CHANX (2,1)  Track: 1
  IPIN (2,2)  Pin: 0
  SINK (2,2)  Class: 0        # Sink for pins of class 0 on a clb.
 CHANX (1,1)  Track: 1        # Note:  Connection to existing routing!
 CHANY (1,2)  Track: 1
 CHANX (2,2)  Track: 1
 CHANX (1,2)  Track: 1
  IPIN (1,3)  Pad: 1
  SINK (1,3)  Pad: 1       # This sink is an output pad at (1,3), subblock 1.
Global net routing does not have to be output for the FPGA Challenge, so you can skip the description below if you are only interested in the FPGA challenge.

Nets which are specified to be global in the netlist file (generally clocks) are not routed. Instead, a list of the blocks (name and internal index) which this net must connect is printed out. The location of each block and the class of the pin to which the net must connect at each block is also printed. For clbs, the class is simply whatever class was specified for that pin in the architecture input file. For pads the pinclass is always -1; since pads do not have logically-equivalent pins, pin classes are not needed. An example listing for a global net is given below.

Net 146 (pclk): global net connecting:
Block pclk (#146) at (1, 0), pinclass -1.
Block pksi_17_ (#431) at (3, 26), pinclass 2.
Block pksi_185_ (#432) at (5, 48), pinclass 2.
Block n_n2879 (#433) at (49, 23), pinclass 2.

Back to the FPGA challenge main page.