This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, and its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures within the logic array block, and logic element features are described.
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