%! %%BoundingBox: (atend) %%Pages: (atend) %%DocumentFonts: (atend) %%EndComments % % FrameMaker PostScript Prolog 3.0, for use with FrameMaker 3.0 % Copyright (c) 1986,87,89,90,91 by Frame Technology Corporation. % All rights reserved. % % Known Problems: % Due to bugs in Transcript, the 'PS-Adobe-' is omitted from line 1 /FMversion (3.0) def % Set up Color vs. Black-and-White /FMPrintInColor systemdict /colorimage known systemdict /currentcolortransfer known or def % Uncomment this line to force b&w on color printer % /FMPrintInColor false def /FrameDict 195 dict def systemdict /errordict known not {/errordict 10 dict def errordict /rangecheck {stop} put} if % The readline in 23.0 doesn't recognize cr's as nl's on AppleTalk FrameDict /tmprangecheck errordict /rangecheck get put errordict /rangecheck {FrameDict /bug true put} put FrameDict /bug false put mark % Some PS machines read past the CR, so keep the following 3 lines together! currentfile 5 string readline 00 0000000000 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pop /cf currentfile def w h 8 [w 0 0 h neg 0 h] {ip} {gip} {bip} true 3 colorimage bitmapsave restore grestore } bind def /BITMAPTRUECOLOR { gsave translate rotate scale /h exch def /w exch def /bitmapsave save def /is w string def /gis w string def /bis w string def /cf currentfile def w h 8 [w 0 0 h neg 0 h] { cf is readhexstring pop } { cf gis readhexstring pop } { cf bis readhexstring pop } true 3 colorimage bitmapsave restore grestore } bind def /BITMAPTRUEGRAYc { gsave translate rotate scale /h exch def /w exch def /bitmapsave save def /is w string def ws 0 w getinterval is copy pop /cf currentfile def w h 8 [w 0 0 h neg 0 h] {ip gip bip w gray} image bitmapsave restore grestore } bind def /ww FMLOCAL /r FMLOCAL /g FMLOCAL /b FMLOCAL /i FMLOCAL /gray { /ww exch def /b exch def /g exch def /r exch def 0 1 ww 1 sub { /i exch def r i get .299 mul g i get .587 mul b i get .114 mul add add r i 3 -1 roll floor cvi put } for r } bind def /BITMAPTRUEGRAY { gsave translate rotate scale /h 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Each FPGA family is tar) 54 567.17 P 0.87 (geted at a single) 225.72 567.17 P -0 (maximum logic capacity) 54 555.17 P -0 (, and consists of several \322siblings\323,) 151.15 555.17 P -0.04 (or FPGAs of differ) 54 543.17 P -0.04 (ent yet complementary ar) 128.75 543.17 P -0.04 (chitectur) 230.13 543.17 P -0.04 (es. Any) 265.29 543.17 P 0.63 (given application cir) 54 531.17 P 0.63 (cuit is implemented in the sibling with) 138.18 531.17 P -0.23 (the most appr) 54 519.17 P -0.23 (opriate ar) 108.15 519.17 P -0.23 (chitectur) 147.81 519.17 P -0.23 (e. W) 182.97 519.17 P -0.23 (ith pr) 199.95 519.17 P -0.23 (operly chosen sib-) 221.29 519.17 P 0.83 (lings, one can develop a family of FPGAs which will have) 54 507.17 P 1.12 (better speed and density than any single FPGA. W) 54 495.17 P 1.12 (e apply) 263.86 495.17 P 2.52 (this concept to cr) 54 483.17 P 2.52 (eate two differ) 130.31 483.17 P 2.52 (ent FPGA families, one) 192.73 483.17 P -0.05 (composed of ar) 54 471.17 P -0.05 (chitectur) 115.14 471.17 P -0.05 (es with differ) 150.31 471.17 P -0.05 (ent types of har) 202.03 471.17 P -0.05 (d-wir) 263.4 471.17 P -0.05 (ed) 284.68 471.17 P 1.12 (logic blocks and the other cr) 54 459.17 P 1.12 (eated fr) 173.88 459.17 P 1.12 (om ar) 205.45 459.17 P 1.12 (chitectur) 229.79 459.17 P 1.12 (es with) 264.95 459.17 P 0.28 (differ) 54 447.17 P 0.28 (ent types of heter) 75.29 447.17 P 0.28 (ogeneous logic blocks. W) 144.31 447.17 P 0.28 (e found that) 245.81 447.17 P 0.8 (a family composed of eight chips with differ) 54 435.17 P 0.8 (ent har) 234.38 435.17 P 0.8 (d-wir) 263.4 435.17 P 0.8 (ed) 284.68 435.17 P 1.89 (logic block ar) 54 423.17 P 1.89 (chitectur) 112.92 423.17 P 1.89 (es simultaneously impr) 148.09 423.17 P 1.89 (oves density) 243.66 423.17 P 0.68 (by 12 to 14% and speed by 18 to 20% over the best single) 54 411.17 P (har) 54 399.17 T (d-wir) 67.51 399.17 T (ed FPGA.) 88.8 399.17 T 1 12 Q (1 Intr) 54 373.83 T (oduction) 83.43 373.83 T 0 10 Q 2.72 (Designing hardware with Field-Programmable Gate) 75.6 355.17 P 0.88 (Arrays \050FPGAs\051 avoids the higher non-recurring engineer-) 54 343.17 P 3.65 (ing costs and longer development times of Mask-Pro-) 54 331.17 P 2.18 (grammed Gate Array \050MPGA\051 solutions. These two key) 54 319.17 P 1.76 (advantages, shorter design cycles and lower development) 54 307.17 P 0.83 (costs, have made FPGAs an extremely popular technology) 54 295.17 P 0.39 (for prototyping and low-volume production runs. However) 54 283.17 P 0.39 (,) 291.62 283.17 P 0.87 (the reprogrammability that allows such rapid and inexpen-) 54 271.17 P -0.06 (sive development exacts a cost; typically the speed and den-) 54 259.17 P 3.19 (sity of logic implemented in an FPGA is an order of) 54 247.17 P 3.16 (magnitude lower than that of logic implemented in an) 54 235.17 P 0.59 (MPGA [1]. This speed disadvantage makes FPGAs unsuit-) 54 223.17 P 0.3 (able for a lar) 54 211.17 P 0.3 (ge portion of hardware projects, while the area) 105.5 211.17 P 0.17 (penalty makes FPGAs more expensive than MPGAs for the) 317.88 614 P (high-volume implementation of a hardware component.) 317.88 602 T 0.78 (W) 339.48 584 P 0.78 (e propose a method by which these speed and den-) 348.11 584 P 0.07 (sity disadvantages can be reduced. An FPGA architecture is) 317.88 572 P 0.08 (normally selected so that it can implement the lar) 317.88 560 P 0.08 (gest possi-) 515.44 560 P 1.76 (ble class of application circuits as ef) 317.88 548 P 1.76 (\336ciently as possible.) 473.14 548 P 1.08 (This means that the FPGA must contain enough program-) 317.88 536 P 1.08 (mable switches and routing resources to give) 317.88 524 P 2 F 1.08 (any) 507.8 524 P 0 F 1.08 ( applica-) 522.23 524 P 0 (tion circuit a reasonable chance of successfully routing. The) 317.88 512 P 0.58 (vast majority of circuits will utilize only a small portion of) 317.88 500 P -0.23 (these routing switches, but since dif) 317.88 488 P -0.23 (ferent circuits use dif) 459.79 488 P -0.23 (fer-) 543.58 488 P -0.15 (ent switches, reducing the \337exibility of the FPGA by replac-) 317.88 476 P 2.27 (ing some of these switches with metal links is dif) 317.88 464 P 2.27 (\336cult.) 534.95 464 P 2.06 (Some application circuits would \336t into this less-\337exible) 317.88 452 P 0.28 (FPGA very well, and would be smaller and faster than they) 317.88 440 P 0.74 (would have been on the original chip. Other circuits, how-) 317.88 428 P 3.11 (ever) 317.88 416 P 3.11 (, might have made good use of the programmable) 334.68 416 P 1.1 (resources that have been removed, and will now be lar) 317.88 404 P 1.1 (ger) 545.24 404 P 1.67 (and/or slower than they would have been on the original) 317.88 392 P (chip.) 317.88 380 T 3.16 (If, however) 339.48 362 P 3.16 (, one manufactures a) 388.31 362 P 2 F 3.16 (family) 486.17 362 P 0 F 3.16 ( of related) 511.15 362 P 0.8 (FPGA architectures, one can have the best of both worlds.) 317.88 350 P -0.23 (The FPGA) 317.88 338 P 2 F -0.23 (family) 363.5 338 P 0 F -0.23 ( is a group of chips, each of which is based) 388.49 338 P 0.51 (on a somewhat dif) 317.88 326 P 0.51 (ferent FPGA architecture, and each indi-) 392.8 326 P 1.61 (vidual chip in this family is called a) 317.88 314 P 2 F 1.61 (sibling) 476.2 314 P 0 F 1.61 (. All siblings) 503.42 314 P 4.17 (have equivalent maximum logic capacities. Instead of) 317.88 302 P 0.38 (attempting to implement all application circuits in one very) 317.88 290 P 1.76 (\337exible FPGA chip, we use the most suitable sibling for) 317.88 278 P 0.34 (each application circuit. Each sibling is tailored to a certain) 317.88 266 P 0.09 (class of application circuits in some way -- say by replacing) 317.88 254 P 6.33 (many programmable switches with hard-wired links) 317.88 242 P 0.07 (between logic blocks and by using longer routing segments.) 317.88 230 P 0.24 (This sibling implements certain circuits very ef) 317.88 218 P 0.24 (\336ciently) 507.88 218 P 0.24 (, but) 539.99 218 P 2.74 (its reduced \337exibility means that some circuits may no) 317.88 206 P 0.3 (longer \336t into it at all. W) 317.88 194 P 0.3 (e overcome this reduced \337exibility) 418 194 P 1.7 (by choosing the architecture of the remaining siblings so) 317.88 182 P 1.38 (that they can ef) 317.88 170 P 1.38 (\336ciently implement any circuit which will) 383.16 170 P 0.72 (not \336t into this chip well. W) 317.88 158 P 0.72 (ith good choices for the archi-) 434.23 158 P 0.13 (tecture of each chip, a small number of siblings will be able) 317.88 146 P 0.34 (to implement any application circuit more ef) 317.88 134 P 0.34 (\336ciently than a) 497.92 134 P (single highly \337exible FPGA.) 317.88 122 T 0.96 (Since a single FPGA is suf) 339.48 104 P 0.96 (\336cient for prototyping but) 451.56 104 P 1.26 (even a small production run may require 50 chips, FPGA) 317.88 92 P 1.43 (revenues come primarily from sales of chips intended for) 317.88 80 P 54 638 558 738 R 7 X V 0 15 Q 0 X (Using Architectural \322Families\323 to Increase FPGA Speed and Density) 98.54 728 T 0 12 Q (V) 228.72 707 T (aughn Betz and Jonathan Rose) 236.05 707 T (University of T) 253.79 693 T (oronto) 326.9 693 T (T) 254.46 679 T (oronto, ON, Canada) 260.95 679 T (M5S 1A4) 282.51 665 T (vaughn@eecg.toronto.edu) 242.85 651 T 54 135 294 187.5 R 7 X V 0 10 Q 0 X (_________________________) 54 180.83 T 0.05 (This work was supported by the Natural Sciences and Engi-) 54 162.83 P (neering Research Council of Canada and MICRONET) 54 150.83 T (.) 271.43 150.83 T FMENDPAGE %%EndPage: "1" 2 %%Page: "2" 2 612 792 0 FMBEGINPAGE 279 38.14 315 54 R 7 X 0 K V 0 10 Q 0 X (2) 300.6 47.33 T 0.16 (use in production hardware. This is precisely where the sib-) 54 731.33 P 1.19 (lings concept would be of the greatest use. As part of the) 54 719.33 P 2.22 (synthesis procedure, the CAD software would determine) 54 707.33 P 0.35 (not only the technology mapping, placement and routing of) 54 695.33 P 0.81 (the circuit, but also the best sibling to use. Since each sib-) 54 683.33 P 1.12 (ling should be smaller \050and hence cheaper\051 than a general) 54 671.33 P 1.02 (purpose FPGA, the production volume at which it is cost-) 54 659.33 P 3.32 (ef) 54 647.33 P 3.32 (fective to switch to mask programmed logic will be) 61.59 647.33 P 0.99 (increased. As well, the higher speed of siblings will allow) 54 635.33 P 3.38 (the FPGA implementation of circuits which previously) 54 623.33 P 2.27 (could not meet performance speci\336cations without using) 54 611.33 P (custom or semi-custom logic.) 54 599.33 T 2.01 (The structure of this paper is as follows. Section 2) 75.6 581.33 P 0.16 (examines the relationship between FPGAs and MPGAs and) 54 569.33 P 3.37 (shows that the sibling concept lies between these two) 54 557.33 P 0.65 (extrema in the architectural spectrum. In Section 3 the sib-) 54 545.33 P 0.81 (lings concept is applied to create a family of FPGAs com-) 54 533.33 P 5.9 (posed of dif) 54 521.33 P 5.9 (ferent types of hard-wired logic block) 113.36 521.33 P 0.64 (architectures, and the performance gains are assessed. Sec-) 54 509.33 P 0.56 (tion 4 conducts a similar experiment in which the architec-) 54 497.33 P 0.48 (tures in the family contain dif) 54 485.33 P 0.48 (ferent types of heterogeneous) 174.74 485.33 P 0.74 (logic blocks. Finally) 54 473.33 P 0.74 (, we summarize our \336ndings and draw) 136.74 473.33 P (some conclusions in Section 5.) 54 461.33 T 1 12 Q (2 The Siblings Concept) 54 418 T 0 10 Q 1.3 (The basic idea of siblings is to create FPGAs which) 75.6 399.33 P 3.73 (have higher performance and are smaller than current) 54 387.33 P 1.09 (FPGAs by removing some of their \337exibility) 54 375.33 P 1.09 (, i.e. some of) 239.23 375.33 P 0.46 (their programmable switches. The \337exibility removed from) 54 363.33 P 0.19 (each individual sibling is recovered by having the choice of) 54 351.33 P 0.27 (several dif) 54 339.33 P 0.27 (ferent siblings in which to implement an applica-) 95.99 339.33 P (tion circuit.) 54 327.33 T 2.1 (It is instructive to consider the dif) 75.6 309.33 P 2.1 (ferences between) 222.93 309.33 P 1.08 (MPGAs and FPGAs in order to see how the siblings con-) 54 297.33 P 1.28 (cept \336ts into the spectrum of circuit implementation tech-) 54 285.33 P 2.02 (nologies. A single FPGA can implement any application) 54 273.33 P 0.11 (circuit \050subject only to size constraints\051, so only one type of) 54 261.33 P 1.7 (FPGA is needed. A fully-fabricated MPGA, on the other) 54 249.33 P 1.36 (hand, implements exactly one circuit, so a new MPGA is) 54 237.33 P 0.63 (required for each new application. The MPGA achieves its) 54 225.33 P 1.95 (higher speed and smaller area by using small, low-delay) 54 213.33 P 0.27 (wires rather than lar) 54 201.33 P 0.27 (ger and slower programmable intercon-) 134.84 201.33 P 2.71 (nect, and by only laying out the interconnect resources) 54 189.33 P 2.16 (required by this circuit. W) 54 177.33 P 2.16 (e view these two solutions as) 167.02 177.33 P 0.2 (extremes in a spectrum of possible implementation choices,) 54 165.33 P -0.09 (as Figure 1 shows. The idea of an FPGA family allows us to) 54 153.33 P (choose other points on the architectural axis of Figure 1.) 54 141.33 T 1 F (Figur) 317.88 545.08 T (e 1: Speed and Density V) 341.58 545.08 T (ariation with Number of) 446.99 545.08 T (Distinct Chips Fabricated.) 317.88 535.08 T 0 F 0.37 (The best choice for the number of siblings in a family) 339.48 513.08 P 0.8 (must be determined experimentally; it depends on the area) 317.88 501.08 P 1.3 (and speed advantage each new sibling confers and on the) 317.88 489.08 P 0.71 (cost of developing each new sibling. Clearly it is desirable) 317.88 477.08 P 0.55 (to have the smallest number of siblings which provides the) 317.88 465.08 P -0.16 (necessary performance improvement, since smaller invento-) 317.88 453.08 P 0.72 (ries will then have to be maintained by the vendor or user) 317.88 441.08 P 0.72 (,) 555.5 441.08 P 0.52 (and the family development costs will be lower) 317.88 429.08 P 0.52 (. The archi-) 510.6 429.08 P -0.25 (tectural dif) 317.88 417.08 P -0.25 (ferences between siblings are also crucial. A poor) 361.03 417.08 P 1.36 (set of choices will result in little or no gain in speed and) 317.88 405.08 P 1.08 (density) 317.88 393.08 P 1.08 (, or will require a lar) 346.1 393.08 P 1.08 (ge number of siblings to meet) 433.49 393.08 P 0.96 (the performance goals. A good set of choices will provide) 317.88 381.08 P -0.06 (lar) 317.88 369.08 P -0.06 (ger speed and density gains with a smaller number of sib-) 328.24 369.08 P (lings.) 317.88 357.08 T 2.47 (Another way of viewing the siblings concept is to) 339.48 339.08 P 0.84 (observe that along any FPGA architectural axis, for exam-) 317.88 327.08 P 0.55 (ple the granularity of the logic block, dif) 317.88 315.08 P 0.55 (ferent circuits will) 483.63 315.08 P -0.14 (have dif) 317.88 303.08 P -0.14 (ferent speed and density) 350.04 303.08 P -0.14 (. While there may be a good) 445.85 303.08 P 1.12 (single choice based on the average behaviour over all cir-) 317.88 291.08 P 1.23 (cuits, previous experimental work has shown a signi\336cant) 317.88 279.08 P 1.43 (circuit-dependent \337uctuation in speed and density for any) 317.88 267.08 P 1.61 (particular choice. Providing more implementation choices) 317.88 255.08 P 0.56 (will reduce this variation and improve both speed and den-) 317.88 243.08 P (sity) 317.88 231.08 T (.) 331.67 231.08 T 1 12 Q (3 An FPGA Family Based on Hard-W) 317.88 187.75 T (ir) 512.23 187.75 T (ed) 520.68 187.75 T (Logic Block Ar) 317.88 173.75 T (chitectur) 395.62 173.75 T (es) 441.36 173.75 T (3.1 Hard-W) 317.88 149.75 T (ir) 381.96 149.75 T (ed Logic Blocks) 390.4 149.75 T 0 10 Q 0.67 (A hard-wired logic block \050HLB\051 is created by replac-) 339.48 131.08 P 3.1 (ing some programmable connections with simple metal) 317.88 119.08 P 0.84 (wires, or hard-wired connections, between logic blocks [2,) 317.88 107.08 P 2.11 (3]. Since a metal wire incurs a much smaller delay and) 317.88 95.08 P 0.44 (requires less area than a programmable connection, FPGAs) 317.88 83.08 P 317.88 72 558 738 C 317.88 559.75 558 728 C 325.3 685.14 355.86 700.53 R 6 X 0 K V 0.5 H 2 Z 0 X N 355.86 685.14 386.42 700.53 R 5 X V 0 X N 386.42 685.14 416.98 700.53 R 4 X V 0 X N 416.98 685.14 447.54 700.53 R 3 X V 0 X N 447.54 685.14 478.11 700.53 R 2 X V 0 X N 478.11 685.14 508.67 700.53 R 1 X V 0 X N 508.67 685.14 539.23 700.53 R V N 527.12 650.09 538.66 646.78 527.12 643.48 527.12 646.78 4 Y V 527.12 646.78 333.37 646.78 2 L 1 H N 527.12 625.79 538.66 622.48 527.12 619.18 527.12 622.48 4 Y V 527.12 622.48 333.37 622.48 2 L N 527.87 594.74 539.41 591.43 527.87 588.13 527.87 591.43 4 Y V 527.87 591.43 334.12 591.43 2 L N 527.87 568.94 539.41 565.64 527.87 562.33 527.87 565.64 4 Y V 527.87 565.64 334.12 565.64 2 L N 375 710.33 492.5 722.83 R 7 X V 0 10 Q 0 X (For a Fixed Logic Capacity) 375 716.17 T 321.67 703.94 356.67 712.83 R 7 X V 0 X (FPGA) 321.67 706.17 T 513 702.89 548 712.33 R 7 X V 0 X (MPGA) 513 705.67 T 386.67 659.5 466.67 669.5 R 7 X V 0 X (# of Separate) 386.67 662.83 T (Chip Fabrications) 379.17 651.17 T 321.67 646.17 333.33 657 R 7 X V 0 X (1) 321.67 650.33 T (Many) 511.39 664.5 T (\0501 per Circuit\051) 494.45 651.72 T (Lar) 320.28 627.55 T (ge) 333.97 627.55 T (Area) 414.11 625.39 T (Small) 519.06 627.11 T (High) 322.78 595.89 T (Low) 523 596.78 T (High) 524.34 571.83 T (Low) 321.56 569.33 T (Speed) 412.34 568.28 T (Unit Chip Cost for) 385.89 606.67 T (High V) 378.34 594.78 T (olume Production) 406.75 594.78 T 317.88 72 558 738 C 0 0 612 792 C FMENDPAGE %%EndPage: "2" 3 %%Page: "3" 3 612 792 0 FMBEGINPAGE 279 38.14 315 54 R 7 X 0 K V 0 10 Q 0 X (3) 300.6 47.33 T 0.64 (built using HLBs have the potential to be both smaller and) 54 731.33 P -0.03 (faster than FPGAs in which all connections are programma-) 54 719.33 P 1.06 (ble. In this work, as in [2,3], we will consider only HLBs) 54 707.33 P 2.52 (composed of look-up tables \050LUT) 54 695.33 P 2.52 (s\051. Figure 2 illustrates) 199.39 695.33 P 0.91 (both an example HLB composed of three four) 54 683.33 P 0.91 (-input LUT) 244.21 683.33 P 0.91 (s) 290.23 683.33 P 1.03 (\0504-LUT) 54 671.33 P 1.03 (s\051 hard-wired in a chain and a circuit implemented) 84.38 671.33 P (with this HLB.) 54 659.33 T 1 F (Figur) 54 344.17 T (e 2: An Example HLB and Cir) 77.7 344.17 T (cuit) 207.46 344.17 T (Implementation.) 54 334.17 T 0 F 1.31 (In the HLBs we study) 75.6 312.17 P 1.31 (, the inputs of some LUT) 167.9 312.17 P 1.31 (s are) 274.22 312.17 P 0.07 (permanently hard-wired to the outputs of others. The output) 54 300.17 P -0.16 (of each LUT in an HLB can also be directed to the program-) 54 288.17 P 3.76 (mable interconnect via the output and tapping buf) 54 276.17 P 3.76 (fers) 279.14 276.17 P 1.76 (shown in the \336gure. Figure 2b shows an example circuit) 54 264.17 P 2.13 (implemented with a \050nonhard-wired\051 4-LUT logic block,) 54 252.17 P (while Figure 2c shows the same circuit implemented via the) 54 240.17 T 0.09 (HLB of Figure 2a. The circuit implemented with HLBs will) 54 228.17 P 0.93 (be faster) 54 216.17 P 0.93 (, since it has replaced many of the slow program-) 88.66 216.17 P 0.59 (mable connections on the critical path with fast hard-wired) 54 204.17 P -0.17 (ones. The ef) 54 192.17 P -0.17 (fect of HLBs on area is more dif) 102.61 192.17 P -0.17 (\336cult to predict.) 230.88 192.17 P 1.81 (Since many programmable connections are replaced with) 54 180.17 P 2.02 (simple metal wires, HLB circuit implementations can be) 54 168.17 P 0.59 (smaller than standard LUT realizations. On the other hand,) 54 156.17 P 0.79 (since HLBs are more coarse-grained, it is more dif) 54 144.17 P 0.79 (\336cult to) 262.5 144.17 P 0.12 (utilize them fully) 54 132.17 P 0.12 (, so the area required by many circuits will) 122.44 132.17 P 0.16 (increase. In practice, one \336nds that HLBs with a lar) 54 120.17 P 0.16 (ge num-) 260.93 120.17 P -0.24 (ber of hard-wired connections generally cause an increase in) 54 108.17 P 1.14 (circuit area, while HLBs with only a few hard-wired con-) 54 96.17 P 54 72 294.12 738 C 54.5 358.84 293.62 656 C 116.19 594.1 138.06 608.68 R 7 X 0 K V 0.5 H 2 Z 0 X N 124.36 609.09 124.36 617.39 2 L N 129.09 609.09 129.09 617.39 2 L N 133.81 609.09 133.81 617.39 2 L N 72.14 579.93 123.02 585.6 R 7 X V 0 8 Q 0 X (T) 72.14 580.26 T (apping Buf) 76.46 580.26 T (fer) 112.08 580.26 T 102.02 627.51 123.89 642.09 R 7 X V 0 X N 105.46 642.5 105.46 650.8 2 L N 110.19 642.5 110.19 650.8 2 L N 114.91 642.5 114.91 650.8 2 L N 119.64 642.5 119.64 650.8 2 L N (T) 61.07 613.16 T (apping Buf) 65.4 613.16 T (fer) 101.01 613.16 T 130.77 560.69 152.64 575.27 R 7 X V 0 X N 138.94 575.68 138.94 583.98 2 L N 143.66 575.68 143.66 583.98 2 L N 148.39 575.68 148.39 583.98 2 L N 141.51 560.69 141.51 554.01 2 L N 135.84 554.01 146.57 554.01 141.3 548.74 3 Y N 141.3 548.74 141.3 544.29 2 L N (Output Buf) 92.1 546.14 T (fer) 128.16 546.14 T 100.91 602.61 100.91 610.71 109 602.61 3 Y N 100.7 602.61 98.07 599.97 2 L N 112.25 613.74 104.96 606.66 2 L N 112.45 627.51 112.45 613.95 119.33 613.95 119.33 608.88 4 L 1 H 0 Z N 115.28 569.2 115.28 577.3 123.38 569.2 3 Y 0.5 H 2 Z N 115.08 569.2 112.45 566.56 2 L N 126.62 580.33 119.33 573.25 2 L N 126.82 594.1 126.82 580.54 133.71 580.54 133.71 575.47 4 L 1 H 0 Z N 82.62 532.23 153.32 539.52 R 7 X V 1 9 Q 0 X (\050a\051) 82.62 533.52 T 0 F ( Example HLB) 93.1 533.52 T 63.22 474.29 151.24 480.36 R 7 X V 0 8 Q 0 X (Programmable Connection) 63.22 475.03 T 63.45 466.19 150.94 472.26 R 7 X V 0 X (Hard-wired Connection) 63.45 466.93 T 152.62 477.66 161.4 477.66 2 L 0.5 H 2 Z N 152.59 470.09 162.49 470.09 2 L 1 H N 230.57 558.74 245.15 570.28 R 0.5 H N 232.4 570.28 232.4 576.76 2 L N 235.84 570.28 235.84 576.76 2 L N 239.28 570.28 239.28 576.76 2 L N 188.25 584.66 202.83 596.2 R N 190.07 596.2 190.07 602.68 2 L N 193.52 596.2 193.52 602.68 2 L N 196.96 596.2 196.96 602.68 2 L N 200.4 596.2 200.4 602.68 2 L N 221.87 606.33 236.45 617.87 R N 223.69 617.87 223.69 624.35 2 L N 227.13 617.87 227.13 624.35 2 L N 230.57 617.87 230.57 624.35 2 L N 195.34 558.94 209.92 570.49 R N 200.6 570.49 200.6 576.96 2 L N 204.05 570.49 204.05 576.96 2 L N 230.57 628.6 245.15 640.14 R N 232.4 640.14 232.4 646.62 2 L 4 X N 235.84 640.14 235.84 646.62 2 L N 239.28 640.14 239.28 646.62 2 L N 242.72 640.14 242.72 646.62 2 L N 214.98 534.44 229.56 545.98 R 0 X N 220.25 545.98 220.25 552.46 2 L N 214.58 583.04 229.16 594.58 R N 216.4 594.58 216.4 601.06 2 L N 219.84 594.58 219.84 601.06 2 L N 223.28 594.58 223.28 601.06 2 L N 252.85 558.74 267.43 570.28 R N 254.67 570.28 254.67 576.76 2 L N 258.11 570.28 258.11 576.76 2 L N 261.55 570.28 261.55 576.76 2 L N 262.16 582.64 276.74 594.18 R N 263.98 594.18 263.98 600.66 2 L N 267.43 594.18 267.43 600.66 2 L N 270.87 594.18 270.87 600.66 2 L N 274.31 594.18 274.31 600.66 2 L N 203.03 558.74 203.03 548.82 216.6 548.82 216.6 546.39 4 L 4 X N 194.93 584.46 194.93 574.54 196.76 574.54 196.76 570.89 4 L 0 X N 221.66 583.04 221.66 573.93 207.69 573.93 207.69 570.69 4 L 4 X N 237.46 628.4 237.46 621.51 233.61 621.51 233.61 618.07 4 L N 228.95 606.12 228.95 598.23 226.52 598.23 226.52 594.79 4 L N 222.07 534.24 222.07 529.79 2 L N 237.86 558.54 237.86 551.86 223.28 551.86 223.28 546.19 4 L 0 X N 259.73 558.54 259.73 548.01 227.13 548.01 227.13 545.98 4 L N 269.25 582.23 269.25 575.14 265 575.14 265 570.28 4 L N 245.96 610.98 285.78 616.65 R 7 X V 2 F 0 X -0.75 (critical path) 245.96 611.32 P 275.53 609.77 283.43 609.77 2 L 4 X N 182.58 520.47 282.21 528.37 R 7 X V 0 9 Q 0 X (\050b\051 Circuit mapped to basic) 182.58 522.37 T 202.22 511.96 251.02 518.65 R 7 X V 0 X (logic blocks) 202.22 512.65 T 0 8 Q (A) 110.73 633.03 T (B) 125.31 598.81 T (C) 139.68 566.01 T 218.93 411.31 233.51 422.85 R N 220.75 422.85 220.75 429.33 2 L N 224.2 422.85 224.2 429.33 2 L N 227.64 422.85 227.64 429.33 2 L N 176.61 437.23 191.19 448.77 R N 178.43 448.77 178.43 455.25 2 L N 181.87 448.77 181.87 455.25 2 L N 185.32 448.77 185.32 455.25 2 L N 188.76 448.77 188.76 455.25 2 L N 210.22 458.89 224.8 470.44 R N 212.04 470.44 212.04 476.92 2 L N 215.49 470.44 215.49 476.92 2 L N 218.93 470.44 218.93 476.92 2 L N 183.7 411.51 198.28 423.05 R N 188.96 423.05 188.96 429.53 2 L N 192.4 423.05 192.4 429.53 2 L N 218.93 481.17 233.51 492.71 R N 220.75 492.71 220.75 499.19 2 L N 224.2 492.71 224.2 499.19 2 L N 227.64 492.71 227.64 499.19 2 L N 231.08 492.71 231.08 499.19 2 L N 203.34 387.01 217.92 398.55 R N 208.6 398.55 208.6 405.03 2 L N 202.93 435.61 217.51 447.15 R N 204.76 447.15 204.76 453.63 2 L N 208.2 447.15 208.2 453.63 2 L N 211.64 447.15 211.64 453.63 2 L N 241.2 411.31 255.78 422.85 R N 243.03 422.85 243.03 429.33 2 L N 246.47 422.85 246.47 429.33 2 L N 249.91 422.85 249.91 429.33 2 L N 250.52 435.2 265.1 446.74 R N 252.34 446.74 252.34 453.22 2 L N 255.78 446.74 255.78 453.22 2 L N 259.23 446.74 259.23 453.22 2 L N 262.67 446.74 262.67 453.22 2 L N 191.39 411.31 191.39 401.39 204.96 401.39 204.96 398.96 4 L 1 H N 183.29 437.02 183.29 427.1 185.11 427.1 185.11 423.46 4 L N 210.02 435.61 210.02 426.49 196.05 426.49 196.05 423.26 4 L 0.5 H N 225.82 480.97 225.82 474.08 221.97 474.08 221.97 470.64 4 L 1 H N 217.31 458.69 217.31 450.8 214.88 450.8 214.88 447.35 4 L N 210.43 386.81 210.43 382.35 2 L 0.5 H N 226.22 411.11 226.22 404.42 211.64 404.42 211.64 398.75 4 L N 248.09 411.11 248.09 400.58 215.49 400.58 215.49 398.55 4 L N 257.61 434.8 257.61 427.71 253.35 427.71 253.35 422.85 4 L 1 H N (A) 181.87 440.72 T (B) 189.37 415.01 T (C) 208.6 391.11 T (A) 224.6 483.85 T (B) 215.89 462.79 T (C) 208.6 439.1 T (A) 224.8 415.41 T (A) 255.58 438.9 T (B) 246.47 415.41 T 226.62 502.23 M 201.52 495.55 205.97 462.54 199.69 445.73 D 194.8 432.72 209.12 424.17 215.49 432.17 D 228.45 448.57 249.1 495.14 226.22 502.63 D 0.5 H 4 X N 176.2 459.5 M 160.9 441.45 182.74 414.87 189.65 395.11 D 193.6 383.82 213.04 375.82 217.88 387.01 D 225.86 405.47 203.77 415.8 198 432.77 D 194.41 443.33 192.63 462.6 176.61 459.3 D N 253.35 456.26 M 240.95 445.47 228.74 407.61 248.09 406.45 D 263.41 405.52 263.35 428.71 267.53 440.27 D 270.58 448.72 262.23 456.17 253.76 456.26 D N 90 450 12.35 12.35 225.41 419.61 A 231.08 423.05 231.08 431.96 257.2 431.96 3 L 0 X N 242.93 570.49 242.93 578.79 269.05 578.79 3 L N 176.2 372.83 278.26 379.11 R 7 X V 1 9 Q 0 X (\050c\051) 176.2 373.11 T 0 F ( Circuit mapped to HLBs) 186.18 373.11 T 199.09 363.45 246.99 370 R 7 X V 0 X (shown in \050a\051) 199.09 364 T 54 72 294.12 738 C 0 0 612 792 C 0 10 Q 0 X 0 K 1.84 (nections can reduce the circuit area slightly compared to) 317.88 731.33 P (nonhard-wired implementations [2,3].) 317.88 719.33 T 1.74 (W) 339.48 701.33 P 1.74 (e create families of FPGAs by simply choosing a) 348.11 701.33 P -0.18 (dif) 317.88 689.33 P -0.18 (ferent HLB architecture for each sibling. Figure 3a shows) 328.8 689.33 P 1.2 (an example family with two siblings, and Figure 3b illus-) 317.88 677.33 P 1.54 (trates the fact that an application circuit is always imple-) 317.88 665.33 P (mented in the most suitable sibling.) 317.88 653.33 T 1 F (Figur) 317.88 421.14 T (e 3: An Example Family and Cir) 341.58 421.14 T (cuit) 480.21 421.14 T (Implementations.) 317.88 411.14 T 1 12 Q (3.2 Experimental Methodology) 317.88 387.8 T 0 10 Q 0.73 (W) 339.48 369.14 P 0.73 (e use the results of a previous study [3] to evaluate) 348.11 369.14 P 0.48 (the density and speed improvements attainable by applying) 317.88 357.14 P 2.15 (the siblings concept to HLBs. The results of technology) 317.88 345.14 P 0.8 (mapping a set of \336fteen mcnc benchmark circuits into 209) 317.88 333.14 P 0.27 (dif) 317.88 321.14 P 0.27 (ferent HLB architectures are used to compare the \322good-) 328.8 321.14 P -0.21 (ness\323 of each family) 317.88 309.14 P -0.21 (. Each architecture is de\336ned by the size) 398.48 309.14 P 0.48 (of its LUT) 317.88 297.14 P 0.48 (s \050from 2 to 7 inputs\051 and by the topology of the) 360.34 297.14 P 3.73 (hard-wired connections between these LUT) 317.88 285.14 P 3.73 (s. For each) 506.96 285.14 P 0.88 (architecture we compute area and delay estimates for each) 317.88 273.14 P 2.47 (circuit and normalize them to those of the same circuit) 317.88 261.14 P -0.1 (implemented in a 4-LUT FPGA with no hard-wired connec-) 317.88 249.14 P 0.78 (tions. The 4-LUT has previously been shown to be a good) 317.88 237.14 P -0.22 (choice for an FPGA logic block architecture [4], and by nor-) 317.88 225.14 P 1.81 (malizing our area and delay results to it we can average) 317.88 213.14 P 0.25 (results from circuits with a wide variance of sizes and logic) 317.88 201.14 P -0.1 (depths in a meaningful way) 317.88 189.14 P -0.1 (. All averaging is done with geo-) 427.31 189.14 P 0.35 (metric averages, since taking the arithmetic average of nor-) 317.88 177.14 P (malized numbers can lead to misleading results [5].) 317.88 165.14 T 0.92 (The delay and area of a family with only one sibling) 339.48 147.14 P 1.42 (are taken to the geometric averages of that FPGA) 317.88 135.14 P 1.42 (\325) 525.77 135.14 P 1.42 (s delay) 528.54 135.14 P 4.17 (and area metrics over our \336fteen benchmark circuits,) 317.88 123.14 P -0.02 (respectively) 317.88 111.14 P -0.02 (. The speed of an FPGA is simply the reciprocal) 365.52 111.14 P 0.56 (of delay) 317.88 99.14 P 0.56 (. In a family with more than one sibling, we de\336ne) 350.27 99.14 P 0.36 (the \322family score\323 on a circuit as the best area and/or delay) 317.88 87.14 P 317.88 72 558 738 C 317.88 435.8 558 650 C 432.69 606.83 447.27 618.37 R 0.5 H 2 Z 0 X 0 K N 434.51 618.37 434.51 624.85 2 L N 437.95 618.37 437.95 624.85 2 L N 441.4 618.37 441.4 624.85 2 L N 441.4 629.1 455.98 640.64 R N 443.22 640.64 443.22 647.12 2 L N 446.66 640.64 446.66 647.12 2 L N 450.1 640.64 450.1 647.12 2 L N 453.55 640.64 453.55 647.12 2 L N 425.4 583.54 439.98 595.08 R N 427.22 595.08 427.22 601.56 2 L N 430.66 595.08 430.66 601.56 2 L N 434.11 595.08 434.11 601.56 2 L N 448.28 628.9 448.28 622.01 444.43 622.01 444.43 618.57 4 L 1 H N 439.78 606.62 439.78 598.73 437.35 598.73 437.35 595.29 4 L N 320.51 630.99 409.7 637.45 R 7 X V 0 8 Q 0 X (Programmable Connection) 320.51 632.12 T 321.21 621.2 399.04 626.66 R 7 X V 0 X (Hard-wired Connection) 321.21 621.33 T 414.74 633.52 422.64 633.52 2 L 0.5 H N 402.42 623.53 411.33 623.53 2 L 1 H N 432.35 583.47 432.35 577.6 2 L 0.5 H N 490.94 600.62 505.52 612.16 R N 496.2 612.16 496.2 618.64 2 L N 499.65 612.16 499.65 618.64 2 L N 501.67 622.89 516.25 634.43 R N 503.49 634.43 503.49 640.91 2 L N 506.94 634.43 506.94 640.91 2 L N 510.38 634.43 510.38 640.91 2 L N 513.82 634.43 513.82 640.91 2 L N 508.76 622.69 508.76 615.8 502.68 615.8 502.68 612.36 4 L 1 H N 497.89 600.55 497.89 594.68 2 L 0.5 H N 479.6 623.09 494.18 634.64 R N 492.36 634.64 492.36 641.11 2 L N 488.91 634.64 488.91 641.11 2 L N 485.47 634.64 485.47 641.11 2 L N 482.03 634.64 482.03 641.11 2 L N 487.09 622.89 487.09 616.01 493.17 616.01 493.17 612.56 4 L 1 H N 422.5 564.96 521.59 573.34 R 7 X V 1 9 Q 0 X (\050a\051) 422.5 567.34 T 0 F ( A T) 432.98 567.34 T (wo Sibling Family) 448.82 567.34 T 393.63 447.86 505.22 456.23 R 7 X V 1 F 0 X (\050b\051) 393.63 450.23 T 0 F ( Mapping of T) 404.61 450.23 T (wo Example) 456.15 450.23 T 398.45 438.18 504.54 446.55 R 7 X V 0 X (Circuits into This Family) 398.45 440.55 T 400.92 491.08 415.5 502.62 R 0.5 H N 402.74 502.62 402.74 509.1 2 L N 406.18 502.62 406.18 509.1 2 L N 409.63 502.62 409.63 509.1 2 L N 409.63 513.35 424.21 524.9 R N 411.45 524.9 411.45 531.38 2 L N 414.89 524.9 414.89 531.38 2 L N 418.33 524.9 418.33 531.38 2 L N 421.78 524.9 421.78 531.38 2 L N 393.63 467.79 408.21 479.34 R N 398.9 479.34 398.9 485.82 2 L N 402.34 479.34 402.34 485.82 2 L N 416.51 513.15 416.51 506.27 412.67 506.27 412.67 502.83 4 L 1 H N 408.01 490.88 408.01 482.98 405.58 482.98 405.58 479.54 4 L N 400.58 467.73 400.58 461.85 2 L 0.5 H N 371.9 514.84 386.48 526.38 R N 384.65 526.38 384.65 532.86 2 L N 381.21 526.38 381.21 532.86 2 L N 377.77 526.38 377.77 532.86 2 L N 363.19 537.11 377.77 548.66 R N 375.95 548.66 375.95 555.14 2 L N 372.5 548.66 372.5 555.14 2 L N 369.06 548.66 369.06 555.14 2 L N 365.62 548.66 365.62 555.14 2 L N 379.19 491.55 393.77 503.1 R N 391.94 503.1 391.94 509.58 2 L N 388.5 503.1 388.5 509.58 2 L N 385.06 503.1 385.06 509.58 2 L N 370.88 536.91 370.88 530.03 374.73 530.03 374.73 526.58 4 L 1 H N 379.39 514.64 379.39 506.74 381.82 506.74 381.82 503.3 4 L N 485.09 465.43 499.67 476.97 R 0.5 H N 490.35 476.97 490.35 483.45 2 L N 493.8 476.97 493.8 483.45 2 L N 495.82 487.71 510.4 499.25 R N 497.64 499.25 497.64 505.73 2 L N 501.09 499.25 501.09 505.73 2 L N 504.53 499.25 504.53 505.73 2 L N 507.97 499.25 507.97 505.73 2 L N 502.91 487.5 502.91 480.62 496.83 480.62 496.83 477.18 4 L 1 H N 492.04 465.16 492.04 459.29 2 L 0.5 H N 473.75 487.91 488.33 499.45 R N 486.51 499.45 486.51 505.93 2 L N 483.06 499.45 483.06 505.93 2 L N 479.62 499.45 479.62 505.93 2 L N 481.24 487.71 481.24 480.82 487.32 480.82 487.32 477.38 4 L 1 H N 457.95 509.91 472.53 521.45 R 0.5 H N 463.22 521.45 463.22 527.93 2 L N 466.66 521.45 466.66 527.93 2 L N 468.69 532.19 483.27 543.73 R N 470.51 543.73 470.51 550.21 2 L N 473.95 543.73 473.95 550.21 2 L N 477.39 543.73 477.39 550.21 2 L N 480.84 543.73 480.84 550.21 2 L N 475.77 531.98 475.77 525.1 469.7 525.1 469.7 521.66 4 L 1 H N 446.62 532.39 461.2 543.93 R 0.5 H N 459.37 543.93 459.37 550.41 2 L N 455.93 543.93 455.93 550.41 2 L N 452.49 543.93 452.49 550.41 2 L N 449.05 543.93 449.05 550.41 2 L N 454.11 532.19 454.11 525.3 460.18 525.3 460.18 521.86 4 L 1 H N 386.41 491.48 386.41 482.58 395.32 482.58 395.32 479.34 4 L 0.5 H N 365.96 557.29 M 349.49 550.87 360.86 527.38 367.11 515.99 D 372.81 505.58 374.81 481.75 390.86 488.98 D 404.57 495.16 391.95 517.4 387.55 530.97 D 384.39 540.72 379.34 561.43 364.34 556.69 D 4 X N 416.78 533.6 M 398.92 522.74 391.78 487.23 390.86 466.98 D 390.38 456.37 408.68 463.34 410.43 468.4 D 417.04 487.42 438.65 533.81 416.78 533.4 D N 465.38 509.64 465.38 503.36 475.3 503.36 475.3 499.72 4 L 0 X N 4 X 90 450 28.15 24.7 464.77 530.5 A 90 450 29.67 23.49 491.81 483.52 A 383.63 592.61 421.63 598.08 R 7 X V 0 8 Q 0 X (Sibling A) 383.63 592.74 T 512.31 607.32 546.34 612.79 R 7 X V 0 X (Sibling B) 512.31 607.46 T 319.87 479.99 373.14 485.93 R 7 X V 0 X (Circuit 1 is best) 319.87 480.6 T 320.38 467.3 382.36 473.84 R 7 X V 0 X (suited to Sibling A) 320.38 468.51 T 495.56 526.44 550.84 532.38 R 7 X V 0 X (Circuit 2 is best) 495.56 527.05 T 491.08 515.25 555.06 521.8 R 7 X V 0 X (suited to Sibling B) 491.08 516.46 T 317.88 72 558 738 C 0 0 612 792 C FMENDPAGE %%EndPage: "3" 4 %%Page: "4" 4 612 792 0 FMBEGINPAGE 279 38.14 315 54 R 7 X 0 K V 0 10 Q 0 X (4) 300.6 47.33 T 0.24 (metric achieved by) 54 731.33 P 2 F 0.24 (any) 133.27 731.33 P 0 F 0.24 ( of the siblings on that circuit. A) 147.71 731.33 P 0.24 (ver-) 278.03 731.33 P 1.7 (aging this \322family score\323 over all the benchmark circuits) 54 719.33 P (yields the performance of this family) 54 707.33 T (.) 201.3 707.33 T 1.87 (T) 75.6 689.33 P 1.87 (o assess the improvement in the performance of a) 81.01 689.33 P 0.5 (family as the number of siblings is increased, we must \336nd) 54 677.33 P -0.2 (the best family with the given number of siblings that can be) 54 665.33 P 2.5 (constructed from our pool of possible architectures. For) 54 653.33 P 0.31 (families with three or fewer siblings we exhaustively check) 54 641.33 P 0.06 (the performance of all the possible families, so we are guar-) 54 629.33 P 2.06 (anteed to \336nd the best family) 54 617.33 P 2.06 (. W) 179.97 617.33 P 2.06 (ith 209 architectures to) 196.06 617.33 P 1.84 (choose from the number of possible families grows very) 54 605.33 P 0.1 (rapidly as the family size increases. Hence for families with) 54 593.33 P 0.03 (four or more siblings we limit the search space by assuming) 54 581.33 P -0.06 (that a family of size n consists of the best family of size n-1,) 54 569.33 P 0.96 (plus one more sibling. Therefore for four or more siblings) 54 557.33 P 0.76 (we may not have the absolute best family that can be con-) 54 545.33 P 0.76 (structed, but our investigations have shown that the family) 54 533.33 P 0.65 (we obtain is either the best or one with only slightly lower) 54 521.33 P (performance.) 54 509.33 T 1 12 Q (3.3 Ar) 54 486 T (ea and Delay Models) 88.76 486 T 0 10 Q 0.81 (The area and delay models used are deliberately kept) 75.6 467.33 P 0.64 (simple in order to allow the evaluation of the FPGA archi-) 54 455.33 P 1.29 (tectures after technology mapping; i.e. no place and route) 54 443.33 P 0.47 (step was undertaken. Note that only relative delay and area) 54 431.33 P 2.2 (metrics are necessary in this study) 54 419.33 P 2.2 (, since we are simply) 201.21 419.33 P 0.6 (comparing architectures. The critical path delay consists of) 54 407.33 P -0.18 (the logic block delay plus the delay incurred by programma-) 54 395.33 P 0.14 (ble interconnect, since the delay of a hard-wired connection) 54 383.33 P (is essentially zero [3].) 54 371.33 T -0.24 (D) 75.6 328.33 P 0 8 Q -0.19 (T) 82.82 325.83 P -0.19 (ot) 87.14 325.83 P 0 10 Q -0.24 ( is the total delay) 93.36 328.33 P -0.24 (, while N) 160.04 328.33 P 0 8 Q -0.19 (R) 196.47 325.83 P 0 10 Q -0.24 (and N) 203.61 328.33 P 0 8 Q -0.19 (L) 227.51 325.83 P 0 10 Q -0.24 ( are the number) 232.4 328.33 P 3.25 (of programmable connections and the number of logic) 54 316.33 P 0.09 (blocks on the critical path, respectively) 54 304.33 P 0.09 (. D) 210.36 304.33 P 0 8 Q 0.07 (LB) 222.66 301.83 P 0 10 Q 0.09 (and D) 234.95 304.33 P 0 8 Q 0.07 (R) 259.19 301.83 P 0 10 Q 0.09 ( are the) 264.52 304.33 P 0.59 (delays of a logic block and of a programmable connection,) 54 292.33 P 2.12 (respectively) 54 280.33 P 2.12 (. The architectures studied were all based on) 101.64 280.33 P -0.21 (LUT) 54 268.33 P -0.21 (s with between 2 and 7 inputs. The delays of these logic) 72.73 268.33 P 0.38 (blocks have been found from SPICE simulations of 1.2) 54 256.33 P 3 F 0.38 (m) 280.59 256.33 P 0 F 0.38 (m) 286.34 256.33 P (CMOS implementations [6], and are listed in T) 54 244.33 T (able 1.) 242.08 244.33 T 1 F (T) 102.06 222.33 T (ABLE 1. Lookup T) 107.99 222.33 T (able Delays in a 1.2) 189.27 222.33 T 3 F (m) 273.68 222.33 T 1 F (m) 279.43 222.33 T (CMOS pr) 102.06 210.33 T (ocess) 144.36 210.33 T 0 F (.) 166.01 210.33 T 1 9 Q (# Inputs to) 117.33 190 T (LUT) 128.82 179 T (D) 194.04 179 T 1 7 Q (LB) 200.53 176.75 T 1 9 Q (\050ns\051) 211.6 179 T 0 10 Q (2) 135.56 163.33 T (1.39) 201.32 163.33 T (3) 135.56 147.33 T (1.44) 201.32 147.33 T (4) 135.56 131.33 T (1.71) 201.32 131.33 T (5) 135.56 115.33 T (2.03) 201.32 115.33 T (6) 135.56 99.33 T (2.38) 201.32 99.33 T (7) 135.56 83.33 T (2.85) 201.32 83.33 T 102.06 203.75 102.06 78.25 2 L V 0.5 H 0 Z N 174.06 204.25 174.06 77.75 2 L V N 246.06 203.75 246.06 78.25 2 L V N 101.81 204 246.31 204 2 L V N 102.31 175.25 245.81 175.25 2 L V N 102.31 172.75 245.81 172.75 2 L V N 101.81 158 246.31 158 2 L V N 101.81 142 246.31 142 2 L V N 101.81 126 246.31 126 2 L V N 101.81 110 246.31 110 2 L V N 101.81 94 246.31 94 2 L V N 101.81 78 246.31 78 2 L V N 54 72 294.12 738 C 59.81 343 288.31 368 C 2 9 Q 0 X 0 K (D) 117.84 350.5 T 2 7 Q (T) 124.67 347.37 T (o) 129.1 347.37 T (t) 133.13 347.37 T 2 9 Q (N) 149.01 350.5 T 2 7 Q (L) 155.35 347.37 T 2 9 Q (D) 168.67 350.5 T 2 7 Q (L) 175.5 347.37 T (B) 179.93 347.37 T 3 9 Q (\264) 161.48 350.5 T 2 F (N) 193.63 350.5 T 2 7 Q (R) 199.97 347.37 T 2 9 Q (D) 213.68 350.5 T 2 7 Q (R) 220.51 347.37 T 3 9 Q (\264) 206.49 350.5 T (+) 186.45 350.5 T (=) 139.57 350.5 T 54 72 294.12 738 C 0 0 612 792 C 0 10 Q 0 X 0 K 1.49 (Choosing a value for D) 339.48 731.33 P 0 8 Q 1.19 (R) 438.72 728.83 P 0 10 Q 1.49 ( is more problematic, since) 444.05 731.33 P 3.26 (the delay of a programmable connection varies widely) 317.88 719.33 P 0.25 (depending on its fanout and the number of routing switches) 317.88 707.33 P 1.54 (through which it passes. W) 317.88 695.33 P 1.54 (e set D) 431.79 695.33 P 0 8 Q 1.23 (R) 462.63 692.83 P 0 10 Q 1.54 ( to 4 ns, since in our) 467.96 695.33 P 0.7 (experience this is a reasonable value for the type of FPGA) 317.88 683.33 P 3.9 (architectures we are studying implemented in 1.2) 317.88 671.33 P 3 F 3.9 (m) 544.47 671.33 P 0 F 3.9 (m) 550.22 671.33 P 1.59 (CMOS. T) 317.88 659.33 P 1.59 (o ensure that the value chosen for D) 358.2 659.33 P 0 8 Q 1.27 (R) 513.39 656.83 P 0 10 Q 1.59 ( does not) 518.73 659.33 P 1.58 (af) 317.88 647.33 P 1.58 (fect our conclusions, we also conduct experiments with) 325.47 647.33 P (D) 317.88 635.33 T 0 8 Q (R) 325.1 632.83 T 0 10 Q (as low as 1 ns and as high as 10 ns.) 332.43 635.33 T 2.1 (Instead of referring to delay directly) 339.48 617.33 P 2.1 (, we will often) 493.95 617.33 P 0.95 (refer to the speedup of one FPGA with respect to another) 317.88 605.33 P 0.95 (.) 555.5 605.33 P -0.19 (The speedup of FPGA) 317.88 593.33 P 0 8 Q -0.16 (A) 406.96 590.83 P 0 10 Q -0.19 ( with respect to FPGA) 412.73 593.33 P 0 8 Q -0.16 (B) 501.34 590.83 P 0 10 Q -0.19 ( is de\336ned as) 506.67 593.33 P 0.57 (The area of the logic blocks in a LUT) 339.48 539.33 P 0.57 (-based FPGA is) 493.56 539.33 P 1.46 (mostly SRAM bits, while the routing area correlates well) 317.88 527.33 P 0.2 (with the total number of pins on the logic blocks. W) 317.88 515.33 P 0.2 (e there-) 527.56 515.33 P (fore take the area of a circuit to be proportional to [7, 8]) 317.88 503.33 T 0 11 Q 0.38 (where N) 317.88 464.45 P 0 9 Q 0.31 (HLB) 355.78 461.7 P 0 11 Q 0.38 ( is the number of hard-wired logic blocks) 373.76 464.45 P 0.94 (required to implement the circuit and HLB) 317.88 451.45 P 0 9 Q 0.76 (Bits) 511.45 448.7 P 0 11 Q 0.94 (, HLB-) 525.94 451.45 P 0 9 Q 1.59 (Pins) 317.88 435.7 P 0 11 Q 1.94 (, and HLB) 333.36 438.45 P 0 9 Q 1.59 (LUT) 383.33 435.7 P 1.59 (s) 400.17 435.7 P 0 11 Q 1.94 (are the number of bits, pins and) 407.5 438.45 P 0.99 (LUT) 317.88 425.45 P 0.99 (s per HLB, respectively) 338.47 425.45 P 0.99 (. Pinfac is the number of) 445.06 425.45 P 0.84 (logic bit equivalent area units consumed by each pin,) 317.88 412.45 P 1.85 (while F) 317.88 399.45 P 1.85 (A is the number of logic bit equivalent area) 352.18 399.45 P 0.27 (units required by the \336xed resources \050a D \337ip \337op and) 317.88 386.45 P 0.7 (output buf) 317.88 373.45 P 0.7 (fer\051 associated with each LUT) 363.85 373.45 P 0.7 (. In a 1.2) 498.84 373.45 P 3 F 0.7 (m) 543.12 373.45 P 0 F 0.7 (m) 549.45 373.45 P 0.49 (CMOS process F) 317.88 360.45 P 0.49 (A is 3.4 [3], while Pinfac is approxi-) 393.74 360.45 P 1.09 (mately 14 for the type of FPGA architectures we are) 317.88 347.45 P 0.2 (studying. As with the D) 317.88 334.45 P 0 9 Q 0.16 (R) 423.35 331.7 P 0 11 Q 0.2 ( parameter) 429.35 334.45 P 0.2 (, however) 475.78 334.45 P 0.2 (, we also) 518.85 334.45 P -0.09 (conduct experiments with Pinfac set as low as 4 and as) 317.88 321.45 P 1.25 (high as 30, in order to ensure that its value does not) 317.88 308.45 P (greatly in\337uence our results.) 317.88 295.45 T 1 12 Q (3.4 Experimental Results) 317.88 271.78 T 0 10 Q 2.23 (The technology mapping procedure could be set to) 339.48 253.11 P 2.82 (produce either area or delay-optimized circuits, and we) 317.88 241.11 P 0.34 (tested the performance of siblings on both types of circuits.) 317.88 229.11 P 1.74 (For the area-mapped case, we chose the sibling architec-) 317.88 217.11 P 0.39 (tures to minimize the area of the benchmark circuits. In the) 317.88 205.11 P 1.25 (case of delay-mapped circuits, however) 317.88 193.11 P 1.25 (, choosing the sib-) 480.96 193.11 P -0.24 (ling architectures to minimize delay alone produces a family) 317.88 181.11 P 0.89 (with unacceptably lar) 317.88 169.11 P 0.89 (ge areas -- typically about four times) 405.53 169.11 P 0.21 (the area of a nonhard-wired 4 LUT implementation. Conse-) 317.88 157.11 P 0.81 (quently we chose siblings to minimize the sum of the area) 317.88 145.11 P 1.11 (and delay for the delay-mapped circuits. This slows down) 317.88 133.11 P 0.18 (the circuits only slightly) 317.88 121.11 P 0.18 (, while reducing their area by a fac-) 414.66 121.11 P 0.83 (tor of approximately 4. Figure 4 shows the speed and area) 317.88 109.11 P 1.07 (improvements possible with siblings for both types of cir-) 317.88 97.11 P (cuit mappings.) 317.88 85.11 T 317.88 72 558 738 C 325.77 554 550.11 590 C 2 9 Q 0 X 0 K (S) 388.77 568 T (p) 393.79 568 T (e) 398.81 568 T (e) 403.33 568 T (d) 407.85 568 T (u) 412.88 568 T (p) 417.9 568 T 2 7 Q (A) 422.74 564.87 T (B) 427.55 564.87 T 2 9 Q (D) 446.5 576.51 T (e) 453.52 576.51 T (l) 458.04 576.51 T (a) 461.07 576.51 T (y) 466.09 576.51 T 2 7 Q (B) 470.43 573.38 T 2 9 Q (D) 446.5 561.79 T (e) 453.52 561.79 T (l) 458.04 561.79 T (a) 461.07 561.79 T (y) 466.09 561.79 T 2 7 Q (A) 470.43 558.66 T 3 9 Q (=) 436.32 568 T 446.5 569.94 474.45 569.94 2 L 0.33 H 0 Z N 476.61 566.75 482.61 575.75 R 7 X V 0 10 Q 0 X (.) 477.61 569.08 T 317.88 72 558 738 C 0 0 612 792 C 317.88 72 558 738 C 322.21 479.78 553.67 500 C 2 9 Q 0 X 0 K (A) 321.82 487.02 T (r) 327.84 487.02 T (e) 331.86 487.02 T (a) 336.38 487.02 T (N) 351.79 487.02 T 2 7 Q (H) 358.13 483.89 T (L) 363.71 483.89 T (B) 368.14 483.89 T 2 9 Q (H) 378.32 487.02 T (L) 385.34 487.02 T (B) 390.86 487.02 T 2 7 Q (B) 396.7 483.89 T (i) 401.51 483.89 T (t) 403.99 483.89 T (s) 406.47 483.89 T 2 9 Q (P) 418.63 487.02 T (i) 424.65 487.02 T (n) 427.67 487.02 T (f) 432.7 487.02 T (a) 435.73 487.02 T (c) 440.75 487.02 T (H) 454.17 487.02 T (L) 461.19 487.02 T (B) 466.72 487.02 T 2 7 Q (P) 472.55 483.89 T (i) 477.36 483.89 T (n) 479.85 483.89 T (s) 483.88 483.89 T 2 9 Q (F) 496.03 487.02 T (A) 502.05 487.02 T (H) 516.98 487.02 T (L) 523.99 487.02 T (B) 529.52 487.02 T 2 7 Q (L) 535.36 483.89 T (U) 539.78 483.89 T (T) 545.37 483.89 T (s) 549.79 483.89 T 3 9 Q (\264) 509.79 487.02 T (+) 488.85 487.02 T (\264) 446.99 487.02 T (+) 411.44 487.02 T (\050) 374.43 487.02 T (\051) 552.9 487.02 T (\265) 343.13 487.02 T 317.88 72 558 738 C 0 0 612 792 C FMENDPAGE %%EndPage: "4" 5 %%Page: "5" 5 612 792 0 FMBEGINPAGE 279 38.14 315 54 R 7 X 0 K V 0 10 Q 0 X (5) 300.6 47.33 T 1 F (Figur) 54 254.84 T (e 4: Impr) 77.7 254.84 T (ovements in FPGA Performance and) 117.49 254.84 T (Density Measur) 54 244.84 T (es as a Function of Number of Siblings) 121.27 244.84 T (for \050a\051 Cir) 54 234.84 T (cuits T) 97.67 234.84 T (echnology Mapped to Minimize Ar) 125.9 234.84 T (ea,) 274.52 234.84 T (and \050b\051 Cir) 54 224.84 T (cuits T) 101.57 224.84 T (echnology Mapped to Minimize Delay) 129.81 224.84 T (.) 290.83 224.84 T 0 F 0.03 (In Figure 4 we have normalized all our results to those) 75.6 202.84 P -0.19 (obtained by the best single FPGA architecture \050i.e. the 1 sib-) 54 190.84 P 2.74 (ling case\051 so that the performance improvement due to) 54 178.84 P 1.39 (increasing the size of the family is immediately apparent.) 54 166.84 P 0.48 (From Figure 4, one sees that using a family with 8 siblings) 54 154.84 P 2.01 (would result in FPGAs that are 12.5% smaller and 20%) 54 142.84 P 0.53 (faster than any single FPGA for the area-mapped case, and) 54 130.84 P (1) 54 118.84 T (1.5% smaller and 19% faster for the delay-mapped case.) 58.63 118.84 T 2.75 ( Figures 5 and 6 show which FPGA architectures) 75.6 100.84 P 1.48 (formed the best families with between one and three sib-) 54 88.84 P 4.54 (lings for the area-mapped and delay-mapped circuits,) 54 76.84 P 54 72 294.12 738 C 64.69 497.8 283.43 728 C 0 126 275 410 606 206.28 224.59 69.14 500.9 FMBEGINEPSF %%BeginDocument: /jayar/d0/vaughn/fpga95/xgraph2/hardarea.eps %!PS-Adobe-2.0 EPSF-1.2 %%BoundingBox: 126 275 410 606 %!PS-Adobe-2.0 EPSF-1.2 %%DocumentFonts: Times-Roman Times-Bold %%Pages: 1 %%BoundingBox: 127 274 411 606 %%EndComments /IdrawDict 52 dict def IdrawDict begin /reencodeISO { dup dup findfont dup length dict begin { 1 index /FID ne { def }{ pop pop } ifelse } forall /Encoding ISOLatin1Encoding def currentdict end definefont } def /ISOLatin1Encoding [ /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /space/exclam/quotedbl/numbersign/dollar/percent/ampersand/quoteright /parenleft/parenright/asterisk/plus/comma/minus/period/slash /zero/one/two/three/four/five/six/seven/eight/nine/colon/semicolon /less/equal/greater/question/at/A/B/C/D/E/F/G/H/I/J/K/L/M/N /O/P/Q/R/S/T/U/V/W/X/Y/Z/bracketleft/backslash/bracketright /asciicircum/underscore/quoteleft/a/b/c/d/e/f/g/h/i/j/k/l/m /n/o/p/q/r/s/t/u/v/w/x/y/z/braceleft/bar/braceright/asciitilde /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/dotlessi/grave/acute/circumflex/tilde/macron/breve /dotaccent/dieresis/.notdef/ring/cedilla/.notdef/hungarumlaut /ogonek/caron/space/exclamdown/cent/sterling/currency/yen/brokenbar /section/dieresis/copyright/ordfeminine/guillemotleft/logicalnot /hyphen/registered/macron/degree/plusminus/twosuperior/threesuperior /acute/mu/paragraph/periodcentered/cedilla/onesuperior/ordmasculine /guillemotright/onequarter/onehalf/threequarters/questiondown /Agrave/Aacute/Acircumflex/Atilde/Adieresis/Aring/AE/Ccedilla /Egrave/Eacute/Ecircumflex/Edieresis/Igrave/Iacute/Icircumflex /Idieresis/Eth/Ntilde/Ograve/Oacute/Ocircumflex/Otilde/Odieresis /multiply/Oslash/Ugrave/Uacute/Ucircumflex/Udieresis/Yacute /Thorn/germandbls/agrave/aacute/acircumflex/atilde/adieresis /aring/ae/ccedilla/egrave/eacute/ecircumflex/edieresis/igrave /iacute/icircumflex/idieresis/eth/ntilde/ograve/oacute/ocircumflex /otilde/odieresis/divide/oslash/ugrave/uacute/ucircumflex/udieresis /yacute/thorn/ydieresis ] def /Times-Roman reencodeISO def /Times-Bold reencodeISO def /arrowHeight 8 def /arrowWidth 4 def /none null def /numGraphicParameters 17 def /stringLimit 65535 def /Begin { save numGraphicParameters dict begin } def /End { end restore } def /SetB { dup type /nulltype eq { pop false /brushRightArrow idef false /brushLeftArrow idef true /brushNone idef } { /brushDashOffset idef /brushDashArray idef 0 ne /brushRightArrow idef 0 ne /brushLeftArrow idef /brushWidth idef false /brushNone idef } ifelse } def /SetCFg { /fgblue idef /fggreen idef /fgred idef } def /SetCBg { /bgblue idef /bggreen idef /bgred idef } def /SetF { /printSize idef /printFont idef } def /SetP { dup type /nulltype eq { pop true /patternNone idef } { dup -1 eq { /patternGrayLevel idef /patternString idef } { /patternGrayLevel idef } ifelse false /patternNone idef } ifelse } def /BSpl { 0 begin storexyn newpath n 1 gt { 0 0 0 0 0 0 1 1 true subspline n 2 gt { 0 0 0 0 1 1 2 2 false subspline 1 1 n 3 sub { /i exch def i 1 sub dup i dup i 1 add dup i 2 add dup false subspline } for n 3 sub dup n 2 sub dup n 1 sub dup 2 copy false subspline } if n 2 sub dup n 1 sub dup 2 copy 2 copy false subspline patternNone not brushLeftArrow not brushRightArrow not and and { ifill } if brushNone not { istroke } if 0 0 1 1 leftarrow n 2 sub dup n 1 sub dup rightarrow } if end } dup 0 4 dict put def /Circ { newpath 0 360 arc patternNone not { ifill } if brushNone not { istroke } if } def /CBSpl { 0 begin dup 2 gt { storexyn newpath n 1 sub dup 0 0 1 1 2 2 true subspline 1 1 n 3 sub { /i exch def i 1 sub dup i dup i 1 add dup i 2 add dup false subspline } for n 3 sub dup n 2 sub dup n 1 sub dup 0 0 false subspline n 2 sub dup n 1 sub dup 0 0 1 1 false subspline patternNone not { ifill } if brushNone not { istroke } if } { Poly } ifelse end } dup 0 4 dict put def /Elli { 0 begin newpath 4 2 roll translate scale 0 0 1 0 360 arc patternNone not { ifill } if brushNone not { istroke } if end } dup 0 1 dict put def /Line { 0 begin 2 storexyn newpath x 0 get y 0 get moveto x 1 get y 1 get lineto brushNone not { istroke } if 0 0 1 1 leftarrow 0 0 1 1 rightarrow end } dup 0 4 dict put def /MLine { 0 begin storexyn newpath n 1 gt { x 0 get y 0 get moveto 1 1 n 1 sub { /i exch def x i get y i get lineto } for patternNone not brushLeftArrow not brushRightArrow not and and { ifill } if brushNone not { istroke } if 0 0 1 1 leftarrow n 2 sub dup n 1 sub dup rightarrow } if end } dup 0 4 dict put def /Poly { 3 1 roll newpath moveto -1 add { lineto } repeat closepath patternNone not { ifill } if brushNone not { istroke } if } def /Rect { 0 begin /t exch def /r exch def /b exch def /l exch def newpath l b moveto l t lineto r t lineto r b lineto closepath patternNone not { ifill } if brushNone not { istroke } if end } dup 0 4 dict put def /Text { ishow } def /idef { dup where { pop pop pop } { exch def } ifelse } def /ifill { 0 begin gsave patternGrayLevel -1 ne { fgred bgred fgred sub patternGrayLevel mul add fggreen bggreen fggreen sub patternGrayLevel mul add fgblue bgblue fgblue sub patternGrayLevel mul add setrgbcolor eofill } { eoclip originalCTM setmatrix pathbbox /t exch def /r exch def /b exch def /l exch def /w r l sub ceiling cvi def /h t b sub ceiling cvi def /imageByteWidth w 8 div ceiling cvi def /imageHeight h def bgred bggreen bgblue setrgbcolor eofill fgred fggreen fgblue setrgbcolor w 0 gt h 0 gt and { l b translate w h scale w h true [w 0 0 h neg 0 h] { patternproc } imagemask } if } ifelse grestore end } dup 0 8 dict put def /istroke { gsave brushDashOffset -1 eq { [] 0 setdash 1 setgray } { brushDashArray brushDashOffset setdash fgred fggreen fgblue setrgbcolor } ifelse brushWidth setlinewidth originalCTM setmatrix stroke grestore } def /ishow { 0 begin gsave fgred fggreen fgblue setrgbcolor printFont printSize scalefont setfont /descender 0 printFont /FontBBox get 1 get printFont /FontMatrix get transform exch pop def /vertoffset 1 printSize sub descender sub def { 0 vertoffset moveto show /vertoffset vertoffset printSize sub def } forall grestore end } dup 0 2 dict put def /patternproc { 0 begin /patternByteLength patternString length def /patternHeight patternByteLength 8 mul sqrt cvi def /patternWidth patternHeight def /patternByteWidth patternWidth 8 idiv def /imageByteMaxLength imageByteWidth imageHeight mul stringLimit patternByteWidth sub min def /imageMaxHeight imageByteMaxLength imageByteWidth idiv patternHeight idiv patternHeight mul patternHeight max def /imageHeight imageHeight imageMaxHeight sub store /imageString imageByteWidth imageMaxHeight mul patternByteWidth add string def 0 1 imageMaxHeight 1 sub { /y exch def /patternRow y patternByteWidth mul patternByteLength mod def /patternRowString patternString patternRow patternByteWidth getinterval def /imageRow y imageByteWidth mul def 0 patternByteWidth imageByteWidth 1 sub { /x exch def imageString imageRow x add patternRowString putinterval } for } for imageString end } dup 0 12 dict put def /min { dup 3 2 roll dup 4 3 roll lt { exch } if pop } def /max { dup 3 2 roll dup 4 3 roll gt { exch } if pop } def /arrowhead { 0 begin transform originalCTM itransform /taily exch def /tailx exch def transform originalCTM itransform /tipy exch def /tipx exch def /dy tipy taily sub def /dx tipx tailx sub def /angle dx 0 ne dy 0 ne or { dy dx atan } { 90 } ifelse def gsave originalCTM setmatrix tipx tipy translate angle rotate newpath 0 0 moveto arrowHeight neg arrowWidth 2 div lineto arrowHeight neg arrowWidth 2 div neg lineto closepath patternNone not { originalCTM setmatrix /padtip arrowHeight 2 exp 0.25 arrowWidth 2 exp mul add sqrt brushWidth mul arrowWidth div def /padtail brushWidth 2 div def tipx tipy translate angle rotate padtip 0 translate arrowHeight padtip add padtail add arrowHeight div dup scale arrowheadpath ifill } if brushNone not { originalCTM setmatrix tipx tipy translate angle rotate arrowheadpath istroke } if grestore end } dup 0 9 dict put def /arrowheadpath { newpath 0 0 moveto arrowHeight neg arrowWidth 2 div lineto arrowHeight neg arrowWidth 2 div neg lineto closepath } def /leftarrow { 0 begin y exch get /taily exch def x exch get /tailx exch def y exch get /tipy exch def x exch get /tipx exch def brushLeftArrow { tipx tipy tailx taily arrowhead } if end } dup 0 4 dict put def /rightarrow { 0 begin y exch get /tipy exch def x exch get /tipx exch def y exch get /taily exch def x exch get /tailx exch def brushRightArrow { tipx tipy tailx taily arrowhead } if end } dup 0 4 dict put def /midpoint { 0 begin /y1 exch def /x1 exch def /y0 exch def /x0 exch def x0 x1 add 2 div y0 y1 add 2 div end } dup 0 4 dict put def /thirdpoint { 0 begin /y1 exch def /x1 exch def /y0 exch def /x0 exch def x0 2 mul x1 add 3 div y0 2 mul y1 add 3 div end } dup 0 4 dict put def /subspline { 0 begin /movetoNeeded exch def y exch get /y3 exch def x exch get /x3 exch def y exch get /y2 exch def x exch get /x2 exch def y exch get /y1 exch def x exch get /x1 exch def y exch get /y0 exch def x exch get /x0 exch def x1 y1 x2 y2 thirdpoint /p1y exch def /p1x exch def x2 y2 x1 y1 thirdpoint /p2y exch def /p2x exch def x1 y1 x0 y0 thirdpoint p1x p1y midpoint /p0y exch def /p0x exch def x2 y2 x3 y3 thirdpoint p2x p2y midpoint /p3y exch def /p3x exch def movetoNeeded { p0x p0y moveto } if p1x p1y p2x p2y p3x p3y curveto end } dup 0 17 dict put def /storexyn { /n exch def /y n array def /x n array def n 1 sub -1 0 { /i exch def y i 3 2 roll put x i 3 2 roll put } for } def %%EndProlog %I Idraw 9 Grid 4.80467 %%Page: 1 1 Begin %I b u %I cfg u %I cbg u %I f u %I p u %I t u /originalCTM matrix currentmatrix def Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 242.239 596.369 ] concat %I [ (Number of Bits) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 242.239 350.669 ] concat %I [ (Number of Pins) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 341.527 573.185 ] concat %I [ (Speedup) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 247.784 407.117 ] concat %I [ (Area) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 260.888 298.763 ] concat %I [ (Number of Siblings) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 336.557 ] concat %I [ (0.80) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 364.907 ] concat %I [ (0.85) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 393.257 ] concat %I [ (0.90) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 421.607 ] concat %I [ (0.95) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 449.957 ] concat %I [ (1.00) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 478.307 ] concat %I [ (1.05) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 506.657 ] concat %I [ (1.10) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 535.637 ] concat %I [ (1.15) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 563.987 ] concat %I [ (1.20) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 141.855 592.337 ] concat %I [ (1.25) ] Text End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 310 443 310 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 355 443 355 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 400 443 400 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 445 443 445 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 490 443 490 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 535 443 535 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 580 443 580 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 626 443 626 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 671 443 671 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 43 716 443 716 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 113 744 113 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 217 744 217 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 321 744 321 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 2 425 744 425 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 5 43 744 43 275 443 275 443 744 43 744 5 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 8 61 490 113 635 165 723 217 681 269 586 321 653 373 581 425 606 8 MLine End Begin %I MLine %I b -3856 0 0 0 [4 4 4 4] 17 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 8 61 490 113 363 165 330 217 321 269 320 321 296 373 314 425 303 8 MLine End Begin %I MLine %I b -13108 0 0 0 [2 2 2 2 2 2 2 2] 17 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 8 61 490 113 567 165 653 217 658 269 663 321 680 373 675 425 670 8 MLine End Begin %I MLine %I b -21846 0 0 0 [1] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 131.485 136.847 ] concat %I 8 61 490 113 446 165 423 217 409 269 395 321 388 373 382 425 378 8 MLine End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 200.705 307.57 ] concat %I [ (2) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 266.505 307.57 ] concat %I [ (4) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 331.745 307.57 ] concat %I [ (6) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 397.545 307.57 ] concat %I [ (8) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 168.785 307.57 ] concat %I [ (1) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 234.305 307.57 ] concat %I [ (3) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 299.825 307.57 ] concat %I [ (5) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 365.345 307.57 ] concat %I [ (7) ] Text End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 163.185 266.97 ] concat %I 263 138 262 139 Line End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 163.185 266.97 ] concat %I 24 155 24 172 Line End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 294.505 266.97 ] concat %I 24 155 24 172 Line End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 228.985 266.97 ] concat %I 24 155 24 172 Line End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 360.025 266.97 ] concat %I 24 155 24 172 Line End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-bold-r-*-140-75-75-* Times-Bold 14 SetF %I t [ 0.8 0 0 0.8 281.2 286 ] concat %I [ (\(a\)) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0 -0.72 0.72 0 137.68 571.32 ] concat %I [ (Normalized FPGA Performance and Density Measures) ] Text End End %I eop showpage %%Trailer end %%EndDocument FMENDEPSF 54 72 294.12 738 C 0 0 612 792 C 54 72 294.12 738 C 66.06 269.51 282.06 497.8 C 0 131 320 417 647 205.16 213.86 72.73 272.45 FMBEGINEPSF %%BeginDocument: /jayar/d0/vaughn/fpga95/xgraph2/harddel.eps %!PS-Adobe-2.0 EPSF-1.2 %%BoundingBox: 131 320 417 647 %!PS-Adobe-2.0 EPSF-1.2 %%DocumentFonts: Times-Roman Times-Bold %%Pages: 1 %%BoundingBox: 131 319 418 647 %%EndComments /IdrawDict 52 dict def IdrawDict begin /reencodeISO { dup dup findfont dup length dict begin { 1 index /FID ne { def }{ pop pop } ifelse } forall /Encoding ISOLatin1Encoding def currentdict end definefont } def /ISOLatin1Encoding [ /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /space/exclam/quotedbl/numbersign/dollar/percent/ampersand/quoteright /parenleft/parenright/asterisk/plus/comma/minus/period/slash /zero/one/two/three/four/five/six/seven/eight/nine/colon/semicolon /less/equal/greater/question/at/A/B/C/D/E/F/G/H/I/J/K/L/M/N /O/P/Q/R/S/T/U/V/W/X/Y/Z/bracketleft/backslash/bracketright /asciicircum/underscore/quoteleft/a/b/c/d/e/f/g/h/i/j/k/l/m /n/o/p/q/r/s/t/u/v/w/x/y/z/braceleft/bar/braceright/asciitilde /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef/.notdef /.notdef/dotlessi/grave/acute/circumflex/tilde/macron/breve /dotaccent/dieresis/.notdef/ring/cedilla/.notdef/hungarumlaut /ogonek/caron/space/exclamdown/cent/sterling/currency/yen/brokenbar /section/dieresis/copyright/ordfeminine/guillemotleft/logicalnot /hyphen/registered/macron/degree/plusminus/twosuperior/threesuperior /acute/mu/paragraph/periodcentered/cedilla/onesuperior/ordmasculine /guillemotright/onequarter/onehalf/threequarters/questiondown /Agrave/Aacute/Acircumflex/Atilde/Adieresis/Aring/AE/Ccedilla /Egrave/Eacute/Ecircumflex/Edieresis/Igrave/Iacute/Icircumflex /Idieresis/Eth/Ntilde/Ograve/Oacute/Ocircumflex/Otilde/Odieresis /multiply/Oslash/Ugrave/Uacute/Ucircumflex/Udieresis/Yacute /Thorn/germandbls/agrave/aacute/acircumflex/atilde/adieresis /aring/ae/ccedilla/egrave/eacute/ecircumflex/edieresis/igrave /iacute/icircumflex/idieresis/eth/ntilde/ograve/oacute/ocircumflex /otilde/odieresis/divide/oslash/ugrave/uacute/ucircumflex/udieresis /yacute/thorn/ydieresis ] def /Times-Roman reencodeISO def /Times-Bold reencodeISO def /arrowHeight 8 def /arrowWidth 4 def /none null def /numGraphicParameters 17 def /stringLimit 65535 def /Begin { save numGraphicParameters dict begin } def /End { end restore } def /SetB { dup type /nulltype eq { pop false /brushRightArrow idef false /brushLeftArrow idef true /brushNone idef } { /brushDashOffset idef /brushDashArray idef 0 ne /brushRightArrow idef 0 ne /brushLeftArrow idef /brushWidth idef false /brushNone idef } ifelse } def /SetCFg { /fgblue idef /fggreen idef /fgred idef } def /SetCBg { /bgblue idef /bggreen idef /bgred idef } def /SetF { /printSize idef /printFont idef } def /SetP { dup type /nulltype eq { pop true /patternNone idef } { dup -1 eq { /patternGrayLevel idef /patternString idef } { /patternGrayLevel idef } ifelse false /patternNone idef } ifelse } def /BSpl { 0 begin storexyn newpath n 1 gt { 0 0 0 0 0 0 1 1 true subspline n 2 gt { 0 0 0 0 1 1 2 2 false subspline 1 1 n 3 sub { /i exch def i 1 sub dup i dup i 1 add dup i 2 add dup false subspline } for n 3 sub dup n 2 sub dup n 1 sub dup 2 copy false subspline } if n 2 sub dup n 1 sub dup 2 copy 2 copy false subspline patternNone not brushLeftArrow not brushRightArrow not and and { ifill } if brushNone not { istroke } if 0 0 1 1 leftarrow n 2 sub dup n 1 sub dup rightarrow } if end } dup 0 4 dict put def /Circ { newpath 0 360 arc patternNone not { ifill } if brushNone not { istroke } if } def /CBSpl { 0 begin dup 2 gt { storexyn newpath n 1 sub dup 0 0 1 1 2 2 true subspline 1 1 n 3 sub { /i exch def i 1 sub dup i dup i 1 add dup i 2 add dup false subspline } for n 3 sub dup n 2 sub dup n 1 sub dup 0 0 false subspline n 2 sub dup n 1 sub dup 0 0 1 1 false subspline patternNone not { ifill } if brushNone not { istroke } if } { Poly } ifelse end } dup 0 4 dict put def /Elli { 0 begin newpath 4 2 roll translate scale 0 0 1 0 360 arc patternNone not { ifill } if brushNone not { istroke } if end } dup 0 1 dict put def /Line { 0 begin 2 storexyn newpath x 0 get y 0 get moveto x 1 get y 1 get lineto brushNone not { istroke } if 0 0 1 1 leftarrow 0 0 1 1 rightarrow end } dup 0 4 dict put def /MLine { 0 begin storexyn newpath n 1 gt { x 0 get y 0 get moveto 1 1 n 1 sub { /i exch def x i get y i get lineto } for patternNone not brushLeftArrow not brushRightArrow not and and { ifill } if brushNone not { istroke } if 0 0 1 1 leftarrow n 2 sub dup n 1 sub dup rightarrow } if end } dup 0 4 dict put def /Poly { 3 1 roll newpath moveto -1 add { lineto } repeat closepath patternNone not { ifill } if brushNone not { istroke } if } def /Rect { 0 begin /t exch def /r exch def /b exch def /l exch def newpath l b moveto l t lineto r t lineto r b lineto closepath patternNone not { ifill } if brushNone not { istroke } if end } dup 0 4 dict put def /Text { ishow } def /idef { dup where { pop pop pop } { exch def } ifelse } def /ifill { 0 begin gsave patternGrayLevel -1 ne { fgred bgred fgred sub patternGrayLevel mul add fggreen bggreen fggreen sub patternGrayLevel mul add fgblue bgblue fgblue sub patternGrayLevel mul add setrgbcolor eofill } { eoclip originalCTM setmatrix pathbbox /t exch def /r exch def /b exch def /l exch def /w r l sub ceiling cvi def /h t b sub ceiling cvi def /imageByteWidth w 8 div ceiling cvi def /imageHeight h def bgred bggreen bgblue setrgbcolor eofill fgred fggreen fgblue setrgbcolor w 0 gt h 0 gt and { l b translate w h scale w h true [w 0 0 h neg 0 h] { patternproc } imagemask } if } ifelse grestore end } dup 0 8 dict put def /istroke { gsave brushDashOffset -1 eq { [] 0 setdash 1 setgray } { brushDashArray brushDashOffset setdash fgred fggreen fgblue setrgbcolor } ifelse brushWidth setlinewidth originalCTM setmatrix stroke grestore } def /ishow { 0 begin gsave fgred fggreen fgblue setrgbcolor printFont printSize scalefont setfont /descender 0 printFont /FontBBox get 1 get printFont /FontMatrix get transform exch pop def /vertoffset 1 printSize sub descender sub def { 0 vertoffset moveto show /vertoffset vertoffset printSize sub def } forall grestore end } dup 0 2 dict put def /patternproc { 0 begin /patternByteLength patternString length def /patternHeight patternByteLength 8 mul sqrt cvi def /patternWidth patternHeight def /patternByteWidth patternWidth 8 idiv def /imageByteMaxLength imageByteWidth imageHeight mul stringLimit patternByteWidth sub min def /imageMaxHeight imageByteMaxLength imageByteWidth idiv patternHeight idiv patternHeight mul patternHeight max def /imageHeight imageHeight imageMaxHeight sub store /imageString imageByteWidth imageMaxHeight mul patternByteWidth add string def 0 1 imageMaxHeight 1 sub { /y exch def /patternRow y patternByteWidth mul patternByteLength mod def /patternRowString patternString patternRow patternByteWidth getinterval def /imageRow y imageByteWidth mul def 0 patternByteWidth imageByteWidth 1 sub { /x exch def imageString imageRow x add patternRowString putinterval } for } for imageString end } dup 0 12 dict put def /min { dup 3 2 roll dup 4 3 roll lt { exch } if pop } def /max { dup 3 2 roll dup 4 3 roll gt { exch } if pop } def /arrowhead { 0 begin transform originalCTM itransform /taily exch def /tailx exch def transform originalCTM itransform /tipy exch def /tipx exch def /dy tipy taily sub def /dx tipx tailx sub def /angle dx 0 ne dy 0 ne or { dy dx atan } { 90 } ifelse def gsave originalCTM setmatrix tipx tipy translate angle rotate newpath 0 0 moveto arrowHeight neg arrowWidth 2 div lineto arrowHeight neg arrowWidth 2 div neg lineto closepath patternNone not { originalCTM setmatrix /padtip arrowHeight 2 exp 0.25 arrowWidth 2 exp mul add sqrt brushWidth mul arrowWidth div def /padtail brushWidth 2 div def tipx tipy translate angle rotate padtip 0 translate arrowHeight padtip add padtail add arrowHeight div dup scale arrowheadpath ifill } if brushNone not { originalCTM setmatrix tipx tipy translate angle rotate arrowheadpath istroke } if grestore end } dup 0 9 dict put def /arrowheadpath { newpath 0 0 moveto arrowHeight neg arrowWidth 2 div lineto arrowHeight neg arrowWidth 2 div neg lineto closepath } def /leftarrow { 0 begin y exch get /taily exch def x exch get /tailx exch def y exch get /tipy exch def x exch get /tipx exch def brushLeftArrow { tipx tipy tailx taily arrowhead } if end } dup 0 4 dict put def /rightarrow { 0 begin y exch get /tipy exch def x exch get /tipx exch def y exch get /taily exch def x exch get /tailx exch def brushRightArrow { tipx tipy tailx taily arrowhead } if end } dup 0 4 dict put def /midpoint { 0 begin /y1 exch def /x1 exch def /y0 exch def /x0 exch def x0 x1 add 2 div y0 y1 add 2 div end } dup 0 4 dict put def /thirdpoint { 0 begin /y1 exch def /x1 exch def /y0 exch def /x0 exch def x0 2 mul x1 add 3 div y0 2 mul y1 add 3 div end } dup 0 4 dict put def /subspline { 0 begin /movetoNeeded exch def y exch get /y3 exch def x exch get /x3 exch def y exch get /y2 exch def x exch get /x2 exch def y exch get /y1 exch def x exch get /x1 exch def y exch get /y0 exch def x exch get /x0 exch def x1 y1 x2 y2 thirdpoint /p1y exch def /p1x exch def x2 y2 x1 y1 thirdpoint /p2y exch def /p2x exch def x1 y1 x0 y0 thirdpoint p1x p1y midpoint /p0y exch def /p0x exch def x2 y2 x3 y3 thirdpoint p2x p2y midpoint /p3y exch def /p3x exch def movetoNeeded { p0x p0y moveto } if p1x p1y p2x p2y p3x p3y curveto end } dup 0 17 dict put def /storexyn { /n exch def /y n array def /x n array def n 1 sub -1 0 { /i exch def y i 3 2 roll put x i 3 2 roll put } for } def %%EndProlog %I Idraw 9 Grid 4.80467 %%Page: 1 1 Begin %I b u %I cfg u %I cbg u %I f u %I p u %I t u /originalCTM matrix currentmatrix def Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 262.235 341.235 ] concat %I [ (Number of Siblings) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 323.075 400.097 ] concat %I [ (Number of Bits) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 333.859 535.541 ] concat %I [ (Number of Pins) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 351.531 636.681 ] concat %I [ (Speedup) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 350.491 495.309 ] concat %I [ (Area) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 356.495 ] concat %I [ (0.60) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 380.435 ] concat %I [ (0.65) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 403.745 ] concat %I [ (0.70) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 427.685 ] concat %I [ (0.75) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 450.995 ] concat %I [ (0.80) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 474.935 ] concat %I [ (0.85) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 498.875 ] concat %I [ (0.90) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 522.185 ] concat %I [ (0.95) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 546.125 ] concat %I [ (1.00) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 569.435 ] concat %I [ (1.05) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 593.375 ] concat %I [ (1.10) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 616.685 ] concat %I [ (1.15) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.63 0 0 0.63 149.899 640.625 ] concat %I [ (1.20) ] Text End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 277 443 277 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 315 443 315 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 352 443 352 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 390 443 390 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 427 443 427 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 465 443 465 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.425 177.575 ] concat %I 2 43 503 443 503 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 540 443 540 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 578 443 578 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 615 443 615 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 653 443 653 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 690 443 690 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 43 728 443 728 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 113 744 113 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 217 744 217 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 321 744 321 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 2 425 744 425 275 2 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 5 43 744 43 275 443 275 443 744 43 744 5 MLine End Begin %I MLine %I b -1 0 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 8 61 578 113 377 165 296 217 318 269 325 321 318 373 334 425 354 8 MLine End Begin %I MLine %I b -3856 0 0 0 [4 4 4 4] 17 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 8 61 578 113 568 165 552 217 564 269 565 321 554 373 544 425 535 8 MLine End Begin %I MLine %I b -13108 0 0 0 [2 2 2 2 2 2 2 2] 17 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 8 61 578 113 608 165 601 217 656 269 691 321 691 373 710 425 723 8 MLine End Begin %I MLine %I b -21846 0 0 0 [1] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg none SetP %I p n %I t [ 0.63 0 0 0.63 137.929 177.575 ] concat %I 8 61 578 113 514 165 480 217 497 269 500 321 490 373 491 425 491 8 MLine End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 148.545 307.81 ] concat %I 801 174 801 154 Line End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 -48.015 307.81 ] concat %I 801 174 801 154 Line End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 17.505 308.09 ] concat %I 801 174 801 154 Line End Begin %I Line %I b 65535 1 0 0 [] 0 SetB %I cfg Black 0 0 0 SetCFg %I cbg White 1 1 1 SetCBg %I p 0 SetP %I t [ 0.28 0 0 0.28 83.025 308.09 ] concat %I 801 174 801 154 Line End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 174.585 349.53 ] concat %I [ (1) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 207.065 349.53 ] concat %I [ (2) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 240.385 349.53 ] concat %I [ (3) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 272.585 349.81 ] concat %I [ (4) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 305.905 349.53 ] concat %I [ (5) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 338.945 349.53 ] concat %I [ (6) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 371.425 349.53 ] concat %I [ (7) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0.56 0 0 0.56 403.625 349.53 ] concat %I [ (8) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-bold-r-*-140-75-75-* Times-Bold 14 SetF %I t [ 0.8 0 0 0.8 283.2 330.8 ] concat %I [ (\(b\)) ] Text End Begin %I Text %I cfg Black 0 0 0 SetCFg %I f *-times-medium-r-*-140-75-75-* Times-Roman 14 SetF %I t [ 0 -0.72 0.72 0 142.08 593.32 ] concat %I [ (Normalized FPGA Performance and Density Measures) ] Text End End %I eop showpage %%Trailer end %%EndDocument FMENDEPSF 54 72 294.12 738 C 0 0 612 792 C 0 10 Q 0 X 0 K -0.16 (respectively) 317.88 731.33 P -0.16 (. The label on a LUT denotes its size \050number of) 365.52 731.33 P 0.78 (inputs\051, heavy lines between LUT) 317.88 719.33 P 0.78 (s denote hard-wired con-) 456.03 719.33 P 0.14 (nections from the output of one to the input of the next, and) 317.88 707.33 P (the lighter lines indicate programmable connections.) 317.88 695.33 T 1 F (Figur) 317.88 534.4 T (e 5: Ar) 341.58 534.4 T (chitectur) 370.81 534.4 T (es Constituting the Best Families) 408.93 534.4 T (for the Ar) 317.88 524.4 T (ea-Mapped Cir) 360.44 524.4 T (cuits.) 425.49 524.4 T (Figur) 317.88 362.39 T (e 6: Ar) 341.58 362.39 T (chitectur) 370.81 362.39 T (es Constituting the Best Families) 408.93 362.39 T (for the Delay-Mapped Cir) 317.88 352.39 T (cuits.) 429.01 352.39 T 0 F 3.05 (The most area-ef) 339.48 330.39 P 3.05 (\336cient single HLB architecture is) 413.11 330.39 P 0.65 (shown in the 1 sibling case of Figure 5. Notice that it con-) 317.88 318.39 P 0.6 (sists of two 4-LUT) 317.88 306.39 P 0.6 (s, which have previously been shown to) 394.77 306.39 P 1.11 (be very area ef) 317.88 294.39 P 1.11 (\336cient [4], connected by 1 hard-wired con-) 380.12 294.39 P 2.53 (nection. Since every LUT must fan out, the technology) 317.88 282.39 P 0.22 (mapper can usually make good use of this hard-wire, so the) 317.88 270.39 P 0.73 (area ef) 317.88 258.39 P 0.73 (\336ciency of this architecture is not surprising. As the) 345.34 258.39 P 1.64 (number of siblings increases to 2 and 3, lar) 317.88 246.39 P 1.64 (ger LUT) 502.68 246.39 P 1.64 (s \0507-) 538.32 246.39 P 0.46 (LUT) 317.88 234.39 P 0.46 (s and 5-LUT) 336.61 234.39 P 0.46 (s\051 tend to be selected, and the 1 sibling 4-) 387.89 234.39 P 0.86 (LUT HLB is eventually replaced by a 4-LUT HLB with 3) 317.88 222.39 P 3.14 (hard-wired connections. This is an expected result; the) 317.88 210.39 P 0.8 (choice of siblings in which to implement a circuit helps to) 317.88 198.39 P 0.44 (make up for the \337exibility lost as we move toward coarser) 317.88 186.39 P 0.44 (-) 554.67 186.39 P 1.1 (grained logic blocks. Hence, the utilization of these lar) 317.88 174.39 P 1.1 (ger) 545.24 174.39 P 1.33 (logic blocks is high, and their lower routing area require-) 317.88 162.39 P (ments translate into area-ef) 317.88 150.39 T (\336cient circuits.) 426.22 150.39 T 0.81 (Figure 6 shows that a single 6-LUT is the best archi-) 339.48 132.39 P 0.17 (tecture for simultaneously minimizing the area and delay of) 317.88 120.39 P 0.61 (the delay-mapped circuits. While a 6-LUT is less area ef) 317.88 108.39 P 0.61 (\336-) 549.11 108.39 P 0.23 (cient than a 4-LUT) 317.88 96.39 P 0.23 (, it leads to faster circuits, and hence is a) 394.15 96.39 P 0.59 (good choice when both area and delay must be minimized.) 317.88 84.39 P 317.88 72 558 738 C 317.88 549.06 558 674 C 340.65 575.33 355.23 589.91 R 0.5 H 2 Z 0 X 0 K N 345.6 590.16 345.6 597.58 2 L N 349.38 589.98 349.38 597.4 2 L N 338.09 607.53 338.09 599.63 2 L 1 H N 342.34 590.32 342.34 598.82 2 L N 342.34 599.23 338.09 599.23 2 L N 347.71 575.33 347.71 568.04 2 L 0.5 H N 332.52 622.78 332.52 630.21 2 L N 330.9 607.93 345.48 622.51 R N 342.94 622.67 342.94 630.1 2 L N 336.05 622.76 336.05 630.19 2 L N 339.63 622.58 339.63 630.01 2 L N 352.7 590.18 352.7 597.61 2 L N 420.32 586 434.9 600.58 R N 425.27 600.83 425.27 608.25 2 L N 429.05 600.65 429.05 608.07 2 L N 417.75 618.2 417.75 610.3 2 L 1 H N 422.01 600.98 422.01 609.49 2 L N 422.01 609.89 417.75 609.89 2 L N 427.37 586 427.37 578.71 2 L 0.5 H N 412.19 633.45 412.19 640.88 2 L N 410.57 618.6 425.14 633.18 R N 422.6 633.34 422.6 640.76 2 L N 415.72 633.43 415.72 640.85 2 L N 419.3 633.25 419.3 640.67 2 L N 432.37 600.85 432.37 608.27 2 L N 388.77 584.49 405.57 599.08 R N 389.17 599.28 389.17 608.39 2 L N 391.8 599.28 391.8 608.39 2 L N 394.43 599.28 394.43 608.39 2 L N 397.07 599.28 397.07 608.39 2 L N 399.7 599.28 399.7 608.39 2 L N 402.33 599.28 402.33 608.39 2 L N 404.96 599.28 404.96 608.39 2 L N 472.34 602.29 487.12 616.88 R N 479.32 617.05 479.32 625.79 2 L N 476.24 617.05 476.24 625.79 2 L N 482.81 616.88 482.81 625.79 2 L N 486.1 616.88 486.1 625.79 2 L N 479.43 602.09 479.43 595.61 2 L N 457.96 636.32 472.75 650.9 R N 464.95 651.07 464.95 659.8 2 L N 461.86 651.07 461.86 659.8 2 L N 458.58 650.9 458.58 659.8 2 L N 468.43 650.9 468.43 659.8 2 L N 471.72 650.9 471.72 659.8 2 L N 465.05 636.11 465.05 629.63 2 L 1 H N 473.15 629.63 465.05 629.63 2 L 0 Z N 473.15 617.08 473.15 629.84 2 L N 522.18 584.27 536.76 598.84 R 0.5 H 2 Z N 527.13 599.09 527.13 606.52 2 L N 530.91 598.91 530.91 606.34 2 L N 538.04 630.81 538.04 638.23 2 L N 536.42 615.96 551 630.54 R N 548.46 630.69 548.46 638.12 2 L N 541.58 630.78 541.58 638.21 2 L N 545.15 630.6 545.15 638.03 2 L N 519.62 616.46 519.62 608.57 2 L 1 H N 523.87 599.25 523.87 607.76 2 L N 523.87 608.16 519.62 608.16 2 L N 544.12 616.06 544.12 608.57 2 L N 544.12 608.16 534.2 608.16 2 L N 533.99 608.16 533.99 599.05 2 L N 529.23 584.27 529.23 576.97 2 L 0.5 H N 514.05 631.72 514.05 639.14 2 L 1 H N 512.43 616.87 527.01 631.45 R 0.5 H N 524.47 631.6 524.47 639.03 2 L N 517.58 631.69 517.58 639.12 2 L N 521.16 631.51 521.16 638.94 2 L N 508.58 660.27 508.58 667.69 2 L N 506.96 645.42 521.54 660 R N 519 660.16 519 667.58 2 L N 512.11 660.25 512.11 667.67 2 L N 515.69 660.07 515.69 667.49 2 L N 514.05 639.14 514.05 645.01 2 L 1 H N 396.86 584.7 396.86 579.03 2 L 0.5 H 0 Z N 492.6 577.66 509.41 592.24 R 2 Z N 493 592.44 493 601.56 2 L N 495.64 592.44 495.64 601.56 2 L N 498.27 592.44 498.27 601.56 2 L N 500.9 592.44 500.9 601.56 2 L N 503.53 592.44 503.53 601.56 2 L N 506.17 592.44 506.17 601.56 2 L N 508.8 592.44 508.8 601.56 2 L N 500.7 577.86 500.7 572.19 2 L 0 Z N 320.21 658.42 409.96 665.17 R 7 X V 0 8 Q 0 X (Programmable Connection) 320.21 659.83 T 320.46 649.42 402.96 656.17 R 7 X V 0 X (Hard-wired Connection) 320.46 650.83 T 413.71 662.17 423.46 662.17 2 L 2 Z N 411.46 652.92 422.46 652.92 2 L 1 H N 330.17 551 373.5 561.83 R 7 X V 0 9 Q 0 X (1 Sibling) 330.17 555.83 T 393.33 552.33 440 562.33 R 7 X V 0 X (2 Siblings) 393.33 556.33 T 487.18 554.5 531.34 563.83 R 7 X V 0 X (3 Siblings) 487.18 557.83 T 335.75 610 343.75 618.5 R 7 X V 0 8 Q 0 X (4) 335.75 613.17 T 346.75 577.5 354.75 586 R 7 X V 0 X (4) 346.75 580.67 T 414.75 622 422.75 630.5 R 7 X V 0 X (4) 414.75 625.17 T 425.75 588 433.75 596.5 R 7 X V 0 X (4) 425.75 591.17 T 511.75 648 519.75 656.5 R 7 X V 0 X (4) 511.75 651.17 T 517.25 619 525.25 627.5 R 7 X V 0 X (4) 517.25 622.17 T 541.25 618.5 549.25 627 R 7 X V 0 X (4) 541.25 621.67 T 527.25 586 535.25 594.5 R 7 X V 0 X (4) 527.25 589.17 T (7) 498.75 583.17 T (7) 395.25 590.67 T (5) 477.75 607.67 T (5) 462.75 642.17 T 371.5 644 371.5 567.5 2 L 0.5 H 4 X N 446 664 446 567.5 2 L 3 X N 317.88 72 558 738 C 0 0 612 792 C 317.88 72 558 738 C 317.89 381.05 557.99 499.06 C 377.66 409.41 392.24 423.99 R 0.5 H 2 Z 0 X 0 K N 382.17 424.11 382.17 431.53 2 L N 385.25 424.11 385.25 431.53 2 L N 388.34 424.11 388.34 431.53 2 L N 379.08 424.11 379.08 431.53 2 L N 391.43 424.11 391.43 431.53 2 L N 384.95 409.42 384.95 402.12 2 L N 532.59 425.25 532.59 432.67 2 L N 530.77 410.58 545.35 425.16 R N 543.01 425.25 543.01 432.67 2 L N 536.07 425.25 536.07 432.67 2 L N 539.54 425.25 539.54 432.67 2 L N 537.52 410.33 537.52 404.46 2 L N 325.69 443.06 343.1 457.64 R N 327.01 457.84 327.01 466.95 2 L N 329.94 457.84 329.94 466.95 2 L N 332.87 457.84 332.87 466.95 2 L N 335.8 457.84 335.8 466.95 2 L N 338.73 457.84 338.73 466.95 2 L N 341.66 457.84 341.66 466.95 2 L N 334.08 443.26 334.08 437.59 2 L 0 Z N 475.33 417.33 489.91 431.91 R 2 Z N 479.83 432.02 479.83 439.45 2 L N 482.92 432.02 482.92 439.45 2 L N 486.01 432.02 486.01 439.45 2 L N 476.74 432.02 476.74 439.45 2 L N 489.1 432.02 489.1 439.45 2 L N 482.62 417.33 482.62 410.04 2 L N 402.76 421.95 421.39 436.53 R N 412.14 421.5 412.14 416.24 2 L N 406.47 436.87 406.47 443.93 2 L 1 H N 398.17 444.18 406.07 444.18 2 L N 376.1 440.74 402.62 440.74 2 L N 397.76 447.22 397.76 444.16 2 L N 421.05 447.42 421.05 444.18 2 L N 417 437.09 417 443.57 2 L N 417.2 443.98 420.65 443.98 2 L N 375.29 447.52 375.29 440.84 2 L N 443.73 447.52 443.73 441.12 2 L N 403.23 436.87 403.23 440.64 2 L N 420.85 436.67 420.85 440.64 2 L N 421.1 441.14 442.92 441.14 2 L N 409.08 436.87 409.08 444.16 2 L 0.5 H N 411.51 436.87 411.51 444.16 2 L N 413.94 436.87 413.94 444.16 2 L N 366.69 448.28 384.11 462.86 R N 368.02 463.06 368.02 472.17 2 L N 370.95 463.06 370.95 472.17 2 L N 373.88 463.06 373.88 472.17 2 L N 376.81 463.06 376.81 472.17 2 L N 379.74 463.06 379.74 472.17 2 L N 382.67 463.06 382.67 472.17 2 L N 388.76 447.67 406.18 462.25 R N 390.09 462.45 390.09 471.56 2 L N 393.02 462.45 393.02 471.56 2 L N 395.95 462.45 395.95 471.56 2 L N 398.88 462.45 398.88 471.56 2 L N 401.81 462.45 401.81 471.56 2 L N 404.74 462.45 404.74 471.56 2 L N 412.25 447.67 429.67 462.25 R N 413.58 462.45 413.58 471.56 2 L N 416.51 462.45 416.51 471.56 2 L N 419.44 462.45 419.44 471.56 2 L N 422.37 462.45 422.37 471.56 2 L N 425.3 462.45 425.3 471.56 2 L N 428.23 462.45 428.23 471.56 2 L N 434.93 447.87 452.35 462.45 R N 436.26 462.65 436.26 471.77 2 L N 439.19 462.65 439.19 471.77 2 L N 442.12 462.65 442.12 471.77 2 L N 445.05 462.65 445.05 471.77 2 L N 447.98 462.65 447.98 471.77 2 L N 450.91 462.65 450.91 471.77 2 L N 324.23 488.09 413.98 494.84 R 7 X V 0 8 Q 0 X (Programmable Connection) 324.23 489.51 T 324.48 479.09 406.98 485.84 R 7 X V 0 X (Hard-wired Connection) 324.48 480.51 T 417.73 491.84 427.48 491.84 2 L N 415.48 482.59 426.48 482.59 2 L 1 H N (5) 480.5 423.17 T (5) 383 415.67 T (7) 396 452.67 T (7) 419 452.67 T (7) 441.5 453.17 T (7) 409.5 426.17 T (7) 373 452.67 T 503.76 435.95 522.39 450.53 R 0.5 H N 513.14 435.5 513.14 430.24 2 L N 507.47 450.87 507.47 457.93 2 L 1 H N 499.17 458.18 507.07 458.18 2 L N 477.1 454.74 503.62 454.74 2 L N 498.76 461.22 498.76 458.16 2 L N 522.05 461.42 522.05 458.18 2 L N 518 451.09 518 457.57 2 L N 518.2 457.98 521.65 457.98 2 L N 476.29 461.52 476.29 454.84 2 L N 544.73 461.52 544.73 455.12 2 L N 504.23 450.87 504.23 454.64 2 L N 521.85 450.67 521.85 454.64 2 L N 522.1 455.14 543.92 455.14 2 L N 510.08 450.87 510.08 458.16 2 L 0.5 H N 512.51 450.87 512.51 458.16 2 L N 514.94 450.87 514.94 458.16 2 L N 467.69 462.28 485.11 476.86 R N 469.02 477.06 469.02 486.17 2 L N 471.95 477.06 471.95 486.17 2 L N 474.88 477.06 474.88 486.17 2 L N 477.81 477.06 477.81 486.17 2 L N 480.74 477.06 480.74 486.17 2 L N 483.67 477.06 483.67 486.17 2 L N 489.76 461.67 507.18 476.25 R N 491.09 476.45 491.09 485.56 2 L N 494.02 476.45 494.02 485.56 2 L N 496.95 476.45 496.95 485.56 2 L N 499.88 476.45 499.88 485.56 2 L N 502.81 476.45 502.81 485.56 2 L N 505.74 476.45 505.74 485.56 2 L N 513.25 461.67 530.67 476.25 R N 514.58 476.45 514.58 485.56 2 L N 517.51 476.45 517.51 485.56 2 L N 520.44 476.45 520.44 485.56 2 L N 523.37 476.45 523.37 485.56 2 L N 526.3 476.45 526.3 485.56 2 L N 529.23 476.45 529.23 485.56 2 L N 535.93 461.87 553.35 476.45 R N 537.26 476.65 537.26 485.77 2 L N 540.19 476.65 540.19 485.77 2 L N 543.12 476.65 543.12 485.77 2 L N 546.05 476.65 546.05 485.77 2 L N 548.98 476.65 548.98 485.77 2 L N 551.91 476.65 551.91 485.77 2 L N (7) 497 466.67 T (7) 520 466.67 T (7) 542.5 467.17 T (7) 510.5 440.17 T (7) 474 466.67 T 332 445 339 453.5 R 7 X V 0 X (6) 332 448.17 T 536 412.5 543 421 R 7 X V 0 X (4) 536 415.67 T 325.16 385.7 368.49 396.53 R 7 X V 0 9 Q 0 X (1 Sibling) 325.16 390.53 T 392.83 386.53 439.49 396.53 R 7 X V 0 X (2 Siblings) 392.83 390.53 T 494.67 385.7 538.84 395.03 R 7 X V 0 X (3 Siblings) 494.67 389.03 T 355.5 472.5 355.5 402.5 2 L 3 X N 458.5 487 458.5 400 2 L N 317.88 72 558 738 C 0 0 612 792 C FMENDPAGE %%EndPage: "5" 6 %%Page: "6" 6 612 792 0 FMBEGINPAGE 279 38.14 315 54 R 7 X 0 K V 0 10 Q 0 X (6) 300.6 47.33 T 0.23 (In Figure 6, notice that when one goes from one to two sib-) 54 731.33 P 0.74 (lings, a single six-input LUT is replaced by a lar) 54 719.33 P 0.74 (ge 7-LUT) 253.69 719.33 P 1.22 (HLB and a single \336ve-input LUT) 54 707.33 P 1.22 (. The six-input LUT has) 192.9 707.33 P 1.85 (been replaced by one more coarse-grained HLB and one) 54 695.33 P 1.44 (more \336ne-grained HLB. Clearly) 54 683.33 P 1.44 (, when forced to use only) 185.9 683.33 P 0.12 (one general-purpose FPGA architecture, we had to compro-) 54 671.33 P 0.28 (mise between the two and use the six-input LUT) 54 659.33 P 0.28 (. Similarly) 249.79 659.33 P 0.28 (,) 291.62 659.33 P 0.46 (one can see from Figure 5 that the single best FPGA archi-) 54 647.33 P 0.2 (tecture for area-mapped circuits \0501 sibling\051 is not one of the) 54 635.33 P 0.95 (architectures chosen for the three-sibling family; again the) 54 623.33 P (single architecture was a compromise choice.) 54 611.33 T 0.21 (T) 75.6 593.33 P 0.21 (ables 2 and 3 show the ef) 81.01 593.33 P 0.21 (fect of varying D) 183.11 593.33 P 0 8 Q 0.17 (R) 252.28 590.83 P 0 10 Q 0.21 ( and Pin-) 257.61 593.33 P -0.22 (fac over a wide range. Notice that the parameter we are opti-) 54 581.33 P 0.49 (mizing, the area reduction for area-mapped circuits and the) 54 569.33 P 0.62 (sum of the area and delay reductions for the delay-mapped) 54 557.33 P -0.03 (circuits, is fairly constant regardless of the values of D) 54 545.33 P 0 8 Q -0.03 (R) 271.89 542.83 P 0 10 Q -0.03 ( and) 277.22 545.33 P 2.42 (Pinfac. The sibling architectures chosen for each family) 54 533.33 P 0.58 (change somewhat when the extreme values of D) 54 521.33 P 0 8 Q 0.47 (R) 251.53 518.83 P 0 10 Q 0.58 ( and Pin-) 256.86 521.33 P 1.39 (fac are used in our delay and area models, but the trends) 54 509.33 P (observed as the family size increases are the same.) 54 497.33 T 2.82 (W) 75.6 141.33 P 2.82 (e also conducted experiments in which) 84.24 141.33 P 2 F 2.82 (both) 258.82 141.33 P 0 F 2.82 ( the) 276.59 141.33 P 0.79 (area-mapped and delay-mapped circuits were implemented) 54 129.33 P 1.9 (in a single family) 54 117.33 P 1.9 (. This case is of interest because some) 128.73 117.33 P 1.45 (applications may be limited by the capacity of an FPGA,) 54 105.33 P 0.74 (while others are limited by its speed. Consequently) 54 93.33 P 0.74 (, manu-) 262.85 93.33 P 0.11 (facturers desire FPGA families capable of ef) 54 81.33 P 0.11 (\336ciently imple-) 232.65 81.33 P 1 F (T) 53.82 475.33 T (ABLE 2. Effect of V) 59.75 475.33 T (arying D) 144.6 475.33 T 1 8 Q (R) 182.08 472.83 T 1 10 Q ( and Pinfac Parameters) 187.85 475.33 T (for Ar) 53.82 463.33 T (ea-Mapped Cir) 80.56 463.33 T (cuits) 145.61 463.33 T 1 9 Q (D) 62.45 421 T 1 7 Q (R) 68.94 418.75 T 1 9 Q (\050ns\051) 60.98 410 T (Pin-) 89.03 421 T (fac) 91.28 410 T (5) 132.21 443 T (Sibling) 120.97 432 T (Ar) 125.06 421 T (ea) 135.38 421 T (Red.) 125.6 410 T (8) 178.29 443 T (Sibling) 167.05 432 T (Ar) 171.14 421 T (ea) 181.46 421 T (Red.) 171.68 410 T (5) 224.01 432 T (Sibling) 212.77 421 T (Speedup) 209.78 410 T (8) 269.37 432 T (Sibling) 258.13 421 T (Speedup) 255.14 410 T 0 10 Q (4.0) 61.97 394.33 T (14) 92.02 394.33 T (10.6%) 121.55 394.33 T (12.5%) 167.63 394.33 T (1.19) 217.51 394.33 T (1.20) 262.88 394.33 T (1.0) 61.97 378.33 T (14) 92.02 378.33 T (10.6%) 121.55 378.33 T (12.5%) 167.63 378.33 T (1.16) 217.51 378.33 T (1.15) 262.88 378.33 T (10.) 61.97 362.33 T (14) 92.02 362.33 T (10.6%) 121.55 362.33 T (12.5%) 167.63 362.33 T (1.21) 217.51 362.33 T (1.23) 262.88 362.33 T (4.0) 61.97 346.33 T (4) 94.52 346.33 T (9.4%) 124.05 346.33 T (10.4%) 167.63 346.33 T (1.02) 217.51 346.33 T (1.01) 262.88 346.33 T (4.0) 61.97 330.33 T (30) 92.02 330.33 T (14.2%) 121.55 330.33 T (15.6%) 167.63 330.33 T (1.09) 217.51 330.33 T (1.07) 262.88 330.33 T 1 F (T) 53.82 306.33 T (ABLE 3. Effect of V) 59.75 306.33 T (arying D) 144.6 306.33 T 1 8 Q (R) 182.08 303.83 T 1 10 Q ( and Pinfac Parameters) 187.85 306.33 T (for Delay-Mapped Cir) 53.82 294.33 T (cuits) 149.13 294.33 T 1 9 Q (D) 62.45 252 T 1 7 Q (R) 68.94 249.75 T 1 9 Q (\050ns\051) 60.98 241 T (Pin-) 89.03 252 T (fac) 91.28 241 T (5) 132.21 274 T (Sibling) 120.97 263 T (Ar) 125.06 252 T (ea) 135.38 252 T (Red.) 125.6 241 T (8) 178.29 274 T (Sibling) 167.05 263 T (Ar) 171.14 252 T (ea) 181.46 252 T (Red.) 171.68 241 T (5) 224.01 263 T (Sibling) 212.77 252 T (Speedup) 209.78 241 T (8) 269.37 263 T (Sibling) 258.13 252 T (Speedup) 255.14 241 T 0 10 Q (4.0) 61.97 225.33 T (14) 92.02 225.33 T (10.3%) 121.55 225.33 T (1) 167.82 225.33 T (1.5%) 172.44 225.33 T (1.15) 217.51 225.33 T (1.19) 262.88 225.33 T (1.0) 61.97 209.33 T (14) 92.02 209.33 T (1) 121.74 209.33 T (1.7%) 126.36 209.33 T (12.0%) 167.63 209.33 T (1.07) 217.51 209.33 T (1.09) 262.88 209.33 T (10.) 61.97 193.33 T (14) 92.02 193.33 T (6.0%) 124.05 193.33 T (8.7%) 170.13 193.33 T (1.30) 217.51 193.33 T (1.32) 262.88 193.33 T (4.0) 61.97 177.33 T (4) 94.52 177.33 T (-0.5%) 122.39 177.33 T (-0.9%) 168.47 177.33 T (1.23) 217.51 177.33 T (1.31) 262.88 177.33 T (4.0) 61.97 161.33 T (30) 92.02 161.33 T (2.9%) 124.05 161.33 T (6.1%) 170.13 161.33 T (1.24) 217.51 161.33 T (1.25) 262.88 161.33 T 53.82 456.75 53.82 325.25 2 L V 0.5 H 0 Z N 82.62 457.25 82.62 324.75 2 L V N 111.42 457.25 111.42 324.75 2 L V N 157.5 457.25 157.5 324.75 2 L V N 203.58 457.25 203.58 324.75 2 L V N 248.94 457.25 248.94 324.75 2 L V N 294.3 456.75 294.3 325.25 2 L V N 53.57 457 294.55 457 2 L V N 54.07 406.25 294.05 406.25 2 L V N 54.07 403.75 294.05 403.75 2 L V N 53.57 389 294.55 389 2 L V N 53.57 373 294.55 373 2 L V N 53.57 357 294.55 357 2 L V N 53.57 341 294.55 341 2 L V N 53.57 325 294.55 325 2 L V N 53.82 287.75 53.82 156.25 2 L V N 82.62 288.25 82.62 155.75 2 L V N 111.42 288.25 111.42 155.75 2 L V N 157.5 288.25 157.5 155.75 2 L V N 203.58 288.25 203.58 155.75 2 L V N 248.94 288.25 248.94 155.75 2 L V N 294.3 287.75 294.3 156.25 2 L V N 53.57 288 294.55 288 2 L V N 54.07 237.25 294.05 237.25 2 L V N 54.07 234.75 294.05 234.75 2 L V N 53.57 220 294.55 220 2 L V N 53.57 204 294.55 204 2 L V N 53.57 188 294.55 188 2 L V N 53.57 172 294.55 172 2 L V N 53.57 156 294.55 156 2 L V N 0.37 (menting circuits that have been optimized for either area or) 317.88 731.33 P 1.62 (delay) 317.88 719.33 P 1.62 (. In this case we chose the siblings to minimize the) 338.88 719.33 P 0.8 (sum of area and delay) 317.88 707.33 P 0.8 (, and found that a family with 8 sib-) 408.11 707.33 P 0.06 (lings was 13.7% smaller and 18% faster than the best single) 317.88 695.33 P (HLB FPGA architecture for our benchmark circuits.) 317.88 683.33 T 1 12 Q (4 Performance of an FPGA Family Composed) 317.88 658 T (of Heter) 317.88 644 T (ogeneous Logic Block Ar) 359.95 644 T (chitectur) 487.33 644 T (es) 533.08 644 T 0 10 Q -0.09 (As described in Section 3, we construct an FPGA fam-) 339.48 625.33 P 1.36 (ily by choosing an appropriate number of siblings from a) 317.88 613.33 P -0.04 (pool of possible architectures. The architectural \322pool\323 used) 317.88 601.33 P -0.01 (in this section consisted of 45 dif) 317.88 589.33 P -0.01 (ferent FPGAs with a heter-) 449.79 589.33 P 0.24 (ogeneous mixture of two dif) 317.88 577.33 P 0.24 (ferent types of logic blocks. As) 431.9 577.33 P 0.4 (outlined in [9, 10], each FPGA has logic blocks of two dif-) 317.88 565.33 P 0.04 (ferent sizes. The de\336ning parameters for each FPGA are the) 317.88 553.33 P 0.86 (size of the small LUT) 317.88 541.33 P 0.86 (, s, the size of the lar) 407.72 541.33 P 0.86 (ge LUT) 495.39 541.33 P 0.86 (, p, and) 526.87 541.33 P 0.67 (the ratio of the number of small logic blocks to lar) 317.88 529.33 P 0.67 (ge logic) 525.41 529.33 P -0.21 (blocks, r = N) 317.88 517.33 P 0 8 Q -0.17 (S) 369.53 514.83 P 0 10 Q -0.21 (/N) 373.97 517.33 P 0 8 Q -0.17 (P) 383.97 514.83 P 0 10 Q -0.21 (. Figure 7 shows an example of a heteroge-) 387.3 517.33 P (neous FPGA with p = 4, s = 2, and r = 2.) 317.88 505.33 T 1 F (Figur) 317.88 202.02 T (e 7: Heter) 341.58 202.02 T (ogeneous FPGA ar) 383.57 202.02 T (chitectur) 463.9 202.02 T (e with p=4, s) 502.02 202.02 T (= 2 and r = 2.) 317.88 192.02 T 0 F 0.39 (The architectures in the \322pool\323 used to create families) 339.48 170.02 P 2.09 (have all possible heterogeneous logic block architectures) 317.88 158.02 P 0.77 (with p between 3 and 7, s between 2 and 6, and r equal to) 317.88 146.02 P 0.92 (0.5, 1, or 2. The experimental procedure is very similar to) 317.88 134.02 P 1.91 (that described in Section 3.1, with two exceptions. First,) 317.88 122.02 P 0.39 (delay statistics were not computed in [10], so we select our) 317.88 110.02 P 1.11 (families to minimize area alone, and we cannot determine) 317.88 98.02 P 0.16 (the speedup. Secondly) 317.88 86.02 P 0.16 (, since we are using a pool of only 45) 407.21 86.02 P 317.88 72 558 738 C 317.88 216.69 558 484 C 333.5 237.59 527.89 364.79 R 7 X 0 K V 2 H 2 Z 0 X N 340.7 331.19 383.9 359.99 R 7 X V 0.5 H 0 X N 347.9 338.39 362.3 352.79 R 7 X V 0 X N 369.5 348.92 376.7 356.12 R 7 X V 0 X N 369.5 335.19 376.7 342.39 R 7 X V 0 X N 405.5 331.19 448.7 359.99 R 7 X V 0 X N 412.7 338.39 427.1 352.79 R 7 X V 0 X N 434.3 348.92 441.5 356.12 R 7 X V 0 X N 434.3 335.19 441.5 342.39 R 7 X V 0 X N 470.3 331.19 513.49 359.99 R 7 X V 0 X N 477.49 338.39 491.89 352.79 R 7 X V 0 X N 499.1 348.92 506.3 356.12 R 7 X V 0 X N 499.1 335.19 506.3 342.39 R 7 X V 0 X N 340.7 287.99 383.9 316.79 R 7 X V 0 X N 347.9 295.19 362.3 309.59 R 7 X V 0 X N 369.5 305.72 376.7 312.92 R 7 X V 0 X N 369.5 291.99 376.7 299.19 R 7 X V 0 X N 405.5 287.99 448.7 316.79 R 7 X V 0 X N 412.7 295.19 427.1 309.59 R 7 X V 0 X N 434.3 305.72 441.5 312.92 R 7 X V 0 X N 434.3 291.99 441.5 299.19 R 7 X V 0 X N 470.3 287.99 513.49 316.79 R 7 X V 0 X N 477.49 295.19 491.89 309.59 R 7 X V 0 X N 499.1 305.72 506.3 312.92 R 7 X V 0 X N 499.1 291.99 506.3 299.19 R 7 X V 0 X N 340.7 244.79 383.9 273.59 R 7 X V 0 X N 347.9 251.99 362.3 266.39 R 7 X V 0 X N 369.5 262.52 376.7 269.72 R 7 X V 0 X N 369.5 248.79 376.7 255.99 R 7 X V 0 X N 405.5 244.79 448.7 273.59 R 7 X V 0 X N 412.7 251.99 427.1 266.39 R 7 X V 0 X N 434.3 262.52 441.5 269.72 R 7 X V 0 X N 434.3 248.79 441.5 255.99 R 7 X V 0 X N 470.3 244.79 513.49 273.59 R 7 X V 0 X N 477.49 251.99 491.89 266.39 R 7 X V 0 X N 499.1 262.52 506.3 269.72 R 7 X V 0 X N 499.1 248.79 506.3 255.99 R 7 X V 0 X N 371.91 407.4 477.22 474.53 R 7 X V 2 H 0 X N 383.67 418.67 431.14 458.99 R 7 X V 1 H 0 X N 440.06 413.15 466.43 436.19 R 7 X V 0 X N 360.22 435.11 383.26 435.11 2 L N 360.22 440.87 383.26 440.87 2 L N 360.22 446.63 383.26 446.63 2 L N 360.22 429.35 383.26 429.35 2 L N 447.42 413.15 447.42 401.64 2 L N 458.94 413.15 458.94 401.64 2 L N 453.18 441.95 453.18 441.95 2 L N 440.09 444.23 465.26 467.27 R 7 X V 0 X N 446.92 467.27 446.92 478.79 2 L N 458.44 467.27 458.44 478.79 2 L N 394.91 435 423.24 443.33 R 7 X V 0 8 Q 0 X (4-LUT) 394.91 438 T (2-LUT) 441.17 454.67 T (2-LUT) 441.67 423.67 T 466.5 425.83 486 425.83 2 L 0.5 H N 466.5 456.83 486 456.83 2 L N 408.5 458.83 408.5 482.83 2 L N 383 377.33 465 389.83 R 7 X V 0 9 Q 0 X (Basic T) 383 383.83 T (ile of FPGA) 410.39 383.83 T 358 218.33 497.5 228.83 R 7 X V 0 X (FPGA = Array of these Basic T) 358 222.83 T (iles) 471.58 222.83 T 317.88 72 558 738 C 0 0 612 792 C FMENDPAGE %%EndPage: "6" 7 %%Page: "7" 7 612 792 0 FMBEGINPAGE 279 38.14 315 54 R 7 X 0 K V 0 10 Q 0 X (7) 300.6 47.33 T 1.1 (dif) 54 731.33 P 1.1 (ferent architectures, it is feasible to exhaustively search) 64.92 731.33 P 0.07 (all possible families with up to 8 siblings in order to be sure) 54 719.33 P (of \336nding the best family) 54 707.33 T (.) 154.4 707.33 T -0.1 (The gains provided by applying the siblings concept to) 75.6 689.33 P -0.19 (this architectural axis are not as great as those obtained from) 54 677.33 P 0.71 (hard-wired architectures. W) 54 665.33 P 0.71 (ith 8 siblings, we obtain only a) 166.86 665.33 P 0.65 (6% area reduction, even though we are choosing our fami-) 54 653.33 P -0.09 (lies strictly to minimize area. Clearly) 54 641.33 P -0.09 (, choosing the architec-) 201.13 641.33 P 3.99 (tural dif) 54 629.33 P 3.99 (ferences between siblings wisely is crucial to) 89.74 629.33 P 0.13 (obtaining lar) 54 617.33 P 0.13 (ge density and performance gains as the family) 104.75 617.33 P 0.84 (size is increased. In order to assess the in\337uence of Pinfac) 54 605.33 P 0.52 (on these results, we let it vary from 4 to 30. T) 54 593.33 P 0.52 (able 4 shows) 241.44 593.33 P (that our results are not very sensitive to this parameter) 54 581.33 T (.) 270.24 581.33 T 1 12 Q (5 Conclusions) 54 433 T 0 10 Q 0.19 (The concept of an FPGA family allows one to explore) 75.6 414.33 P 3.57 (points in the architectural spectrum between the usual) 54 402.33 P 0.34 (extremes of general-purpose FPGAs and nonprogrammable) 54 390.33 P 2.18 (MPGAs. W) 54 378.33 P 2.18 (e have run experiments with two families of) 102.58 378.33 P -0.2 (FPGAs, and found that a family consisting of dif) 54 366.33 P -0.2 (ferent types) 247.41 366.33 P 0.7 (of hard-wired FPGA architectures outperforms one created) 54 354.33 P 0.82 (from dif) 54 342.33 P 0.82 (ferent heterogeneous logic block architectures. W) 87.67 342.33 P 0.82 (e) 289.68 342.33 P 2.55 (found that a family of eight dif) 54 330.33 P 2.55 (ferent HLB FPGAs can) 192.37 330.33 P 1.36 (implement circuits in 12 to 14% less area and with 18 to) 54 318.33 P 0.43 (20% faster critical paths than the best single HLB architec-) 54 306.33 P 0.58 (ture. While this improvement may not be enough to justify) 54 294.33 P 0.24 (the higher development and inventory costs associated with) 54 282.33 P 2.5 (marketing eight distinct FPGAs, we believe that greater) 54 270.33 P 0.37 (gains can be realized by clever choices of the sibling archi-) 54 258.33 P 0.52 (tectures, and are pursuing further research in this direction.) 54 246.33 P 1.59 (One promising direction of research involves varying not) 54 234.33 P 0.05 (only the logic block architecture of the siblings, but also the) 54 222.33 P 2.97 (routing architecture in order to increase the dif) 54 210.33 P 2.97 (ferences) 260.83 210.33 P (between siblings.) 54 198.33 T 1 12 Q (Acknowledgments) 127.09 161 T 0 10 Q 1.12 (The authors wish to thank Dr) 75.6 140.33 P 1.12 (. Kevin Chung and Mr) 197.49 140.33 P 1.12 (.) 291.62 140.33 P -0.19 (Jianshe He for providing and explaining the use of their data) 54 128.33 P (and CAD software.) 54 116.33 T 1 F (T) 58.86 559.33 T (ABLE 4. In\337uence of Pinfac on r) 64.79 559.33 T (esults.) 204.26 559.33 T (Pinfac) 81.26 526.33 T (5 Sibling Ar) 140.01 538.33 T (ea) 191.48 538.33 T (Impr) 141.41 526.33 T (ovement) 163.43 526.33 T (8 Sibling Ar) 219.21 538.33 T (ea) 270.68 538.33 T (Impr) 220.61 526.33 T (ovement) 242.63 526.33 T 0 F (4) 92.36 510.33 T (4.9%) 160.05 510.33 T (5.1%) 239.25 510.33 T (14) 89.86 494.33 T (5.1%) 160.05 494.33 T (6.0%) 239.25 494.33 T (30) 89.86 478.33 T (5.6%) 160.05 478.33 T (6.9%) 239.25 478.33 T 58.86 552.75 58.86 473.25 2 L V 0.5 H 0 Z N 130.86 553.25 130.86 472.75 2 L V N 210.06 553.25 210.06 472.75 2 L V N 289.26 552.75 289.26 473.25 2 L V N 58.61 553 289.51 553 2 L V N 59.11 522.25 289.01 522.25 2 L V N 59.11 519.75 289.01 519.75 2 L V N 58.61 505 289.51 505 2 L V N 58.61 489 289.51 489 2 L V N 58.61 473 289.51 473 2 L V N 1 12 Q (Refer) 410.08 730 T (ences) 438.49 730 T 0 10 Q ([1]) 317.88 709.33 T 0.09 (J. Rose, A. El Gamal, and A. Sangiovanni-V) 339.48 709.33 P 0.09 (incentelli,) 518.3 709.33 P 2.52 (\322Architecture of Field-Programmable Gate Arrays,\323) 339.48 697.33 P 2 F 1.73 (Pr) 339.48 685.33 P 1.73 (oceedings of the IEEE) 349.11 685.33 P 0 F 1.73 (, V) 443.4 685.33 P 1.73 (ol. 81, No. 7, pp. 1013-) 456.06 685.33 P (1029, July 1993.) 339.48 673.33 T ([2]) 317.88 655.33 T 2.11 (K. Chung, S. Singh, J. Rose, and P) 339.48 655.33 P 2.11 (. Chow) 492.24 655.33 P 2.11 (, \322Using) 522.58 655.33 P 1.99 (Hierarchical Logic Blocks to Improve the Speed of) 339.48 643.33 P 2.7 (FPGAs,\323 in) 339.48 631.33 P 1 F 2.7 (FPGAs) 394.02 631.33 P 0 F 2.7 (, W) 425.11 631.33 P 2.7 (. Moore and W) 441.33 631.33 P 2.7 (. Luk Eds.,) 509.01 631.33 P (Abingdon 1991, pp. 103-1) 339.48 619.33 T (13.) 444.88 619.33 T ([3]) 317.88 601.33 T 1.35 (K. Chung, \322Architecture and Synthesis of Field-Pro-) 339.48 601.33 P 3.46 (grammable Gate Arrays with Hard-wired Connec-) 339.48 589.33 P (tions,\323) 339.48 577.33 T 2 F (Phd Dissertation) 368.35 577.33 T 0 F (, University of T) 436.38 577.33 T (oronto, 1994.) 502.3 577.33 T ([4]) 317.88 559.33 T 2.79 (J. S. Rose, R. J. Francis, D. Lewis and P) 339.48 559.33 P 2.79 (. Chow) 524.49 559.33 P 2.79 (,) 555.5 559.33 P 4.02 (\322Architecture of Programmable Gate Arrays: The) 339.48 547.33 P 2.92 (Ef) 339.48 535.33 P 2.92 (fect of Logic Block Functionality on Area Ef) 348.73 535.33 P 2.92 (\336-) 549.11 535.33 P 0.26 (ciency) 339.48 523.33 P 0.26 (,\323) 364.92 523.33 P 2 F 0.26 (IEEE Journal of Solid State Cir) 374.61 523.33 P 0.26 (cuits) 502.41 523.33 P 0 F 0.26 (, V) 521.29 523.33 P 0.26 (ol. 26,) 532.47 523.33 P (No. 3, pp. 277-282, March 1991.) 339.48 511.33 T ([5]) 317.88 493.33 T 0.96 (P) 339.48 493.33 P 0.96 (. J. Fleming and J. J. W) 343.93 493.33 P 0.96 (allace, \322How not to lie with) 442.72 493.33 P 2.28 (statistics: the correct way to summarize benchmark) 339.48 481.33 P 0.41 (results,\323) 339.48 469.33 P 2 F 0.41 (Communications of the ACM) 375.42 469.33 P 0 F 0.41 (, V) 492.97 469.33 P 0.41 (ol. 29, No. 3,) 504.3 469.33 P (pp. 218-221, March 1986.) 339.48 457.33 T ([6]) 317.88 439.33 T 0.82 (S. Singh, J. Rose, D. Lewis, K. Chung, and P) 339.48 439.33 P 0.82 (. Chow) 526.46 439.33 P 0.82 (,) 555.5 439.33 P 2.26 (\322The Ef) 339.48 427.33 P 2.26 (fect of Logic Block Architecture on FPGA) 373.47 427.33 P 1.69 (Performance,\323) 339.48 415.33 P 2 F 1.69 (IEEE Journal of Solid State Cir) 401.67 415.33 P 1.69 (cuits) 536.62 415.33 P 0 F 1.69 (,) 555.5 415.33 P (V) 339.48 403.33 T (ol. 27, No. 3, March 1992, pp. 281-287.) 345.41 403.33 T ([7]) 317.88 385.33 T 0.67 (S. D. Brown, R. J. Francis, J. Rose, and Z. G. V) 339.48 385.33 P 0.67 (rane-) 537.47 385.33 P 0.16 (sic,) 339.48 373.33 P 1 F 0.16 (Field-Pr) 355.74 373.33 P 0.16 (ogrammable Gate Arrays) 391.1 373.33 P 0 F 0.16 (, Kluwer Aca-) 500.78 373.33 P (demic Publishers 1992, pp. 93-96.) 339.48 361.33 T ([8]) 317.88 343.33 T 0.96 (D. Hill and N-S W) 339.48 343.33 P 0.96 (oo, \322The Bene\336ts of Flexibility in) 417.73 343.33 P 0.15 (Look-up T) 339.48 331.33 P 0.15 (able FPGAs,\323 in) 381.96 331.33 P 1 F 0.15 (FPGAs) 450.7 331.33 P 0 F 0.15 (, W) 481.8 331.33 P 0.15 (. Moore and W) 495.46 331.33 P 0.15 (.) 555.5 331.33 P (Luk Eds., Abingdon 1991, pp. 127-136.) 339.48 319.33 T ([9]) 317.88 301.33 T 1.2 (J. He, J. Rose, \322Advantages of Heterogeneous Logic) 339.48 301.33 P 1.62 (Block Architectures for FPGAs,\323) 339.48 289.33 P 2 F 1.62 (Custom Integrated) 481.7 289.33 P (Cir) 339.48 277.33 T (cuits Confer) 352.44 277.33 T (ence 1993) 401.22 277.33 T 0 F (, pp. 7.4.1-7.4.5, May 1993.) 442.01 277.33 T ([10]) 317.88 259.33 T 0.35 (J. He, \322T) 339.48 259.33 P 0.35 (echnology Mapping and Architecture of Het-) 375.56 259.33 P 9.93 (erogeneous Field-Programmable Gate Arrays,\323) 339.48 247.33 P 2 F (M.A.Sc. Thesis) 339.48 235.33 T 0 F (, University of T) 398.89 235.33 T (oronto, 1994.) 464.81 235.33 T FMENDPAGE %%EndPage: "7" 8 %%Trailer %%BoundingBox: 0 0 612 792 %%Pages: 7 1 %%DocumentFonts: Times-Roman %%+ Times-Bold %%+ Times-Italic %%+ Symbol