%!PS-Adobe-3.0 %%BoundingBox: (atend) %%Pages: (atend) %%PageOrder: (atend) %%DocumentFonts: (atend) %%Creator: Frame 5.1 %%DocumentData: Clean7Bit %%EndComments %%BeginProlog %- %- Frame ps_prolog 5.0, for use with Frame 5.0 products %- This ps_prolog file is Copyright (c) 1986-1996 Adobe Systems, Incoporated. %- All rights reserved. This ps_prolog file may be freely copied and %- distributed in conjunction with documents created using FrameMaker, %- FrameMaker/SGML FrameReader and FrameViewer as long as this %- copyright notice is preserved. %- %- FrameMaker users specify the proper paper size for each print job in the %- "Print" dialog's "Printer Paper Size" "Width" and "Height~ fields. If the %- printer that the PS file is sent to does not support the requested paper %- size, or if there is no paper tray of the proper size currently installed, %- then the job will not be printed. The following flag, if set to true, will %- cause the job to print on the default paper in such cases. /FMAllowPaperSizeMismatch false def %- %- Frame products normally print colors as their true color on a color printer %- or as shades of gray, based on luminance, on a black-and white printer. The %- following flag, if set to true, forces all non-white colors to print as pure %- black. This has no effect on bitmap images. /FMPrintAllColorsAsBlack false def %- %- Frame products can either set their own line screens or use a printer's %- default settings. Three flags below control this separately for no %- separations, spot separations and process separations. If a flag %- is true, then the default printer settings will not be changed. If it is %- false, Frame products will use their own settings from a table based on %- the printer's resolution. /FMUseDefaultNoSeparationScreen true def /FMUseDefaultSpotSeparationScreen true def /FMUseDefaultProcessSeparationScreen false def %- %- For any given PostScript printer resolution, Frame products have two sets of %- screen angles and frequencies for printing process separations, which are %- recomended by Adobe. The following variable chooses the higher frequencies %- when set to true or the lower frequencies when set to false. This is only %- effective if the appropriate FMUseDefault...SeparationScreen flag is false. /FMUseHighFrequencyScreens true def %- %- The following is a set of predefined optimal frequencies and angles for various %- common dpi settings. This is taken from "Advances in Color Separation Using %- PostScript Software Technology," from Adobe Systems (3/13/89 P.N. LPS 0043) %- and corrolated with information which is in various PPD (4.0) files. %- %- The "dpiranges" figure is the minimum dots per inch device resolution which %- can support this setting. The "low" and "high" values are controlled by the %- setting of the FMUseHighFrequencyScreens flag above. The "TDot" flags control %- the use of the "Yellow Triple Dot" feature whereby the frequency id divided by %- three, but the dot function is "trippled" giving a block of 3x3 dots per cell. %- %- PatFreq is a compromise pattern frequency for ps Level 2 printers which is close %- to the ideal WYSIWYG pattern frequency of 9 repetitions/inch but does not beat %- (too badly) against the screen frequencies of any separations for that DPI. % This is computed by taking dpi/9 as the ideal pixels per repetition, and then % computing a tiling size in printer pixels for each of the four separations as % (dpi/screenFreq)*(cos(screenAngle)+sin(screenAngle)) Actually, this is the same % for Cyan and Magenta). Then, we take a "nice" LCM of the tile sizes close to % the desired pattern tile where the beat factor is not more than 2 or 3. % /dpiranges [ 2540 2400 1693 1270 1200 635 600 0 ] def /CMLowFreqs [ 100.402 94.8683 89.2289 100.402 94.8683 66.9349 63.2456 47.4342 ] def /YLowFreqs [ 95.25 90.0 84.65 95.25 90.0 70.5556 66.6667 50.0 ] def /KLowFreqs [ 89.8026 84.8528 79.8088 89.8026 84.8528 74.8355 70.7107 53.033 ] def /CLowAngles [ 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 ] def /MLowAngles [ 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 ] def /YLowTDot [ true true false true true false false false ] def /CMHighFreqs [ 133.87 126.491 133.843 108.503 102.523 100.402 94.8683 63.2456 ] def /YHighFreqs [ 127.0 120.0 126.975 115.455 109.091 95.25 90.0 60.0 ] def /KHighFreqs [ 119.737 113.137 119.713 128.289 121.218 89.8026 84.8528 63.6395 ] def /CHighAngles [ 71.5651 71.5651 71.5651 70.0169 70.0169 71.5651 71.5651 71.5651 ] def /MHighAngles [ 18.4349 18.4349 18.4349 19.9831 19.9831 18.4349 18.4349 18.4349 ] def /YHighTDot [ false false true false false true true false ] def /PatFreq [ 10.5833 10.0 9.4055 10.5833 10.0 10.5833 10.0 9.375 ] def %- %- PostScript Level 2 printers contain an "Accurate Screens" feature which can %- improve process separation rendering at the expense of compute time. This %- flag is ignored by PostScript Level 1 printers. /FMUseAcccurateScreens true def %- %- The following PostScript procedure defines the spot function that Frame %- products will use for process separations. You may un-comment-out one of %- the alternative functions below, or use your own. %- %- Dot function /FMSpotFunction {abs exch abs 2 copy add 1 gt {1 sub dup mul exch 1 sub dup mul add 1 sub } {dup mul exch dup mul add 1 exch sub }ifelse } def %- %- Line function %- /FMSpotFunction { pop } def %- %- Elipse function %- /FMSpotFunction { dup 5 mul 8 div mul exch dup mul exch add %- sqrt 1 exch sub } def %- %- /FMversion (5.0) def % matches PS_VERSION in fmprintdriver % PostScript Level 1 = true, 2 = false /fMLevel1 /languagelevel where {pop languagelevel} {1} ifelse 2 lt def % Set up Color vs. Black-and-White /FMPColor fMLevel1 { false /colorimage where {pop pop true} if } { % statusdict /processcolors known { % statusdict /processcolors get exec % } {1} ifelse % 1 gt true } ifelse def /FrameDict 400 dict def % should check this value each time changes made % % For NeWS we add a fake errordict, so we can psh files % systemdict /errordict known not {/errordict 10 dict def errordict /rangecheck {stop} put} if %- The readline in PS 23.0 doesn't recognize cr's as nl's on AppleTalk FrameDict /tmprangecheck errordict /rangecheck get put % save old rangecheck errordict /rangecheck {FrameDict /bug true put} put % will flag bug found FrameDict /bug false put % flag bug not found mark % since we're not sure what will happen next %- Some PS machines read past the CR, so keep the following 3 lines together! currentfile 5 string readline 00 0000000000 cleartomark % junk from readline and rangecheck errordict /rangecheck FrameDict /tmprangecheck get put % restore rangecheck FrameDict /bug get { % redefine readline if last one got a rangecheck /readline { /gstring exch def /gfile exch def /gindex 0 def { gfile read pop % get a char dup 10 eq {exit} if % exit if LF dup 13 eq {exit} if % exit if CR gstring exch gindex exch put % store it away /gindex gindex 1 add def % bump index } loop pop % eol character gstring 0 gindex getinterval true % simulate real readline } bind def } if % outer-world defs /FMshowpage /showpage load def /FMquit /quit load def /FMFAILURE { % enter with two error strings on the stack dup = flush % send a copy of the message to the console FMshowpage % msg on a page by itself, so it can't be, say, black on black /Helvetica findfont 12 scalefont setfont 72 200 moveto show 72 220 moveto show FMshowpage % we might be in the middle of some EPS, where "showpage" FMquit % and "quit" are redefined } def % only used once at most, so no bind /FMVERSION { FMversion ne { (Adobe Frame product version does not match ps_prolog! Check installation;) (also check ~/fminit and ./fminit for old versions) FMFAILURE } if } def % only used at startup, so no bind /FMBADEPSF { % Call with bad operator name on stack (as a string) (Adobe's PostScript Language Reference Manual, 2nd Edition, section H.2.4) (says your EPS file is not valid, as it calls X ) dup dup (X) search pop exch pop exch pop length % parmstr errstr errstr indx 5 -1 roll % errstr errstr index parmstr putinterval % errstr FMFAILURE } def % standard concatprocs routine /fmConcatProcs { /proc2 exch cvlit def/proc1 exch cvlit def/newproc proc1 length proc2 length add array def newproc 0 proc1 putinterval newproc proc1 length proc2 putinterval newproc cvx }def % Put all local variables here in alphabetical order. FrameDict begin [ /ALDsave /FMdicttop /FMoptop /FMpointsize /FMsaveobject /b /bitmapsave /blut /bpside /bs /bstring /bwidth /c /cf /cs /cynu /depth /edown /fh /fillvals /fw /fx /fy /g /gfile /gindex /grnt /gryt /gstring /height /hh /i /im /indx /is /k /kk /landscape /lb /len /llx /lly /m /magu /manualfeed /n /offbits /onbits /organgle /orgbangle /orgbfreq /orgbproc /orgbxfer /orgfreq /orggangle /orggfreq /orggproc /orggxfer /orgmatrix /orgproc /orgrangle /orgrfreq /orgrproc /orgrxfer /orgxfer /pagesave /paperheight /papersizedict /paperwidth /pos /pwid /r /rad /redt /sl /str /tran /u /urx /ury /val /width /width /ws /ww /x /x1 /x2 /xindex /xpoint /xscale /xx /y /y1 /y2 /yelu /yindex /ypoint /yscale /yy ] { 0 def } forall % Start of PDF/Acrobat support % Bind def /FmBD {bind def} bind def systemdict /pdfmark known { /fMAcrobat true def % FmPD is a conditional PDFMark /FmPD /pdfmark load def % FmPT is a show text operator which only show up when distiller is active /FmPT /show load def % FmPD2 and FmPA are Acrobat 2.0-specific currentdistillerparams /CoreDistVersion get 2000 ge { % FmPD2 is like FmPD but for Acrobat 2.0-specific PDF /FmPD2 /pdfmark load def % x y/name FmPA % is equivalent to % [/Dest/name/View[/FitH x y FmDC exch pop]/DEST FmPD % It is a shortcut for pagragraph Uinique ID designators whic occurr commonly. /FmPA { mark exch /Dest exch 5 3 roll /View [ /XYZ null 6 -2 roll FmDC exch pop null] /DEST FmPD }FmBD } { % These are No-Ops for Distiller 1.0 /FmPD2 /cleartomark load def /FmPA {pop pop pop}FmBD } ifelse } { % these are the No-Ops for regular PostScript /fMAcrobat false def /FmPD /cleartomark load def /FmPD2 /cleartomark load def /FmPT /pop load def /FmPA {pop pop pop}FmBD } ifelse % This convert a set of X Y coordinates from the current user space to the default % PostScript coordinates needed by some pdfmark variants. We also convert to % integer because the distiller doesn't always like floats! /FmDC { transform fMDefaultMatrix itransform cvi exch cvi exch }FmBD % This converts four numbers into a bounding box making sure the first two are maller than the last two /FmBx { dup 3 index lt {3 1 roll exch} if 1 index 4 index lt {4 -1 roll 3 1 roll exch 4 1 roll} if }FmBD % End of PDF/Acrobat support % % Color separation code % % Constants. /FMnone 0 def /FMcyan 1 def /FMmagenta 2 def /FMyellow 3 def /FMblack 4 def /FMcustom 5 def /fMNegative false def % we are inverting the page % Variables. /FrameSepIs FMnone def % separation we are printing % If FrameSepIs is FMcustom, this is the custom color /FrameSepBlack 0 def /FrameSepYellow 0 def /FrameSepMagenta 0 def /FrameSepCyan 0 def /FrameSepRed 1 def /FrameSepGreen 1 def /FrameSepBlue 1 def /FrameCurGray 1 def /FrameCurPat null def /FrameCurColors [ 0 0 0 1 0 0 0 ] def % c m y k r g b % Utility routines /FrameColorEpsilon .001 def % epsilon by which values can differ and sill be equal /eqepsilon { % v1 v2 eqeps bool sub dup 0 lt {neg} if FrameColorEpsilon le } bind def % are the cmyk and cmykrgb arrays on the stack the same color? /FrameCmpColorsCMYK { % [ c1 m1 y1 k1 ] [ c2 m2 y2 k2 r2 g2 b2] -> bool 2 copy 0 get exch 0 get eqepsilon { 2 copy 1 get exch 1 get eqepsilon { 2 copy 2 get exch 2 get eqepsilon { 3 get exch 3 get eqepsilon } {pop pop false} ifelse }{pop pop false} ifelse } {pop pop false} ifelse } bind def % are the rgb and cmykrgb arrays on the stack the same color? /FrameCmpColorsRGB { % [ r1 g1 b1 ] [ c2 m2 y2 k2 r2 g2 b2] -> bool 2 copy 4 get exch 0 get eqepsilon { 2 copy 5 get exch 1 get eqepsilon { 6 get exch 2 get eqepsilon }{pop pop false} ifelse } {pop pop false} ifelse } bind def % convert r g b to c m y k /RGBtoCMYK { % r g b 1 exch sub % r g y 3 1 roll % y r g 1 exch sub % y r m 3 1 roll % m y r 1 exch sub % m y c 3 1 roll % c m y 3 copy % c m y c m y 2 copy % c m y c m y m y le { pop } { exch pop } ifelse % c m y c min(m,y) 2 copy % c m y c min(m,y) c min(m,y) le { pop } { exch pop } ifelse % c m y min(c, min(m,y)) dup dup dup % c m y k k k k 6 1 roll % c k m y k k k 4 1 roll % c k m k y k k 7 1 roll % k c k m k y k sub % k c k m k y 6 1 roll % y k c k m k sub % y k c k m 5 1 roll % m y k c k sub % m y k c 4 1 roll % c m y k } bind def /CMYKtoRGB { % c m y k CMYKtoRGB r g b dup dup 4 -1 roll add % c m k k y+k 5 1 roll 3 -1 roll add % y+k c k m+k 4 1 roll add % m+k y+k c+k 1 exch sub dup 0 lt {pop 0} if 3 1 roll % r m+k y+k 1 exch sub dup 0 lt {pop 0} if exch % r b m+k 1 exch sub dup 0 lt {pop 0} if exch % r g b } bind def % Public routines % Happens at the top of each page that is a separation /FrameSepInit { 1.0 RealSetgray } bind def % Tell the separation code that this separation is for a custom color /FrameSetSepColor { % c m y k r g b /FrameSepBlue exch def /FrameSepGreen exch def /FrameSepRed exch def /FrameSepBlack exch def /FrameSepYellow exch def /FrameSepMagenta exch def /FrameSepCyan exch def /FrameSepIs FMcustom def setCurrentScreen } bind def % Tell the separation code that this separation is Cyan /FrameSetCyan { /FrameSepBlue 1.0 def /FrameSepGreen 1.0 def /FrameSepRed 0.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 1.0 def /FrameSepIs FMcyan def setCurrentScreen } bind def % Tell the separation code that this separation is Magenta /FrameSetMagenta { /FrameSepBlue 1.0 def /FrameSepGreen 0.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 1.0 def /FrameSepCyan 0.0 def /FrameSepIs FMmagenta def setCurrentScreen } bind def % Tell the separation code that this separation is Yellow /FrameSetYellow { /FrameSepBlue 0.0 def /FrameSepGreen 1.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 1.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMyellow def setCurrentScreen } bind def % Tell the separation code that this separation is Black /FrameSetBlack { /FrameSepBlue 0.0 def /FrameSepGreen 0.0 def /FrameSepRed 0.0 def /FrameSepBlack 1.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMblack def setCurrentScreen } bind def % Tell the separation code we are not doing a separation /FrameNoSep { % /FrameSepIs FMnone def setCurrentScreen } bind def % Initialize the separation code with all the custom colors we are % separating (not process colors) /FrameSetSepColors { % list of arrays of [c m y k r g b] count FrameDict begin [ exch 1 add 1 roll ] /FrameSepColors % array of arrays of colors we are separating exch def end } bind def % is this color array in the array of custom color separations? /FrameColorInSepListCMYK { % [ c m y k ] -> bool FrameSepColors { % color elem-of-array exch dup 3 -1 roll % color color elem FrameCmpColorsCMYK % color bool { pop true exit } if } forall % exits with either [color] or true dup true ne {pop false} if } bind def /FrameColorInSepListRGB { % [ r g b ] -> bool FrameSepColors { % color elem-of-array exch dup 3 -1 roll % color color elem FrameCmpColorsRGB % color bool { pop true exit } if } forall % exits with either [color] or true dup true ne {pop false} if } bind def % Level 1 color operators saved and redefined /RealSetgray /setgray load def /RealSetrgbcolor /setrgbcolor load def /RealSethsbcolor /sethsbcolor load def end % Setgray patch /setgray { % num FrameDict begin FrameSepIs FMnone eq { RealSetgray } { % go to white unless the current sep color is black FrameSepIs FMblack eq { RealSetgray } { FrameSepIs FMcustom eq FrameSepRed 0 eq and FrameSepGreen 0 eq and FrameSepBlue 0 eq and { RealSetgray } { 1 RealSetgray pop } ifelse } ifelse } ifelse end } bind def /setrgbcolor { % r g b FrameDict begin FrameSepIs FMnone eq { RealSetrgbcolor } { 3 copy [ 4 1 roll ] % r g b [ r g b ] FrameColorInSepListRGB { FrameSepBlue eq exch FrameSepGreen eq and exch FrameSepRed eq and { 0 } { 1 } ifelse } { FMPColor { RealSetrgbcolor currentcmykcolor } { RGBtoCMYK } ifelse FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind def /sethsbcolor { FrameDict begin FrameSepIs FMnone eq { RealSethsbcolor } { RealSethsbcolor % safe since we will overwrite the color state currentrgbcolor % r g b - Let PostsCript to the conversion. setrgbcolor % call our version } ifelse end } bind def FrameDict begin /setcmykcolor where { pop /RealSetcmykcolor /setcmykcolor load def } { /RealSetcmykcolor { 4 1 roll 3 { 3 index add 0 max 1 min 1 exch sub 3 1 roll} repeat RealSetrgbcolor pop } bind def } ifelse userdict /setcmykcolor { % c m y k FrameDict begin FrameSepIs FMnone eq { RealSetcmykcolor } { 4 copy [ 5 1 roll ] FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and { 0 } { 1 } ifelse } { FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind put % Set up a prototype pattern for PostScript Level 2 fMLevel1 { % set up screen functions for the patterns in PS level 1 % each entry contains an angle, spot function, flipped spot function, % gray level and frequency multiplier. /patScreenDict 7 dict dup begin <0f1e3c78f0e1c387> [ 45 { pop } {exch pop} .5 2 sqrt] FmBD <0f87c3e1f0783c1e> [ 135 { pop } {exch pop} .5 2 sqrt] FmBD [ 0 { pop } dup .5 2 ] FmBD [ 90 { pop } dup .5 2 ] FmBD <8142241818244281> [ 45 { 2 copy lt {exch} if pop} dup .75 2 sqrt] FmBD <03060c183060c081> [ 45 { pop } {exch pop} .875 2 sqrt] FmBD <8040201008040201> [ 135 { pop } {exch pop} .875 2 sqrt] FmBD end def } { % prototype level 2 pattern dictionary % define some PostScript procedures for known jaggy patterns. /patProcDict 5 dict dup begin <0f1e3c78f0e1c387> { 3 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <0f87c3e1f0783c1e> { 3 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def <8142241818244281> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -1 -1 moveto 9 9 lineto stroke } bind def <03060c183060c081> { 1 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <8040201008040201> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def end def /patDict 15 dict dup begin /PatternType 1 def % Always 1 for PS Level 2 /PaintType 2 def % Uncolored pattern /TilingType 3 def % constant spacing and faster tiling /BBox [ 0 0 8 8 ] def % bounding box /XStep 8 def % X offset /YStep 8 def % Y offset /PaintProc { begin patProcDict bstring known { patProcDict bstring get exec } { 8 8 true [1 0 0 -1 0 8] bstring imagemask } ifelse end } bind def end def } ifelse %combineColor puts together the current gray value (which could also be %a fraction of on bits for a fill pattern and the current color and calls %the appropriate function % /combineColor { FrameSepIs FMnone eq { graymode fMLevel1 or not { % Level 2 pattern [/Pattern [/DeviceCMYK]] setcolorspace FrameCurColors 0 4 getinterval aload pop FrameCurPat setcolor } { FrameCurColors 3 get 1.0 ge { FrameCurGray RealSetgray } { fMAcrobat not FMPColor graymode and and { 0 1 3 { FrameCurColors exch get 1 FrameCurGray sub mul } for RealSetcmykcolor } { 4 1 6 { FrameCurColors exch get graymode { 1 exch sub 1 FrameCurGray sub mul 1 exch sub } { 1.0 lt {FrameCurGray} {1} ifelse } ifelse } for RealSetrgbcolor } ifelse } ifelse } ifelse } { % separation case FrameCurColors 0 4 getinterval aload FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and FrameSepIs FMcustom eq and { FrameCurGray } { 1 } ifelse } { FrameSepIs FMblack eq {FrameCurGray 1.0 exch sub mul 1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop FrameCurGray 1.0 exch sub mul 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse graymode fMLevel1 or not { % Level 2 pattern [/Pattern [/DeviceGray]] setcolorspace FrameCurPat setcolor } { graymode not fMLevel1 and { % Level 1 patterns are either all there or not there at all dup 1 lt {pop FrameCurGray} if } if RealSetgray } ifelse } ifelse } bind def /savematrix { orgmatrix currentmatrix pop } bind def /restorematrix { orgmatrix setmatrix } bind def /fMDefaultMatrix matrix defaultmatrix def /fMatrix2 matrix def /dpi 72 0 fMDefaultMatrix dtransform dup mul exch dup mul add sqrt def % freq and sangle are used for ps Level 1 pattern building. /freq dpi dup 72 div round dup 0 eq {pop 1} if 8 mul div def /sangle 1 0 fMDefaultMatrix dtransform exch atan def sangle fMatrix2 rotate fMDefaultMatrix fMatrix2 concatmatrix dup 0 get /sflipx exch def 3 get /sflipy exch def % % screen index depending on dpi % - screenIndex smallint /screenIndex { 0 1 dpiranges length 1 sub { dup dpiranges exch get 1 sub dpi le {exit} {pop} ifelse } for } bind def % % These routines get the standard Adobe frequencies, angles, and spot functions % depending on the DPI % % - getCyanScreen freq angle spotfunction /getCyanScreen { FMUseHighFrequencyScreens { CHighAngles CMHighFreqs} {CLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def % % - getMagentaScreen freq angle spotFunction /getMagentaScreen { FMUseHighFrequencyScreens { MHighAngles CMHighFreqs } {MLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def % % - getYellowScreen freq angle spotFunction % note that some of these use a "tripple dot" function at 1/3 the frequency /getYellowScreen { FMUseHighFrequencyScreens { YHighTDot YHighFreqs} { YLowTDot YLowFreqs } ifelse screenIndex dup 3 1 roll get 3 1 roll get { 3 div {2 { 1 add 2 div 3 mul dup floor sub 2 mul 1 sub exch} repeat FMSpotFunction } } {/FMSpotFunction load } ifelse 0.0 exch } bind def % % - getBlackScreen freq angle spotFunction /getBlackScreen { FMUseHighFrequencyScreens { KHighFreqs } { KLowFreqs } ifelse screenIndex get 45.0 /FMSpotFunction load } bind def % % - getSpotScreen freq angle spotFunction /getSpotScreen { getBlackScreen } bind def % % - getCompositeScreen freq angle spotFunction /getCompositeScreen { getBlackScreen } bind def % FmSetScreen sets the screen for either PostScript Level 1 or Level 2 and optionally % sets the accuratescreens flag in the latter case % freq angle spotfunction FMSetScreen - /FMSetScreen fMLevel1 { /setscreen load }{ { 8 dict begin /HalftoneType 1 def /SpotFunction exch def /Angle exch def /Frequency exch def /AccurateScreens FMUseAcccurateScreens def currentdict end sethalftone } bind } ifelse def % This sets the default screen as was set at the beginning of the job % - setDefaultScreen - /setDefaultScreen { FMPColor { orgrxfer cvx orggxfer cvx orgbxfer cvx orgxfer cvx setcolortransfer } { orgxfer cvx settransfer } ifelse orgfreq organgle orgproc cvx setscreen } bind def % This sets the current screen depending on FrameSepIs % - setCurrentScreen - /setCurrentScreen { FrameSepIs FMnone eq { FMUseDefaultNoSeparationScreen { setDefaultScreen } { getCompositeScreen FMSetScreen } ifelse } { FrameSepIs FMcustom eq { FMUseDefaultSpotSeparationScreen { setDefaultScreen } { getSpotScreen FMSetScreen } ifelse } { FMUseDefaultProcessSeparationScreen { setDefaultScreen } { FrameSepIs FMcyan eq { getCyanScreen FMSetScreen } { FrameSepIs FMmagenta eq { getMagentaScreen FMSetScreen } { FrameSepIs FMyellow eq { getYellowScreen FMSetScreen } { getBlackScreen FMSetScreen } ifelse } ifelse } ifelse } ifelse } ifelse } ifelse } bind def end % End of Color separation code % /FMDOCUMENT { % xscale yscale edown negative paperwidth paperheight manfeed numcopies numfonts array /FMfonts exch def % Why isn't this in FrameDict??? /#copies exch def FrameDict begin 0 ne /manualfeed exch def /paperheight exch def /paperwidth exch def 0 ne /fMNegative exch def % invert page 0 ne /edown exch def % flip page along y axis /yscale exch def /xscale exch def fMLevel1 { manualfeed {setmanualfeed} if /FMdicttop countdictstack 1 add def % some PS's leave junk on dict ... /FMoptop count def % ...or on operand stack... setpapername % This stuff may alter the transfer/screen/angle manualfeed {true} {papersize} ifelse % true->more work to do {manualpapersize} {false} ifelse % true->more work to do {desperatepapersize} {false} ifelse % true->failed completely {papersizefailure} if count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for %...if tray not installed } {2 dict dup /PageSize [paperwidth paperheight] put manualfeed {dup /ManualFeed manualfeed put} if {setpagedevice} stopped {papersizefailure} if } ifelse % fMLevel1 FMPColor { currentcolorscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def cvlit /orgbproc exch def /orgbangle exch def /orgbfreq exch def cvlit /orggproc exch def /orggangle exch def /orggfreq exch def cvlit /orgrproc exch def /orgrangle exch def /orgrfreq exch def currentcolortransfer fMNegative { 1 1 4 { pop { 1 exch sub } fmConcatProcs 4 1 roll } for 4 copy setcolortransfer } if cvlit /orgxfer exch def cvlit /orgbxfer exch def cvlit /orggxfer exch def cvlit /orgrxfer exch def } { currentscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def currenttransfer fMNegative { { 1 exch sub } fmConcatProcs dup settransfer } if cvlit /orgxfer exch def } ifelse end % FrameDict } def % only used at startup, so no bind /FMBEGINPAGE { % pagewidth pageheight landscape color-arrays count FrameDict begin % for the whole page... /pagesave save def 3.86 setmiterlimit /landscape exch 0 ne def landscape { % check for landscape 90 rotate 0 exch dup /pwid exch def neg translate pop }{ pop /pwid exch def } ifelse edown { [-1 0 0 1 pwid 0] concat } if % paint the whole page in "white". If the page is inverted, then % this will actually paint our black background 0 0 moveto paperwidth 0 lineto paperwidth paperheight lineto 0 paperheight lineto 0 0 lineto 1 setgray fill xscale yscale scale /orgmatrix matrix def gsave % for CLIP } def % only used infrequently, so no bind /FMENDPAGE { grestore % for CLIP pagesave restore end % FrameDict showpage } def % only used infrequently, so no bind /FMFONTDEFINE { % fontindex nonstd_encoding fontname -- FrameDict begin findfont % fontindex nonstd_encoding font ReEncode % fontindex font' 1 index exch % fontindex fontindex font' definefont % fontindex font" FMfonts 3 1 roll % FMfonts fontindex font" put end % FrameDict } def % only used infrequently, so no bind /FMFILLS { FrameDict begin dup array /fillvals exch def dict /patCache exch def end % framedict } def % Only called once, so no bind /FMFILL { FrameDict begin fillvals 3 1 roll put end % FrameDict } def % only used infrequently, so no bind % Set things to a known, quiescent state, for when we switch to another writer /FMNORMALIZEGRAPHICS { newpath 1 setlinewidth 0 setlinecap 0 0 0 sethsbcolor 0 setgray % Not FMsetgray; only called outside of our environment! } bind def /FMBEGINEPSF { % llx lly urx ury fw fh fx fy end % FrameDict /FMEPSF save def % in userdict /showpage {} def % this def is in userdict %- See Adobe's "PostScript Language Reference Manual, 2nd Edition", page 714. %- "...the following operators MUST NOT be used in an EPS file:" (emphasis ours) /banddevice {(banddevice) FMBADEPSF} def /clear {(clear) FMBADEPSF} def /cleardictstack {(cleardictstack) FMBADEPSF} def % FMBADEPSF knows this is the longest! /copypage {(copypage) FMBADEPSF} def /erasepage {(erasepage) FMBADEPSF} def /exitserver {(exitserver) FMBADEPSF} def /framedevice {(framedevice) FMBADEPSF} def /grestoreall {(grestoreall) FMBADEPSF} def /initclip {(initclip) FMBADEPSF} def /initgraphics {(initgraphics) FMBADEPSF} def % /initmatrix {(initmatrix) FMBADEPSF} def % Aldus Freehand 4.0 epsf uses this harmlessly /quit {(quit) FMBADEPSF} def /renderbands {(renderbands) FMBADEPSF} def /setglobal {(setglobal) FMBADEPSF} def /setpagedevice {(setpagedevice) FMBADEPSF} def /setshared {(setshared) FMBADEPSF} def /startjob {(startjob) FMBADEPSF} def /lettertray {(lettertray) FMBADEPSF} def /letter {(letter) FMBADEPSF} def /lettersmall {(lettersmall) FMBADEPSF} def /11x17tray {(11x17tray) FMBADEPSF} def /11x17 {(11x17) FMBADEPSF} def /ledgertray {(ledgertray) FMBADEPSF} def /ledger {(ledger) FMBADEPSF} def /legaltray {(legaltray) FMBADEPSF} def /legal {(legal) FMBADEPSF} def /statementtray {(statementtray) FMBADEPSF} def /statement {(statement) FMBADEPSF} def /executivetray {(executivetray) FMBADEPSF} def /executive {(executive) FMBADEPSF} def /a3tray {(a3tray) FMBADEPSF} def /a3 {(a3) FMBADEPSF} def /a4tray {(a4tray) FMBADEPSF} def /a4 {(a4) FMBADEPSF} def /a4small {(a4small) FMBADEPSF} def /b4tray {(b4tray) FMBADEPSF} def /b4 {(b4) FMBADEPSF} def /b5tray {(b5tray) FMBADEPSF} def /b5 {(b5) FMBADEPSF} def FMNORMALIZEGRAPHICS % in case we're in a strange state [/fy /fx /fh /fw /ury /urx /lly /llx] {exch def} forall % neat trick fx fw 2 div add fy fh 2 div add translate rotate fw 2 div neg fh 2 div neg translate fw urx llx sub div fh ury lly sub div scale % then scale llx neg lly neg translate % then compensate for LL offset /FMdicttop countdictstack 1 add def % high-water mark of dict stack /FMoptop count def % tricky! "/FMoptop" on stack } bind def /FMENDEPSF { count -1 FMoptop {pop pop} for % clear EPS junk from operand stack countdictstack -1 FMdicttop {pop end} for % ditto for dict stack FMEPSF restore FrameDict begin % for the whole page... } bind def FrameDict begin % put most defs here /setmanualfeed { %%BeginFeature *ManualFeed True statusdict /manualfeed true put %%EndFeature } bind def /max {2 copy lt {exch} if pop} bind def /min {2 copy gt {exch} if pop} bind def /inch {72 mul} def /pagedimen { % name width height paperheight sub abs 16 lt exch % 16pt is an arbitrary slop amount paperwidth sub abs 16 lt and {/papername exch def} {pop} ifelse } bind def /setpapername { % Already set up: paperwidth paperheight and manualfeed /papersizedict 14 dict def % one for /papername, one for /unknown papersizedict begin /papername /unknown def % in case no match /Letter 8.5 inch 11.0 inch pagedimen /LetterSmall 7.68 inch 10.16 inch pagedimen /Tabloid 11.0 inch 17.0 inch pagedimen /Ledger 17.0 inch 11.0 inch pagedimen /Legal 8.5 inch 14.0 inch pagedimen /Statement 5.5 inch 8.5 inch pagedimen /Executive 7.5 inch 10.0 inch pagedimen /A3 11.69 inch 16.5 inch pagedimen /A4 8.26 inch 11.69 inch pagedimen /A4Small 7.47 inch 10.85 inch pagedimen /B4 10.125 inch 14.33 inch pagedimen /B5 7.16 inch 10.125 inch pagedimen end } bind def /papersize { papersizedict begin /Letter {lettertray letter} def /LetterSmall {lettertray lettersmall} def /Tabloid {11x17tray 11x17} def /Ledger {ledgertray ledger} def /Legal {legaltray legal} def /Statement {statementtray statement} def /Executive {executivetray executive} def /A3 {a3tray a3} def /A4 {a4tray a4} def /A4Small {a4tray a4small} def /B4 {b4tray b4} def /B5 {b5tray b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end statusdict begin stopped end % return true if more work to do } bind def /manualpapersize { papersizedict begin /Letter {letter} def /LetterSmall {lettersmall} def /Tabloid {11x17} def /Ledger {ledger} def /Legal {legal} def /Statement {statement} def /Executive {executive} def /A3 {a3} def /A4 {a4} def /A4Small {a4small} def /B4 {b4} def /B5 {b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end stopped % return true if more work to do } bind def /desperatepapersize { statusdict /setpageparams known { paperwidth paperheight 0 1 statusdict begin {setpageparams} stopped % return true iff failed end } {true} ifelse % return true iff failed } bind def /papersizefailure { FMAllowPaperSizeMismatch not { (The requested paper size is not available in any currently-installed tray) (Edit the PS file to "FMAllowPaperSizeMismatch true" to use default tray) FMFAILURE } if } def % % Font re-encoding to include diacritics % /DiacriticEncoding [ /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /space /exclam /quotedbl /numbersign /dollar /percent /ampersand /quotesingle /parenleft /parenright /asterisk /plus /comma /hyphen /period /slash /zero /one /two /three /four /five /six /seven /eight /nine /colon /semicolon /less /equal /greater /question /at /A /B /C /D /E /F /G /H /I /J /K /L /M /N /O /P /Q /R /S /T /U /V /W /X /Y /Z /bracketleft /backslash /bracketright /asciicircum /underscore /grave /a /b /c /d /e /f /g /h /i /j /k /l /m /n /o /p /q /r /s /t /u /v /w /x /y /z /braceleft /bar /braceright /asciitilde /.notdef /Adieresis /Aring /Ccedilla /Eacute /Ntilde /Odieresis /Udieresis /aacute /agrave /acircumflex /adieresis /atilde /aring /ccedilla /eacute /egrave /ecircumflex /edieresis /iacute /igrave /icircumflex /idieresis /ntilde /oacute /ograve /ocircumflex /odieresis /otilde /uacute /ugrave /ucircumflex /udieresis /dagger /.notdef /cent /sterling /section /bullet /paragraph /germandbls /registered /copyright /trademark /acute /dieresis /.notdef /AE /Oslash /.notdef /.notdef /.notdef /.notdef /yen /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /ordfeminine /ordmasculine /.notdef /ae /oslash /questiondown /exclamdown /logicalnot /.notdef /florin /.notdef /.notdef /guillemotleft /guillemotright /ellipsis /.notdef /Agrave /Atilde /Otilde /OE /oe /endash /emdash /quotedblleft /quotedblright /quoteleft /quoteright /.notdef /.notdef /ydieresis /Ydieresis /fraction /currency /guilsinglleft /guilsinglright /fi /fl /daggerdbl /periodcentered /quotesinglbase /quotedblbase /perthousand /Acircumflex /Ecircumflex /Aacute /Edieresis /Egrave /Iacute /Icircumflex /Idieresis /Igrave /Oacute /Ocircumflex /.notdef /Ograve /Uacute /Ucircumflex /Ugrave /dotlessi /circumflex /tilde /macron /breve /dotaccent /ring /cedilla /hungarumlaut /ogonek /caron ] def /ReEncode { % nonstd_encoding font -- reencodedfont dup % nonstd_encoding font font length % nonstd_encoding font dictlength dict begin % nonstd_encoding font % currentdict = newdict {% forall % forall is over font to be copied 1 index /FID ne % skip FID {def} % defs go into newfontdict which is currentdict {pop pop} ifelse % copy all keys including /Encoding } forall % nonstd_encoding 0 eq {/Encoding DiacriticEncoding def} if % -- currentdict % push a copy of the copied font dict onto operand stack end % font' % before popping it off dictionary stack } bind def FMPColor % setup procs for color printing { /BEGINBITMAPCOLOR { % iw, ih, width, height, theta, x y BITMAPCOLOR} def /BEGINBITMAPCOLORc { % iw, ih, width, height, theta, x y BITMAPCOLORc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUECOLOR } def /BEGINBITMAPTRUECOLORc { BITMAPTRUECOLORc } def /BEGINBITMAPCMYK { BITMAPCMYK } def /BEGINBITMAPCMYKc { BITMAPCMYKc } def } % setup procs for B&W printing { /BEGINBITMAPCOLOR { % iw, ih, width, height, theta, x y BITMAPGRAY} def /BEGINBITMAPCOLORc { % iw, ih, width, height, theta, x y BITMAPGRAYc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUEGRAY } def /BEGINBITMAPTRUECOLORc { BITMAPTRUEGRAYc } def /BEGINBITMAPCMYK { BITMAPCMYKGRAY } def /BEGINBITMAPCMYKc { BITMAPCMYKGRAYc } def } ifelse /K { % c m y k r g b SEPARATION FMPrintAllColorsAsBlack { dup 1 eq 2 index 1 eq and 3 index 1 eq and not {7 {pop} repeat 0 0 0 1 0 0 0} if } if FrameCurColors astore pop combineColor } bind def % % graymode is true if we are just doing gray fills, this way do not keep calling % setscreen. I don't know what the cost is on calling setscreen with defaults, but % this is easy to keep track of, and we know for sure we aren't wasting cycles. % if graymode is false and fMLevel1 is false, then we are using Level 2 patterns. % /graymode true def % used by level 1 patterns % defaultflip matrixentry fmGetFlit -> eith -1 or 1 fMLevel1 { /fmGetFlip { fMatrix2 exch get mul 0 lt { -1 } { 1 } ifelse } FmBD } if /setPatternMode { fMLevel1 { 2 index patScreenDict exch known { pop pop patScreenDict exch get aload pop % angle spot fspot gray mult freq % freq mul % times multiplier 5 2 roll % angle spot fspot gray mult freq -> gray freq angle spot fspot fMatrix2 currentmatrix 1 get 0 ne { 3 -1 roll 90 add 3 1 roll % landscape sflipx 1 fmGetFlip sflipy 2 fmGetFlip neg mul } { % portrait sflipx 0 fmGetFlip sflipy 3 fmGetFlip mul } ifelse 0 lt {exch pop} {pop} ifelse % take regular or flipped spot function fMNegative { {neg} fmConcatProcs % invert spot function } if bind % we need to bypass any screen filter and go directly to systemdict % to avoid problems with Kodak Precision calibration software % systemdict /setscreen get exec % leave graylevel on stack /FrameCurGray exch def } { /bwidth exch def /bpside exch def /bstring exch def /onbits 0 def /offbits 0 def freq sangle landscape {90 add} if {/ypoint exch def /xpoint exch def /xindex xpoint 1 add 2 div bpside mul cvi def /yindex ypoint 1 add 2 div bpside mul cvi def bstring yindex bwidth mul xindex 8 idiv add get 1 7 xindex 8 mod sub bitshift and 0 ne fMNegative {not} if {/onbits onbits 1 add def 1} {/offbits offbits 1 add def 0} ifelse } setscreen offbits offbits onbits add div fMNegative {1.0 exch sub} if /FrameCurGray exch def } ifelse } { % Level 2 version pop pop dup patCache exch known { patCache exch get } { % not in cache dup patDict /bstring 3 -1 roll put patDict 9 PatFreq screenIndex get div dup matrix scale % 9 orgfreq % organgle sin abs organgle cos abs add div % dup 16 div round dup 0 le {pop 1} if % Unix pattern size % dup 9 div round dup 0 le {pop 1} if % Mac larger (WYSIWYG) size % div div dup matrix scale % This gives Unix pattern size. makepattern dup patCache 4 -1 roll 3 -1 roll put } ifelse /FrameCurGray 0 def /FrameCurPat exch def } ifelse /graymode false def combineColor } bind def /setGrayScaleMode { graymode not { /graymode true def fMLevel1 { setCurrentScreen } if } if /FrameCurGray exch def combineColor } bind def /normalize { transform round exch round exch itransform } bind def /dnormalize { dtransform round exch round exch idtransform } bind def /lnormalize { % line widths are always odd so that arrow heads work 0 dtransform exch cvi 2 idiv 2 mul 1 add exch idtransform pop } bind def /H { % THICK lnormalize setlinewidth } bind def /Z { setlinecap } bind def % This is used to fill or stroke white behind a Level 2 pattern /PFill { graymode fMLevel1 or not { gsave 1 setgray eofill grestore } if } bind def /PStroke { graymode fMLevel1 or not { gsave 1 setgray stroke grestore } if stroke } bind def /X { % TEXTURE fillvals exch get dup type /stringtype eq {8 1 setPatternMode} % Silly to pass parameters here {setGrayScaleMode} ifelse } bind def /V { % FILL PFill gsave eofill grestore } bind def /Vclip { clip } bind def /Vstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /N { % PEN PStroke } bind def /Nclip { strokepath clip newpath } bind def /Nstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /M {newpath moveto} bind def /E {lineto} bind def /D {curveto} bind def /O {closepath} bind def /L { % POLYLINE /n exch def newpath normalize moveto 2 1 n {pop normalize lineto} for } bind def /Y { % POLYGON !!! L % POLYLINE closepath } bind def /R { % RECT x1 y1 x2 y2 /y2 exch def /x2 exch def /y1 exch def /x1 exch def x1 y1 x2 y1 x2 y2 x1 y2 4 Y % POLYGON } bind def /rarc % Leaves all sorts of junk on the operand stack for caller to clear off {rad % arcto might fail if we're scaled way down arcto } bind def /RR { % ROUNDRECT x1 y1 x2 y2 r /rad exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def mark newpath { x1 y1 rad add moveto x1 y2 x2 y2 rarc x2 y2 x2 y1 rarc x2 y1 x1 y1 rarc x1 y1 x1 y2 rarc closepath } stopped {x1 y1 x2 y2 R} if % in case rarc failed for degenerate arcs cleartomark } bind def /RRR { % ROUNDRECT ROTATED xs ys x1 y1 x2 y2 x3 y3 x4 y4 r /rad exch def normalize /y4 exch def /x4 exch def normalize /y3 exch def /x3 exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def newpath normalize moveto % eats xs ys mark { x2 y2 x3 y3 rarc x3 y3 x4 y4 rarc x4 y4 x1 y1 rarc x1 y1 x2 y2 rarc closepath } stopped {x1 y1 x2 y2 x3 y3 x4 y4 newpath moveto lineto lineto lineto closepath} if cleartomark } bind def /C { % CLIP grestore gsave R % RECT clip setCurrentScreen } bind def /CP { % CLIPPOLY p1x p1y p2x p2y ... n grestore gsave Y % POLYGON clip setCurrentScreen } bind def /F { % FONT FMfonts exch get FMpointsize scalefont setfont } bind def /Q { % POINTSIZE (& font) /FMpointsize exch def F % could be slightly optimized here } bind def /T { % TEXT moveto show } bind def % Callers of RF (rotate/flip) must gsave (or save) first; (g)restore when done /RF { % rotate 0 ne {-1 1 scale} if } bind def /TF { % TEXTFLIPROTATE gsave moveto RF show grestore } bind def /P { % PADTEXT moveto 0 32 3 2 roll widthshow } bind def /PF { % PADTEXTFLIPROTATE gsave moveto RF 0 32 3 2 roll widthshow grestore } bind def /S { % SPREADTEXT moveto 0 exch ashow } bind def /SF { % SPREADTEXTFLIPROTATE gsave moveto RF 0 exch ashow grestore } bind def /B { % PADSPREADTEXT moveto 0 32 4 2 roll 0 exch awidthshow } bind def /BF { % PADSPREADTEXTFLIPROTATE gsave moveto RF 0 32 4 2 roll 0 exch awidthshow grestore } bind def /G { % ARCFILL theta1 theta2 width height x y gsave newpath normalize translate 0.0 0.0 moveto % eats x y dnormalize scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 closepath PFill fill grestore } bind def /Gstrk { savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch % theta1 theta2 width height x y normalize 2 index 2 div sub exch 3 index 2 div add exch % theta1 theta2 width height x y translate scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /Gclip { % ARCFILL theta1 theta2 width height x y swid newpath savematrix normalize translate 0.0 0.0 moveto % eats x y dnormalize scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 closepath clip newpath restorematrix } bind def /GG { % ARCFILL ROTATED theta1 theta2 width height angle x y gsave newpath normalize translate 0.0 0.0 moveto % eats x y rotate % eats angle dnormalize scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 closepath PFill fill grestore } bind def /GGclip { % ARCFILL ROTATED theta1 theta2 width height angle x y savematrix newpath normalize translate 0.0 0.0 moveto % eats x y rotate % eats angle dnormalize scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 closepath clip newpath restorematrix } bind def /GGstrk { % ARCFILL ROTATED swid theta1 theta2 width height angle x y savematrix newpath normalize translate 0.0 0.0 moveto % eats x y rotate % eats angle dnormalize scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 closepath restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /A { % ARCPEN theta1 theta2 width height x y gsave savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch % theta1 theta2 width height x y normalize 2 index 2 div sub exch 3 index 2 div add exch % theta1 theta2 width height x y translate scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 restorematrix PStroke grestore } bind def /Aclip { newpath savematrix normalize translate 0.0 0.0 moveto % eats x y dnormalize scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 closepath strokepath clip newpath restorematrix } bind def /Astrk { Gstrk } bind def /AA { % ARCPEN ROTATED theta1 theta2 width height angle x y gsave savematrix newpath % theta1 theta2 width height angle x y 3 index 2 div add exch 4 index 2 div sub exch % theta1 theta2 width height angle x y normalize 3 index 2 div sub exch 4 index 2 div add exch translate % eats x y rotate % eats angle scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 restorematrix PStroke grestore } bind def /AAclip { savematrix newpath normalize translate 0.0 0.0 moveto % eats x y rotate % eats angle dnormalize scale % eats width height 0.0 0.0 1.0 5 3 roll arc % eats theta1 theta2 closepath strokepath clip newpath restorematrix } bind def /AAstrk { GGstrk } bind def /BEGINPRINTCODE { % -x -y width height /FMdicttop countdictstack 1 add def % high-water mark of dict stack /FMoptop count 7 sub def % tricky! 7 params on stack, plus "/FMoptop" /FMsaveobject save def userdict begin % insulate user from FrameDict; not in /FMdicttop count /showpage {} def % this def is in userdict FMNORMALIZEGRAPHICS % in case we're in a strange state 3 index neg 3 index neg translate } bind def /ENDPRINTCODE { count -1 FMoptop {pop pop} for % clear user junk from operand stack countdictstack -1 FMdicttop {pop end} for % ditto for dict stack FMsaveobject restore % this is now safe, unless user very malicious } bind def /gn { % get a number in a funny encoding scheme 0 % result on stack { 46 mul % shift old digits cf read pop % get next character 32 sub % zero is the space character dup 46 lt {exit} if % quit if we're the last digit 46 sub add % add in this digit and loop around for next } loop add % result on stack } bind def /cfs { % create a string of length "sl" filled with "val"s /str sl string def % create string as "str" 0 1 sl 1 sub {str exch val put} for % fill array str def % define real array name, too; name is on stack from caller } bind def /ic [ % "case" stmt list of procedures that the image commands should call 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 {0 hx} {1 hx} {2 hx} {3 hx} {4 hx} {5 hx} {6 hx} {7 hx} {8 hx} {9 hx} {10 hx} {11 hx} {12 hx} {13 hx} {14 hx} {15 hx} {16 hx} {17 hx} {18 hx} {19 hx} {gn hx} {0} {1} {2} {3} {4} {5} {6} {7} {8} {9} {10} {11} {12} {13} {14} {15} {16} {17} {18} {19} {gn} {0 wh} {1 wh} {2 wh} {3 wh} {4 wh} {5 wh} {6 wh} {7 wh} {8 wh} {9 wh} {10 wh} {11 wh} {12 wh} {13 wh} {14 wh} {gn wh} {0 bl} {1 bl} {2 bl} {3 bl} {4 bl} {5 bl} {6 bl} {7 bl} {8 bl} {9 bl} {10 bl} {11 bl} {12 bl} {13 bl} {14 bl} {gn bl} {0 fl} {1 fl} {2 fl} {3 fl} {4 fl} {5 fl} {6 fl} {7 fl} {8 fl} {9 fl} {10 fl} {11 fl} {12 fl} {13 fl} {14 fl} {gn fl} ] def /ms { % make all the strings /sl exch def % remember length of currently existing strings /val 255 def % that's white /ws cfs % make "ws" a string filled with white /im cfs % and "im" is a complete image scanline /val 0 def % that's black /bs cfs % make "bs" a string filled with black /cs cfs % here's where we'll put complete command lines } bind def 400 ms % make strings that will be plenty long for most applications /ip { % image procedure; reads and executes commands to make scanlines is % leave image string and... 0 % ...image position on stack all through this procedure cf cs readline pop % get a string of commands { ic exch get exec % execute next command add % all commands leave a length on the stack; update pos } forall % step through all commands pop % get rid of image position pointer % image string left on stack, so it's returned to image primitive } bind def /rip { % this is similar to ip above, except for 24 bit images % this takes an extra argument, the width of the image % do red bis ris copy pop % copy blue to red is 0 cf cs readline pop { ic exch get exec add } forall pop pop % remove is and position from stack ris gis copy pop % copy red to green dup is exch % position of green is width bytes into is % do green cf cs readline pop { ic exch get exec add } forall pop pop gis bis copy pop % copy green to blue dup add is exch % position of blue is 2*width bytes into is % do blue cf cs readline pop { ic exch get exec add } forall pop } bind def /rip4 { % this is similar to ip above, except for 32 bit images % this takes an extra argument, the width of the image % do cyan kis cis copy pop % copy black to cyan is 0 cf cs readline pop { ic exch get exec add } forall pop pop % remove is and position from stack cis mis copy pop % copy cyan to magenta dup is exch % position of magenta is width bytes into is % do magenta cf cs readline pop { ic exch get exec add } forall pop pop mis yis copy pop % copy magenta to yellow dup dup add is exch % position of yellow is 2*width bytes into is % do yellow cf cs readline pop { ic exch get exec add } forall pop pop yis kis copy pop % copy yellow to black 3 mul is exch % position of black is 3*width bytes into is % do black cf cs readline pop { ic exch get exec add } forall pop } bind def /wh { % fill a number of bytes with "white" /len exch def % number of bytes to fill /pos exch def % position to put them at ws 0 len getinterval im pos len getinterval copy pop pos len % remember where we got to } bind def /bl { % fill a number of bytes with "black" /len exch def % number of bytes to fill /pos exch def % position to put them at bs 0 len getinterval im pos len getinterval copy pop pos len % remember where we got to } bind def /s1 1 string def /fl { % fill a number of bytes with a specific hex value /len exch def % number of bytes to fill /pos exch def % position to put them at /val cf s1 readhexstring pop 0 get def pos 1 pos len add 1 sub {im exch val put} for pos len % remember where we got to } bind def /hx { % read hex bytes directly; on entry, stack has 3 copy getinterval % stack has cf exch readhexstring pop pop % stack back to } bind def /wbytes { % width depth -> wb find width in bytes given 1, 2, 8 or 24 or 32 dup dup 8 gt { pop 8 idiv mul } { 8 eq {pop} {1 eq {7 add 8 idiv} {3 add 4 idiv} ifelse} ifelse } ifelse } bind def /BEGINBITMAPBWc { % iw, ih, width, height, theta, x y 1 {} COMMONBITMAPc } bind def /BEGINBITMAPGRAYc { % iw, ih, width, height, theta, x y 8 {} COMMONBITMAPc } bind def /BEGINBITMAP2BITc { % iw, ih, width, height, theta, x y 2 {} COMMONBITMAPc } bind def % % Common routine for imaging compressed images % /COMMONBITMAPc { % iw, ih, width, height, theta, x y depth proc % (x,y) is the lower left corner of the image /cvtProc exch def /depth exch def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /lb width depth wbytes def % so "lb" has width in bytes sl lb lt {lb ms} if % maybe make bigger strings /bitmapsave save def % LW+ has a buggy memory leak! cvtProc % run the desired proc after save has occurred /is im 0 lb getinterval def % image substring ws 0 lb getinterval is copy pop % whiten it /cf currentfile def % evaluate "currentfile" only once width height depth [width 0 0 height neg 0 height] % top to bottom {ip} image % zap! bitmapsave restore % avoid occasional disaster on the LW+ grestore } bind def /BEGINBITMAPBW { % iw, ih, width, height, theta, x y 1 {} COMMONBITMAP } bind def /BEGINBITMAPGRAY { % iw, ih, width, height, theta, x y 8 {} COMMONBITMAP } bind def /BEGINBITMAP2BIT { % iw, ih, width, height, theta, x y 2 {} COMMONBITMAP } bind def % % Common routine for uncompressed images % /COMMONBITMAP { % iw, ih, width, height, theta, x y depth proc /cvtProc exch def /depth exch def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /bitmapsave save def % LW+ has a buggy memory leak! cvtProc % run the desired proc after save has occurred /is width depth wbytes string def /cf currentfile def % evaluate "currentfile" only once width height depth [width 0 0 height neg 0 height] % top to bottom {cf is readhexstring pop} image bitmapsave restore % avoid occasional disaster on the LW+ grestore } bind def % % All this hairy color setup stuff gus wrote on the mac, I just copied and % changed the variable names to be humanly readable. /ngrayt 256 array def /nredt 256 array def /nbluet 256 array def /ngreent 256 array def fMLevel1 { /colorsetup { currentcolortransfer /gryt exch def /blut exch def /grnt exch def /redt exch def 0 1 255 { /indx exch def /cynu 1 red indx get 255 div sub def /magu 1 green indx get 255 div sub def /yelu 1 blue indx get 255 div sub def /kk cynu magu min yelu min def % The HP PaintJet XL300 ignores the gray transfer curve but still sets its % default black generation and undercolor removal functions as if it is % used. This causes black colors not to work. Bug#56844 % - We go back to the old (correct?) way of doing this since this code % is now bypassed for PS Level 2 printers in favor of colorSetup2 which % uses PS Level 2 indexed color, which is much cleaner. /u kk currentundercolorremoval exec def %- /u 0 def nredt indx 1 0 cynu u sub max sub redt exec put ngreent indx 1 0 magu u sub max sub grnt exec put nbluet indx 1 0 yelu u sub max sub blut exec put ngrayt indx 1 kk currentblackgeneration exec sub gryt exec put } for {255 mul cvi nredt exch get} {255 mul cvi ngreent exch get} {255 mul cvi nbluet exch get} {255 mul cvi ngrayt exch get} setcolortransfer {pop 0} setundercolorremoval {} setblackgeneration } bind def } { % Here, we set up indexed color for imaging on PS Level 2 without mucking around % with the transfer functions. /colorSetup2 { [ /Indexed /DeviceRGB 255 {dup red exch get 255 div exch dup green exch get 255 div exch blue exch get 255 div} ] setcolorspace } bind def } ifelse % % Setup a transfer function to convert psuedo color values into grayscale % values based on the color lookup tables. % /fakecolorsetup { /tran 256 string def 0 1 255 {/indx exch def tran indx red indx get 77 mul green indx get 151 mul blue indx get 28 mul add add 256 idiv put} for currenttransfer {255 mul cvi tran exch get 255.0 div} exch fmConcatProcs settransfer } bind def % % image a color image % /BITMAPCOLOR { % iw, ih, width, height, theta, x y /depth 8 def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /bitmapsave save def fMLevel1 { colorsetup /is width depth wbytes string def /cf currentfile def % evaluate "currentfile" only once width height depth [width 0 0 height neg 0 height] % top to bottom {cf is readhexstring pop} {is} {is} true 3 colorimage } { colorSetup2 /is width depth wbytes string def /cf currentfile def % evaluate "currentfile" only once 7 dict dup begin /ImageType 1 def /Width width def /Height height def /ImageMatrix [width 0 0 height neg 0 height] def /DataSource {cf is readhexstring pop} bind def /BitsPerComponent depth def /Decode [0 255] def end image } ifelse bitmapsave restore grestore } bind def % % Compressed color image rendering % /BITMAPCOLORc { % iw, ih, width, height, theta, x y /depth 8 def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /lb width depth wbytes def % so "lb" has width in bytes sl lb lt {lb ms} if % maybe make bigger strings /bitmapsave save def fMLevel1 { colorsetup /is im 0 lb getinterval def % image substring ws 0 lb getinterval is copy pop % whiten it /cf currentfile def % evaluate "currentfile" only once width height depth [width 0 0 height neg 0 height] % top to bottom {ip} {is} {is} true 3 colorimage } { colorSetup2 /is im 0 lb getinterval def % image substring ws 0 lb getinterval is copy pop % whiten it /cf currentfile def % evaluate "currentfile" only once 7 dict dup begin /ImageType 1 def /Width width def /Height height def /ImageMatrix [width 0 0 height neg 0 height] def /DataSource {ip} bind def /BitsPerComponent depth def /Decode [0 255] def end image } ifelse bitmapsave restore grestore } bind def /BITMAPTRUECOLORc { /depth 24 def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /lb width depth wbytes def % so "lb" has width in bytes sl lb lt {lb ms} if % maybe make bigger strings /bitmapsave save def /is im 0 lb getinterval def % Whole scanline /ris im 0 width getinterval def % red part of im /gis im width width getinterval def % green part of im /bis im width 2 mul width getinterval def % blue part of im ws 0 lb getinterval is copy pop /cf currentfile def width height 8 [width 0 0 height neg 0 height] {width rip pop ris} {gis} {bis} true 3 colorimage bitmapsave restore grestore } bind def /BITMAPCMYKc { /depth 32 def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /lb width depth wbytes def % so "lb" has width in bytes sl lb lt {lb ms} if % maybe make bigger strings /bitmapsave save def /is im 0 lb getinterval def % Whole scanline /cis im 0 width getinterval def % cyan part of im /mis im width width getinterval def % magenta part of im /yis im width 2 mul width getinterval def % yellow part of im /kis im width 3 mul width getinterval def % black part of im ws 0 lb getinterval is copy pop /cf currentfile def width height 8 [width 0 0 height neg 0 height] {width rip4 pop cis} {mis} {yis} {kis} true 4 colorimage bitmapsave restore grestore } bind def /BITMAPTRUECOLOR { gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /bitmapsave save def /is width string def /gis width string def /bis width string def /cf currentfile def width height 8 [width 0 0 height neg 0 height] { cf is readhexstring pop } { cf gis readhexstring pop } { cf bis readhexstring pop } true 3 colorimage bitmapsave restore grestore } bind def /BITMAPCMYK { gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /bitmapsave save def /is width string def /mis width string def /yis width string def /kis width string def /cf currentfile def width height 8 [width 0 0 height neg 0 height] { cf is readhexstring pop } { cf mis readhexstring pop } { cf yis readhexstring pop } { cf kis readhexstring pop } true 4 colorimage bitmapsave restore grestore } bind def % % image a color image to a b&width device % /BITMAPTRUEGRAYc { /depth 24 def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /lb width depth wbytes def % so "lb" has width in bytes sl lb lt {lb ms} if % maybe make bigger strings /bitmapsave save def /is im 0 lb getinterval def % Whole scanline /ris im 0 width getinterval def % red part of im /gis im width width getinterval def % green part of im /bis im width 2 mul width getinterval def % blue part of im ws 0 lb getinterval is copy pop /cf currentfile def width height 8 [width 0 0 height neg 0 height] {width rip pop ris gis bis width gray} image bitmapsave restore grestore } bind def /BITMAPCMYKGRAYc { /depth 32 def gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /lb width depth wbytes def % so "lb" has width in bytes sl lb lt {lb ms} if % maybe make bigger strings /bitmapsave save def /is im 0 lb getinterval def % Whole scanline /cis im 0 width getinterval def % cyan part of im /mis im width width getinterval def % magenta part of im /yis im width 2 mul width getinterval def % yellow part of im /kis im width 3 mul width getinterval def % black part of im ws 0 lb getinterval is copy pop /cf currentfile def width height 8 [width 0 0 height neg 0 height] {width rip pop cis mis yis kis width cgray} image bitmapsave restore grestore } bind def /cgray { % c m y k width /ww exch def /k exch def /y exch def /m exch def /c exch def 0 1 ww 1 sub { /i exch def c i get m i get y i get k i get CMYKtoRGB .144 mul 3 1 roll .587 mul 3 1 roll .299 mul add add c i 3 -1 roll floor cvi put } for c } bind def /gray { % r g b width /ww exch def /b exch def /g exch def /r exch def 0 1 ww 1 sub { /i exch def r i get .299 mul g i get .587 mul b i get .114 mul add add r i 3 -1 roll floor cvi put } for r } bind def /BITMAPTRUEGRAY { gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /bitmapsave save def /is width string def /gis width string def /bis width string def /cf currentfile def width height 8 [width 0 0 height neg 0 height] { cf is readhexstring pop cf gis readhexstring pop cf bis readhexstring pop width gray} image bitmapsave restore grestore } bind def /BITMAPCMYKGRAY { gsave % rotate about center of image 3 index 2 div add exch % iw ih width height theta y+(height/2) x 4 index 2 div add exch % iw ih width height theta x+(width/2) y+(height/2) translate % iw ih width height theta rotate % iw ih width height 1 index 2 div neg % iw ih width height -(width/2) 1 index 2 div neg % iw ih width height -(width/2) -(height/2) translate % iw ih width height scale % iw ih /height exch def /width exch def /bitmapsave save def /is width string def /yis width string def /mis width string def /kis width string def /cf currentfile def width height 8 [width 0 0 height neg 0 height] { cf is readhexstring pop cf mis readhexstring pop cf yis readhexstring pop cf kis readhexstring pop width cgray} image bitmapsave restore grestore } bind def /BITMAPGRAY { % iw, ih, width, height, theta, x y 8 {fakecolorsetup} COMMONBITMAP } bind def /BITMAPGRAYc { % iw, ih, width, height, theta, x y 8 {fakecolorsetup} COMMONBITMAPc } bind def /ENDBITMAP { } bind def end % of FrameDict definitions % OPI stuff /ALDmatrix matrix def ALDmatrix currentmatrix pop /StartALD { /ALDsave save def savematrix ALDmatrix setmatrix } bind def /InALD { restorematrix } bind def /DoneALD { ALDsave restore } bind def % Dashed lines stuff /I { setdash } bind def /J { [] 0 setdash } bind def %%EndProlog %%BeginSetup (5.0) FMVERSION 1 1 0 0 612 792 0 1 12 FMDOCUMENT 0 0 /Helvetica-Bold FMFONTDEFINE 1 0 /Times-Roman FMFONTDEFINE 2 0 /Times-Bold FMFONTDEFINE 3 0 /Times-Italic FMFONTDEFINE 4 1 /Symbol FMFONTDEFINE 5 1 /ZapfDingbats FMFONTDEFINE 32 FMFILLS 0 0 FMFILL 1 0.1 FMFILL 2 0.3 FMFILL 3 0.5 FMFILL 4 0.7 FMFILL 5 0.9 FMFILL 6 0.97 FMFILL 7 1 FMFILL 8 <0f1e3c78f0e1c387> FMFILL 9 <0f87c3e1f0783c1e> FMFILL 10 FMFILL 11 FMFILL 12 <8142241818244281> FMFILL 13 <03060c183060c081> FMFILL 14 <8040201008040201> FMFILL 16 1 FMFILL 17 0.9 FMFILL 18 0.7 FMFILL 19 0.5 FMFILL 20 0.3 FMFILL 21 0.1 FMFILL 22 0.03 FMFILL 23 0 FMFILL 24 FMFILL 25 FMFILL 26 <3333333333333333> FMFILL 27 <0000ffff0000ffff> FMFILL 28 <7ebddbe7e7dbbd7e> FMFILL 29 FMFILL 30 <7fbfdfeff7fbfdfe> FMFILL %%EndSetup %%Page: "1" 1 %%BeginPaperSize: Letter %%EndPaperSize 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K J 0 0 0 1 0 0 0 K 0 14 Q 0 X 0 0 0 1 0 0 0 K (FPGA Routing Ar) 75.19 710.67 T (c) 190.02 710.67 T (hitecture: Segmentation and Buff) 197.66 710.67 T (ering to Optimiz) 422.32 710.67 T (e) 529.03 710.67 T 54 -63/G1004875 FmPA (Speed and Density) 243.37 693.67 T 1 10 Q (V) 241.57 674.33 T (aughn Betz and Jonathan Rose) 247.68 674.33 T 54 -26/G1005563 FmPA (Department of Electrical and Computer Engineering, Uni) 155.38 660.33 T (v) 384.8 660.33 T (ersity of T) 389.65 660.33 T (oronto) 430.52 660.33 T 54 -12/G1005564 FmPA (T) 230.43 648.33 T (oronto, Ontario, Canada M5S 3G4) 235.74 648.33 T 54 0/G1009157 FmPA ({v) 236.18 636.33 T (aughn, jayar}@eecg.toronto.edu) 245.73 636.33 T 54 12/G1005566 FmPA 2 12 Q (Abstract) 53.33 604 T 53 44/G1005569 FmPA 1 9 Q -0.06 (In this w) 71.33 588 P -0.06 (ork we in) 102.63 588 P -0.06 (v) 136.15 588 P -0.06 (estig) 140.52 588 P -0.06 (ate the routing architecture of FPGAs,) 157.47 588 P 53 60/G1005567 FmPA 0.75 (focusing primarily on determining the best distrib) 53.33 578 P 0.75 (ution of routing) 236.66 578 P 1.35 (se) 53.33 568 P 1.35 (gment lengths and the best mix of pass transistor and tri-state) 60.69 568 P 0.94 (b) 53.33 558 P 0.94 (uf) 57.65 558 P 0.94 (fer routing switches. While most commercial FPGAs contain) 64.93 558 P 0.08 (man) 53.33 548 P 0.08 (y length 1 wires \050wires that span only one logic block\051 we \336nd) 68.7 548 P -0.18 (that wires this short lead to FPGAs that are inferior in terms of both) 53.33 538 P 0.39 (delay and routing area. Our results sho) 53.33 528 P 0.39 (w instead that it is best for) 197.32 528 P 0.08 (FPGA routing se) 53.33 518 P 0.08 (gments to ha) 114.36 518 P 0.08 (v) 160.33 518 P 0.08 (e lengths of 4 to 8 logic blocks. W) 164.7 518 P 0.08 (e) 290.67 518 P 1.13 (also sho) 53.33 508 P 1.13 (w that 50% to 80% of the routing switches in an FPGA) 83.49 508 P 0.59 (should be pass transistors, with the remainder being tri-state b) 53.33 498 P 0.59 (uf) 281.4 498 P 0.59 (f-) 288.67 498 P 0.44 (ers. Architectures that emplo) 53.33 488 P 0.44 (y the best se) 161.22 488 P 0.44 (gmentation distrib) 206.65 488 P 0.44 (utions) 272.66 488 P 0.94 (and the best mix) 53.33 478 P 0.94 (es of pass transistor and tri-state b) 115.27 478 P 0.94 (uf) 243.22 478 P 0.94 (fer switches) 250.49 478 P 0.55 (found in this paper are not only 11% to 18% f) 53.33 468 P 0.55 (aster than a routing) 223.77 468 P 1.07 (architecture v) 53.33 458 P 1.07 (ery similar to that of the Xilinx XC4000X b) 103.5 458 P 1.07 (ut also) 269.85 458 P -0.01 (considerably simpler) 53.33 448 P -0.01 (. These results are obtained using an architec-) 128.07 448 P 0.5 (ture in) 53.33 438 P 0.5 (v) 76.72 438 P 0.5 (estig) 81.09 438 P 0.5 (ation infrastructure that contains a fully timing-dri) 98.04 438 P 0.5 (v) 281.81 438 P 0.5 (en) 286.17 438 P (router and detailed area and delay models.) 53.33 428 T 2 12 Q (1) 53.33 404 T (Intr) 71.33 404 T (oduction) 91.78 404 T 53 244/G1005571 FmPA 1 9 Q 2.38 (FPGAs consist of a lar) 71.33 388 P 2.38 (ge number of programmable logic) 162.18 388 P 53 260/G999465 FmPA 0.24 (blocks, which can each implement a small amount of digital logic,) 53.33 378 P 0.04 (and programmable routing which allo) 53.33 368 P 0.04 (ws the logic block inputs and) 189.24 368 P 0.16 (outputs to be connected to form lar) 53.33 358 P 0.16 (ger circuits. The delay of a cir-) 180.1 358 P 1.81 (cuit implemented in an FPGA is mostly due to routing delays,) 53.33 348 P 1.94 (rather than logic block delays, and most of an FPGA) 53.33 338 P 1.94 (\325) 259.29 338 P 1.94 (s area is) 261.79 338 P 1.97 (de) 53.33 328 P 1.97 (v) 61.6 328 P 1.97 (oted to programmable routing [1]. Furthermore, as FPGAs) 65.92 328 P 0.74 (mo) 53.33 318 P 0.74 (v) 64.7 318 P 0.74 (e into increasingly deep submicron IC processes, the fraction) 69.07 318 P -0.17 (of total delay due to routing is increasing with each process genera-) 53.33 308 P 2.52 (tion [2]. Consequently) 53.33 298 P 2.52 (, one must de) 143.31 298 P 2.52 (vise routing architectures) 198.64 298 P 0.36 (which are both f) 53.33 288 P 0.36 (ast and area-ef) 113.06 288 P 0.36 (\336cient to create an FPGA that fully) 166.02 288 P 0.68 (e) 53.33 278 P 0.68 (xploits the performance and density potential of deep-submicron) 57.19 278 P (technologies.) 53.33 268 T 0.55 (In this paper we in) 71.33 254 P 0.55 (v) 140.16 254 P 0.55 (estig) 144.52 254 P 0.55 (ate island-style FPGA routing archi-) 161.48 254 P 53 394/G1005584 FmPA 1.25 (tectures; the FPGAs of Xilinx [3], Lucent T) 53.33 244 P 1.25 (echnologies [4], and) 218.93 244 P 0.82 (V) 53.33 234 P 0.82 (antis [5] emplo) 58.83 234 P 0.82 (y this style of routing architecture. A simpli\336ed) 114.88 234 P 0.84 (vie) 53.33 224 P 0.84 (w of an island-style FPGA is sho) 64.11 224 P 0.84 (wn in Figure 1. The routing) 187.9 224 P (architecture of an FPGA de\336nes such features as:) 53.33 214 T (1.) 67.73 200 T 0.42 (The length of each routing wire se) 82.13 200 P 0.42 (gment \050ho) 208.01 200 P 0.42 (w man) 244.96 200 P 0.42 (y logic) 269.49 200 P 53 448/G1005848 FmPA (blocks a routing wire spans before terminating\051,) 82.13 190 T (2.) 331.07 605.33 T 1.16 (Whether each routing switch is a pass transistor or a tri-) 345.47 605.33 P 317 43/G1005853 FmPA (state b) 345.47 595.33 T (uf) 368.53 595.33 T (fer) 375.81 595.33 T (,) 385.44 595.33 T (3.) 331.07 581.33 T 2.55 (Where routing switches are located and which routing) 345.47 581.33 P 317 67/G1005860 FmPA (wires the) 345.47 571.33 T (y can connect together) 378.07 571.33 T (,) 458.94 571.33 T (4.) 331.07 557.33 T 1.98 (Which routing wires in the channel adjacent to a logic) 345.47 557.33 P 317 91/G1005587 FmPA (block input or output can connect to that logic block pin,) 345.47 547.33 T (5.) 331.07 533.33 T 0.9 (The sizes of the transistors used to b) 345.47 533.33 P 0.9 (uild the v) 482.29 533.33 P 0.9 (arious pro-) 517.86 533.33 P 317 115/G1005597 FmPA (grammable switches, and) 345.47 523.33 T (6.) 331.07 509.33 T (The metal width and spacing of the routing wires.) 345.47 509.33 T 317 139/G1005601 FmPA 1.5 (In Figure 1, for e) 334.67 495.33 P 1.5 (xample, half the routing tracks consist of) 401.77 495.33 P 317 153/G1005602 FmPA 1.36 (length 1 wire se) 316.67 485.33 P 1.36 (gments, while the other half consist of length 2) 377.86 485.33 P 1.11 (wire se) 316.67 475.33 P 1.11 (gments. Some of the programmable routing switches are) 343.38 475.33 P (pass transistors, while others are tri-state b) 316.67 465.33 T (uf) 469.71 465.33 T (fers.) 476.98 465.33 T 0.49 (In this paper we will focus primarily on determining the best) 334.67 451.33 P 317 197/G1005842 FmPA 0.06 (v) 316.67 441.33 P 0.06 (alues for parameters 1 and 2 abo) 320.94 441.33 P 0.06 (v) 440.45 441.33 P 0.06 (e: the best) 444.81 441.33 P 3 F 0.06 (se) 486.05 441.33 P 0.06 (gmentation distri-) 493.18 441.33 P 0.31 (b) 316.67 431.33 P 0.31 (ution) 320.99 431.33 P 1 F 0.31 ( \050lengths of routing wire se) 339.49 431.33 P 0.31 (gments\051 and the best mix of pass) 438.14 431.33 P 2.89 (transistor and tri-state b) 316.67 421.33 P 2.89 (uf) 410.39 421.33 P 2.89 (fer switches. W) 417.66 421.33 P 2.89 (e ha) 484.09 421.33 P 2.89 (v) 501.54 421.33 P 2.89 (e in) 505.91 421.33 P 2.89 (v) 521.68 421.33 P 2.89 (estig) 526.05 421.33 P 2.89 (ated) 543.01 421.33 P 0.98 (appropriate v) 316.67 411.33 P 0.98 (alues for the other four parameters [6, 7], b) 365.16 411.33 P 0.98 (ut space) 527.78 411.33 P 1.62 (limitations preclude more than a brief discussion of these other) 316.67 401.33 P 1.24 (four issues in this paper) 316.67 391.33 P 1.24 (. Note ho) 406.61 391.33 P 1.24 (we) 445.58 391.33 P 1.24 (v) 455.85 391.33 P 1.24 (er) 460.22 391.33 P 1.24 (, that we set the other 4) 466.85 391.33 P 0.09 (parameters to reasonable v) 316.67 381.33 P 0.09 (alues throughout the e) 412.94 381.33 P 0.09 (xperiments of this) 492.82 381.33 P -0.03 (paper) 316.67 371.33 P -0.03 (, as this is essential for meaningful architectural comparisons.) 336.3 371.33 P 1.32 (Routing architecture design is v) 334.67 357.33 P 1.32 (ery challenging because the) 454.31 357.33 P 317 291/G1005607 FmPA 0.95 (best v) 316.67 347.33 P 0.95 (alue for each of the parameters abo) 338.64 347.33 P 0.95 (v) 470.68 347.33 P 0.95 (e depends on comple) 475.04 347.33 P 0.95 (x) 553.5 347.33 P 0.82 (trade-of) 316.67 337.33 P 0.82 (fs. F) 344.93 337.33 P 0.82 (or e) 364.68 337.33 P 0.82 (xample, in an FPGA with too man) 379.1 337.33 P 0.82 (y short wires,) 507.62 337.33 P 0.05 (some long connections will be constructed using se) 316.67 327.33 P 0.05 (v) 501.55 327.33 P 0.05 (eral short wire) 505.91 327.33 P 0.16 (se) 316.67 317.33 P 0.16 (gments connected in series, resulting in poor speed. If an FPGA) 324.03 317.33 P 1.49 (includes too man) 316.67 307.33 P 1.49 (y long wires, ho) 381.01 307.33 P 1.49 (we) 443.26 307.33 P 1.49 (v) 453.53 307.33 P 1.49 (er) 457.9 307.33 P 1.49 (, some short connections) 464.53 307.33 P 1.74 (will be forced to use long wire se) 316.67 297.33 P 1.74 (gments, de) 448.43 297.33 P 1.74 (grading speed and) 489.04 297.33 P 0.51 (w) 316.67 287.33 P 0.51 (asting area. Similarly) 323.08 287.33 P 0.51 (, an architecture with too man) 403.03 287.33 P 0.51 (y or too fe) 512.94 287.33 P 0.51 (w) 551.5 287.33 P 1.55 (tri-state b) 316.67 277.33 P 1.55 (uf) 352.28 277.33 P 1.55 (fer routing switches will lik) 359.56 277.33 P 1.55 (ely be suboptimal. P) 465.17 277.33 P 1.55 (ass) 547 277.33 P -0.17 (transistor switches require less area, and the) 316.67 267.33 P -0.17 (y are f) 473.72 267.33 P -0.17 (aster than b) 496.27 267.33 P -0.17 (uf) 537.24 267.33 P -0.17 (fers) 544.51 267.33 P 2.3 (for short connections, b) 316.67 257.33 P 2.3 (ut connections that pass through man) 408.38 257.33 P 2.3 (y) 553.5 257.33 P 316.67 70.67 558 611.33 C 316.67 70.67 558 251.37 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 2 9 Q 0 X 0 0 0 1 0 0 0 K (Figur) 329.01 75.71 T (e 1:) 350.35 75.71 T 1 F ( Example island-style FPGA routing architecture.) 364.09 75.71 T 317 572/G1005824 FmPA 343.78 189.61 367.22 213.04 R 0.5 H 0 Z N 354.25 187.51 358.24 191.5 R V N 365.02 199.68 369.01 203.67 R V N 343.78 181.53 367.72 181.53 2 L 2 H N 375.49 188.21 375.49 212.14 2 L N 369.21 201.47 386.17 201.47 2 L 0.5 H N 373.35 203.32 377.54 199.13 2 L N 373.35 199.13 377.54 203.32 2 L N 354.2 183.57 358.39 179.38 2 L N 354.2 179.38 358.39 183.57 2 L N 395.44 189.61 418.87 213.04 R N 405.91 187.51 409.9 191.5 R V N 416.68 199.68 420.67 203.67 R V N 395.44 181.53 419.37 181.53 2 L 2 H N 427.15 188.21 427.15 212.14 2 L N 420.87 201.47 437.82 201.47 2 L 0.5 H N 425.01 203.32 429.19 199.13 2 L N 425.01 199.13 429.19 203.32 2 L N 405.86 183.57 410.05 179.38 2 L N 405.86 179.38 410.05 183.57 2 L N 344.28 172.05 420.07 172.05 2 L 2 H N 356.25 188.51 356.25 181.03 2 L 0.5 H N 408.1 188.01 408.1 181.03 2 L N 343.78 140.94 367.22 164.38 R N 354.25 138.85 358.24 142.84 R V N 365.02 151.01 369.01 155 R V N 343.78 132.86 367.72 132.86 2 L 2 H N 375.49 139.55 375.49 163.48 2 L N 369.21 152.81 386.17 152.81 2 L 0.5 H N 373.35 154.65 377.54 150.47 2 L N 373.35 150.47 377.54 154.65 2 L N 354.2 134.91 358.39 130.72 2 L N 354.2 130.72 358.39 134.91 2 L N 395.44 140.94 418.87 164.38 R N 405.91 138.85 409.9 142.84 R V N 416.68 151.01 420.67 155 R V N 395.44 132.86 419.37 132.86 2 L 2 H N 427.15 139.55 427.15 163.48 2 L N 420.87 152.81 437.82 152.81 2 L 0.5 H N 425.01 154.65 429.19 150.47 2 L N 425.01 150.47 429.19 154.65 2 L N 405.86 134.91 410.05 130.72 2 L N 405.86 130.72 410.05 134.91 2 L N 344.28 123.39 420.07 123.39 2 L 2 H N 356.25 139.84 356.25 132.37 2 L 0.5 H N 408.1 139.35 408.1 132.37 2 L N 386.17 211.44 386.17 140.14 2 L 2 H N 438.32 211.44 438.32 140.14 2 L N 436.27 203.52 440.46 199.33 2 L 0.5 H N 436.27 199.33 440.46 203.52 2 L N 383.72 203.22 387.91 199.03 2 L N 383.72 199.03 387.91 203.22 2 L N 384.02 154.55 388.21 150.37 2 L N 384.02 150.37 388.21 154.55 2 L N 436.17 154.26 440.36 150.07 2 L N 436.17 150.07 440.36 154.26 2 L N 423.04 168.43 426.87 172.26 423.04 176.08 3 Y N 426.87 172.26 429.02 172.26 429.02 174.65 433.57 174.65 433.57 172.02 436.44 172.02 6 L N 429.01 176.34 433.5 176.34 2 L N 375.2 181.63 377.89 181.63 377.89 184.62 383.57 184.62 383.57 181.33 387.16 181.33 6 L N 377.79 186.37 383.27 186.37 2 L N 356.06 117.74 354.19 119.5 359.11 120.97 357.92 115.97 4 Y N 356.06 117.74 354.19 119.5 359.11 120.97 357.92 115.97 4 Y V 355.89 117.56 346.84 107.98 2 L N 446.8 189.61 470.23 213.04 R N 457.27 187.51 461.25 191.5 R V N 468.04 199.68 472.02 203.67 R V N 446.8 181.53 470.73 181.53 2 L 2 H N 478.51 188.21 478.51 212.14 2 L N 472.22 201.47 489.18 201.47 2 L 0.5 H N 476.36 203.32 480.55 199.13 2 L N 476.36 199.13 480.55 203.32 2 L N 457.22 183.57 461.4 179.38 2 L N 457.22 179.38 461.4 183.57 2 L N 498.45 189.61 521.88 213.04 R N 508.92 187.51 512.91 191.5 R V N 519.69 199.68 523.68 203.67 R V N 498.45 181.53 522.38 181.53 2 L 2 H N 530.16 188.21 530.16 212.14 2 L N 523.88 201.47 540.83 201.47 2 L 0.5 H N 528.02 203.32 532.21 199.13 2 L N 528.02 199.13 532.21 203.32 2 L N 508.87 183.57 513.06 179.38 2 L N 508.87 179.38 513.06 183.57 2 L N 447.29 172.05 523.08 172.05 2 L 2 H N 459.26 188.51 459.26 181.03 2 L 0.5 H N 511.11 188.01 511.11 181.03 2 L N 446.8 140.94 470.23 164.38 R N 457.27 138.85 461.25 142.84 R V N 468.04 151.01 472.02 155 R V N 446.8 132.86 470.73 132.86 2 L 2 H N 478.51 139.55 478.51 163.48 2 L N 472.22 152.81 489.18 152.81 2 L 0.5 H N 476.36 154.65 480.55 150.47 2 L N 476.36 150.47 480.55 154.65 2 L N 457.22 134.91 461.4 130.72 2 L N 457.22 130.72 461.4 134.91 2 L N 498.45 140.94 521.88 164.38 R N 508.92 138.85 512.91 142.84 R V N 519.69 151.01 523.68 155 R V N 498.45 132.86 522.38 132.86 2 L 2 H N 530.16 139.55 530.16 163.48 2 L N 523.88 152.81 540.83 152.81 2 L 0.5 H N 528.02 154.65 532.21 150.47 2 L N 528.02 150.47 532.21 154.65 2 L N 508.87 134.91 513.06 130.72 2 L N 508.87 130.72 513.06 134.91 2 L N 447.29 123.39 523.08 123.39 2 L 2 H N 459.26 139.84 459.26 132.37 2 L 0.5 H N 511.11 139.35 511.11 132.37 2 L N 489.18 211.44 489.18 140.14 2 L 2 H N 541.33 211.44 541.33 140.14 2 L N 539.28 203.52 543.48 199.33 2 L 0.5 H N 539.28 199.33 543.48 203.52 2 L N 486.98 203.47 491.17 199.28 2 L N 486.98 199.28 491.17 203.47 2 L N 487.03 154.55 491.22 150.37 2 L N 487.03 150.37 491.22 154.55 2 L N 539.19 154.26 543.37 150.07 2 L N 539.19 150.07 543.37 154.26 2 L N 375.29 181.73 367.32 181.73 2 L N 386.46 181.43 397.23 181.43 2 L N 436.74 174.41 432.91 178.24 436.74 182.07 3 Y N 432.91 178.24 430.76 178.24 430.76 180.63 426.21 180.63 426.21 178 423.34 178 6 L N 430.77 182.33 426.25 182.33 2 L N 378.68 192.39 381.01 193.48 380.57 188.37 376.36 191.3 4 Y N 378.68 192.39 381.01 193.48 380.57 188.37 376.36 191.3 4 Y V 378.58 192.62 364.79 222 2 L N (P) 325.74 234.63 T (ass transistor) 330.61 234.63 T 430.99 186.44 433.47 187.11 432.16 182.15 428.51 185.77 4 Y N 430.99 186.44 433.47 187.11 432.16 182.15 428.51 185.77 4 Y V 430.92 186.68 420.79 224 2 L N 436.82 172.06 447.89 172.06 2 L 2 Z N 420.07 172.35 423.06 172.35 2 L N 423.36 178.04 419.17 178.04 419.17 172.06 3 L 0 Z N 447.89 172.06 447.89 178.34 436.82 178.34 3 L N (Routing wire) 326.27 102.16 T (routing switch) 326.32 225.26 T 461.8 126.02 459.52 124.84 459.77 129.97 464.08 127.19 4 Y N 461.8 126.02 459.52 124.84 459.77 129.97 464.08 127.19 4 Y V 461.91 125.8 468.67 112.67 2 L N (T) 403.12 237.67 T (ri-state b) 408.3 237.67 T (uf) 439.87 237.67 T (fer) 447.14 237.67 T (routing switch) 405.12 228 T (Logic block pin to) 443.45 104.67 T (routing connection point) 442.79 95 T 512.56 207.64 514.79 206.37 510.37 203.77 510.33 208.9 4 Y N 512.56 207.64 514.79 206.37 510.37 203.77 510.33 208.9 4 Y V 512.68 207.85 521.45 223.33 2 L N (Logic block) 504.79 227.33 T 316.67 70.67 558 611.33 C 0 0 612 792 C 0 0 0 1 0 0 0 K [/Creator(FrameMaker xm5.1.1P1b)/DOCINFO FmPD2 [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.1/DEST FmPD2 369 847/M9.32399.Heading1.Chapter.7.Detailed.Routing.Architecture FmPA 369 847/I1.1004507 FmPA 369 847/M9.11440.Heading1.Chapter.7 FmPA 369 847/I1.1004878 FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C 364 226/M9.34505.Figure.Figure.1.Example.islandstyle.routing.architecture FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C 364 226/I1.1005826 FmPA [/Rect[82 229 86 239]/Border[0 0 0]/Page 10/View[/XYZ null 74 676 FmDC exch pop null]/LNK FmPD [/Rect[510 407 515 417]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[187 323 191 333]/Border[0 0 0]/Page 10/View[/XYZ null 74 768 FmDC exch pop null]/LNK FmPD [/Rect[172 239 177 249]/Border[0 0 0]/Page 10/View[/XYZ null 74 702 FmDC exch pop null]/LNK FmPD [/Rect[268 239 273 249]/Border[0 0 0]/Page 10/View[/XYZ null 74 689 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[212 219 243 229]/Border[0 0 0]/Page 1/View[/XYZ null 364 226 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[346 491 378 501]/Border[0 0 0]/Page 1/View[/XYZ null 364 226 FmDC exch pop null]/LNK FmPD [/Rect[75 293 80 303]/Border[0 0 0]/Page 10/View[/XYZ null 74 735 FmDC exch pop null]/LNK FmPD [/Rect[500 407 505 417]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 620 567 729]/ARTICLE FmPD2 [/Title(A)/Rect[44 170 304 621]/ARTICLE FmPD2 [/Title(A)/Rect[308 62 567 620]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "1" 1 %%Page: "2" 2 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 1 9 Q 0 X 0 0 0 1 0 0 0 K 0.59 (series switches are better serv) 54 714 P 0.59 (ed by tri-state b) 163.18 714 P 0.59 (uf) 221.01 714 P 0.59 (fers. As well, the) 228.28 714 P 1.67 (best mix of routing switches is dependent on the length of the) 54 704 P 2.11 (FPGA) 54 694 P 2.11 (\325) 76 694 P 2.11 (s routing wire se) 78.51 694 P 2.11 (gments. In an FPGA with man) 144.46 694 P 2.11 (y long) 269.25 694 P 1.96 (wires, it will rarely be necessary to connect man) 54 684 P 1.96 (y switches in) 243.21 684 P 1.33 (series to mak) 54 674 P 1.33 (e a connection. Consequently) 104.07 674 P 1.33 (, such an FPGA can) 217.05 674 P 0.39 (lik) 54 664 P 0.39 (ely use a higher fraction of pass transistor) 63.41 664 P 0.39 (-based switches in its) 216.2 664 P (routing than an FPGA that contains fe) 54 654 T (w long wires.) 190.76 654 T 1.7 (Considering the importance of routing architecture to both) 72 640 P 54 784/G1005841 FmPA 0 (FPGA area and speed, relati) 54 630 P 0 (v) 155.02 630 P 0 (ely little research has been conducted) 159.38 630 P -0.02 (in this area. Some prior w) 54 620 P -0.02 (ork [8, 9, 10, 11] has in) 149.04 620 P -0.02 (v) 232.81 620 P -0.02 (estig) 237.18 620 P -0.02 (ated dif) 254.13 620 P -0.02 (fer-) 281.13 620 P 0.93 (ent switch topologies for use in FPGAs where all wire se) 54 610 P 0.93 (gments) 268.12 610 P 0.69 (are of length 1 \050i.e. span only a single logic block\051 and has com-) 54 600 P 0.35 (pared architectures only in terms of area-ef) 54 590 P 0.35 (\336cienc) 210.8 590 P 0.35 (y) 234.66 590 P 0.35 (. Some studies) 238.57 590 P 2.04 (ha) 54 580 P 2.04 (v) 62.32 580 P 2.04 (e in) 66.68 580 P 2.04 (v) 81.61 580 P 2.04 (estig) 85.97 580 P 2.04 (ated the best distrib) 102.93 580 P 2.04 (ution of routing wire se) 179.11 580 P 2.04 (gment) 271.62 580 P -0.04 (lengths for use in ro) 54 570 P -0.04 (w-based FPGAs [12, 13, 14, 15], b) 125.62 570 P -0.04 (ut the meth-) 250.7 570 P 2.26 (odology used in these studies is not applicable to island-style) 54 560 P -0.17 (FPGAs. The most directly comparable w) 54 550 P -0.17 (ork to this paper is that of) 202.63 550 P 0.76 (Bro) 54 540 P 0.76 (wn et al [16, 17] and Cho) 67.28 540 P 0.76 (w et al [18]. These studies in) 163.33 540 P 0.76 (v) 274.26 540 P 0.76 (esti-) 278.62 540 P 0.6 (g) 54 530 P 0.6 (ated island-style FPGAs which contained some longer wire se) 58.46 530 P 0.6 (g-) 286.62 530 P 1 (ments. W) 54 520 P 1 (e e) 92.02 520 P 1 (xtend this prior research in se) 103.13 520 P 1 (v) 214.11 520 P 1 (eral important w) 218.48 520 P 1 (ays,) 279.87 520 P 3 (ho) 54 510 P 3 (we) 62.78 510 P 3 (v) 73.04 510 P 3 (er) 77.41 510 P 3 (. First, we consider the possibility of some routing) 83.91 510 P 2.29 (switches being tri-state b) 54 500 P 2.29 (uf) 150.44 500 P 2.29 (fers, whereas all prior research has) 157.71 500 P 0.05 (in) 54 490 P 0.05 (v) 60.64 490 P 0.05 (estig) 65.01 490 P 0.05 (ated FPGAs containing only pass transistor switches. Sec-) 81.96 490 P -0.05 (ond, we compare FPGAs on the basis of the \322true\323 delay metric \321) 54 480 P 0.04 (critical path delay of benchmark circuits \321 and a detailed, transis-) 54 470 P 1.69 (tor) 54 460 P 1.69 (-based area model; prior research has used simpler) 63.82 460 P 1.69 (, and less) 257.49 460 P 0.6 (accurate, delay and area metrics. Third, the CAD \337o) 54 450 P 0.6 (w we use to) 249.59 450 P 2.14 (e) 54 440 P 2.14 (v) 57.77 440 P 2.14 (aluate architectures emplo) 62.05 440 P 2.14 (ys a combined global and detailed) 160.7 440 P -0.09 (\050one-step\051 router) 54 430 P -0.09 (, while Bro) 113.78 430 P -0.09 (wn et al and Cho) 153.61 430 P -0.09 (w et al performed glo-) 214.01 430 P 0.44 (bal and detailed routing in tw) 54 420 P 0.44 (o steps. Since the global router in a) 161.86 420 P 1.5 (tw) 54 410 P 1.5 (o-step routing is una) 62.91 410 P 1.5 (w) 141.03 410 P 1.5 (are of the distrib) 147.44 410 P 1.5 (ution of wire se) 211.01 410 P 1.5 (gment) 271.62 410 P 1.36 (lengths, and hence not attempting to optimize for it, long wires) 54 400 P 0.53 (may not be used as ef) 54 390 P 0.53 (fecti) 134.14 390 P 0.53 (v) 149.91 390 P 0.53 (ely as possible. Finally) 154.28 390 P 0.53 (, the router we) 240.55 390 P 1.6 (use in this study is fully timing-dri) 54 380 P 1.6 (v) 187.87 380 P 1.6 (en \050uses timing analysis to) 192.23 380 P 0.3 (determine which connections need high speed routing\051 allo) 54 370 P 0.3 (wing it) 268.57 370 P 0.4 (to more fully e) 54 360 P 0.4 (xploit the intrinsic speed of dif) 108.31 360 P 0.4 (ferent routing archi-) 220.84 360 P 1.96 (tectures, and hence impro) 54 350 P 1.96 (ving the accurac) 152.23 350 P 1.96 (y of our architecture) 215 350 P (comparisons.) 54 340 T 0.06 (The or) 72 326 P 0.06 (g) 95.64 326 P 0.06 (anization of this paper is as follo) 100.1 326 P 0.06 (ws. The ne) 217.75 326 P 0.06 (xt section) 259.3 326 P 54 470/G1005873 FmPA 1.49 (describes the portions of the FPGA architecture which are held) 54 316 P 0.4 (constant throughout the e) 54 306 P 0.4 (xperiments of this paper) 146.31 306 P 0.4 (. Section 3 then) 234.26 306 P 0.67 (outlines the e) 54 296 P 0.67 (xperimental frame) 103.2 296 P 0.67 (w) 169.88 296 P 0.67 (ork we use to compare dif) 176.28 296 P 0.67 (ferent) 273.13 296 P 1.43 (FPGA routing architectures. In Section 4, we perform e) 54 286 P 1.43 (xperi-) 272.63 286 P 1.38 (ments to determine which length of wire se) 54 276 P 1.38 (gment results in the) 219.24 276 P 1.6 (best speed and area-ef) 54 266 P 1.6 (\336cienc) 138.3 266 P 1.6 (y when all the routing wires in an) 162.16 266 P 0.62 (FPGA ha) 54 256 P 0.62 (v) 88.19 256 P 0.62 (e the same length, and all routing switches are tri-state) 92.56 256 P 0.6 (b) 54 246 P 0.6 (uf) 58.32 246 P 0.6 (fers. In Section 5 we in) 65.59 246 P 0.6 (v) 154.56 246 P 0.6 (estig) 158.93 246 P 0.6 (ate more comple) 175.88 246 P 0.6 (x routing archi-) 236.93 246 P 0.34 (tectures that contain wire se) 54 236 P 0.34 (gments of tw) 155.69 236 P 0.34 (o dif) 203.27 236 P 0.34 (ferent lengths, and a) 220.13 236 P -0.12 (mix of pass transistor and tri-state b) 54 226 P -0.12 (uf) 182.09 226 P -0.12 (fer routing switches. Section) 189.36 226 P -0.04 (6 compares some of the best architectures we ha) 54 216 P -0.04 (v) 227.44 216 P -0.04 (e found to a rout-) 231.8 216 P 0.29 (ing architecture similar to that of the Xilinx 4000X series FPGAs.) 54 206 P (Finally) 54 196 T (, we summarize our results and conclusions.) 78.92 196 T 2 12 Q (2) 54 172 T (FPGA Ar) 72 172 T (chitectur) 121.44 172 T (e and Cir) 167.21 172 T (cuit Design) 214.99 172 T 54 316/G1005991 FmPA (P) 72 158 T (arameters Held Constant) 79.21 158 T 1 9 Q 0.99 (In this paper we are in) 72 142 P 0.99 (v) 156.83 142 P 0.99 (estig) 161.19 142 P 0.99 (ating dif) 178.15 142 P 0.99 (ferent routing architec-) 209.16 142 P 54 286/G1005992 FmPA 1.22 (tures, so we hold the other architectural parameters, such as the) 54 132 P 0.58 (logic block used, constant throughout the e) 54 122 P 0.58 (xperiments. In all our) 212.07 122 P 0.42 (e) 54 112 P 0.42 (xperiments, each channel in an FPGA contains the same number) 57.86 112 P (of tracks and has the same se) 54 102 T (gmentation distrib) 158.34 102 T (ution.) 223.91 102 T 1.23 (The logic block of all the FPGAs studied in this w) 72 88 P 1.23 (ork is a) 265.17 88 P 54 232/G1007611 FmPA 0.13 (logic cluster [19] of four 4-input look-up tables \0504-LUTs\051 and re) 54 78 P 0.13 (g-) 286.62 78 P 1.58 (isters, with ten inputs, four outputs, and one clock. This logic) 317.88 714 P 0.33 (block includes local routing that allo) 317.88 704 P 0.33 (ws each of the LUT inputs to) 451.04 704 P 0.17 (be connected to an) 317.88 694 P 0.17 (y of the 10 logic block inputs or an) 385.5 694 P 0.17 (y of the four) 512.74 694 P -0.22 (outputs generated within the logic block.) 317.88 684 P 1 7.2 Q -0.18 (1) 463.75 687.6 P 1 9 Q -0.22 ( This logic block is more) 467.35 684 P 0.52 (typical of the size of current commercial FPGA logic blocks than) 317.88 674 P 0.01 (the single 4-LUT logic block assumed by most prior routing archi-) 317.88 664 P 0.07 (tecture research, and prior research has sho) 317.88 654 P 0.07 (wn that this logic block) 473.24 654 P 0.94 (leads to an area-ef) 317.88 644 P 0.94 (\336cient FPGA [19]. The input and output pins) 386.2 644 P 1.97 (are e) 317.88 634 P 1.97 (v) 336.86 634 P 1.97 (enly distrib) 341.22 634 P 1.97 (uted around the perimeter of the logic block,) 383.76 634 P (since [20] sho) 317.88 624 T (wed that this pin positioning is best.) 368.14 624 T 0.57 (The number of I/O pads that \336t into the height or width of a) 335.88 610 P 318 754/G1007618 FmPA 0.15 (logic block is set to four) 317.88 600 P 0.15 (, in line with the relati) 405.52 600 P 0.15 (v) 485.55 600 P 0.15 (e sizes of pads and) 489.91 600 P -0.17 (4-LUTs of current FPGAs [3, 4, 5, 21]. W) 317.88 590 P -0.17 (ith this assumption three) 470.24 590 P 0.04 (of the twenty benchmark circuits we use \050bigk) 317.88 580 P 0.04 (e) 484.82 580 P 0.04 (y) 488.68 580 P 0.04 (, des and dsip\051 are) 492.59 580 P 1.13 (pad-limited. W) 317.88 570 P 1.13 (e al) 376.17 570 P 1.13 (w) 389.95 570 P 1.13 (ays map each circuit to the smallest square) 396.36 570 P 0.22 (logic block array that has enough logic blocks and pads to accom-) 317.88 560 P 0.81 (modate it. Since commercial FPGAs normally distrib) 317.88 550 P 0.81 (ute the cir-) 517.39 550 P 0.12 (cuit clock through a special, dedicated routing resource, we do not) 317.88 540 P (route the clock net in sequential circuits.) 317.88 530 T 0.7 (The switch block topology [8] \050which de\336nes which routing) 335.88 516 P 318 660/G1006071 FmPA 0.28 (wire se) 317.88 506 P 0.28 (gments can connect via routing switches at the intersection) 343.77 506 P 0.38 (of a horizontal and v) 317.88 496 P 0.38 (ertical channel\051 used throughout this paper is) 393.75 496 P 0.06 (the) 317.88 486 P 3 F 0.06 (disjoint) 331.19 486 P 1 F 0.06 ( switch block topology used in the original Xilinx 4000) 358.2 486 P 0.41 (series FPGAs [22]. In this switch block, a wire in track number) 317.88 476 P 3 F 0.41 (i) 555.5 476 P 1 F 1.51 (can connect only to other wires in track) 317.88 466 P 3 F 1.51 (i) 474.44 466 P 1 F 1.51 (. Note that with this) 476.94 466 P 1.52 (switch block wires of a gi) 317.88 456 P 1.52 (v) 418.01 456 P 1.52 (en length can only connect to other) 422.38 456 P 0.77 (wires of the same length. Interestingly) 317.88 446 P 0.77 (, while the disjoint switch) 462.16 446 P 0.07 (block topology is not as routable as the W) 317.88 436 P 0.07 (ilton switch block topol-) 469.54 436 P 0.1 (ogy in FPGAs where all routing wire se) 317.88 426 P 0.1 (gments ha) 461.68 426 P 0.1 (v) 498.35 426 P 0.1 (e length 1 [11],) 502.71 426 P 1.34 (we ha) 317.88 416 P 1.34 (v) 340.28 416 P 1.34 (e found that it results in better speed and area-ef) 344.64 416 P 1.34 (\336cienc) 529.64 416 P 1.34 (y) 553.5 416 P 0.04 (than a straightforw) 317.88 406 P 0.04 (ard generalization of the W) 385.86 406 P 0.04 (ilton switch block in) 484.12 406 P 1.44 (FPGAs that contain longer wires [6, 7]. Pre) 317.88 396 P 1.44 (vious switch block) 487.63 396 P -0.04 (research has focused e) 317.88 386 P -0.04 (xclusi) 398.33 386 P -0.04 (v) 419.6 386 P -0.04 (ely on FPGAs containing only length) 423.97 386 P 2.04 (1 wire se) 317.88 376 P 2.04 (gments; clearly future research should in) 354.32 376 P 2.04 (v) 510.89 376 P 2.04 (estig) 515.26 376 P 2.04 (ate the) 532.22 376 P 3.16 (interplay between se) 317.88 366 P 3.16 (gmentation distrib) 398.04 366 P 3.16 (ution and switch block) 466.78 366 P (topology) 317.88 356 T (.) 349.3 356 T -0.12 (W) 335.88 342 P -0.12 (e set the number of routing tracks to which each logic block) 343.66 342 P 318 486/G1006104 FmPA -0.07 (pin can connect, F) 317.88 332 P 1 7.2 Q -0.06 (c) 383.65 329.75 P 1 9 Q -0.07 ( [8], to 0.5W) 386.84 332 P -0.07 (, where W is the number of routing) 432.04 332 P 1.34 (tracks in a channel. Our e) 317.88 320.35 P 1.34 (xperiments ha) 420.01 320.35 P 1.34 (v) 471.91 320.35 P 1.34 (e sho) 476.27 320.35 P 1.34 (wn that this is a) 496.14 320.35 P (good v) 317.88 310.35 T (alue for a wide range of routing architectures.) 342.4 310.35 T -0.22 (The size of the transistors used in the routing switches is a k) 335.88 296.35 P -0.22 (e) 549.64 296.35 P -0.22 (y) 553.5 296.35 P 318 440/G1006019 FmPA 0.81 (architectural issue. The metal capacitance of a routing wire se) 317.88 286.35 P 0.81 (g-) 550.5 286.35 P 2.17 (ment is quite lar) 317.88 276.35 P 2.17 (ge, so signi\336cant speed impro) 382.49 276.35 P 2.17 (v) 498.3 276.35 P 2.17 (ements can be) 502.67 276.35 P -0.2 (achie) 317.88 266.35 P -0.2 (v) 336.64 266.35 P -0.2 (ed by increasing the size of the transistors forming pass tran-) 341.01 266.35 P 0.12 (sistor or tri-state b) 317.88 256.35 P 0.12 (uf) 383.82 256.35 P 0.12 (fer routing switches. At some point, ho) 391.09 256.35 P 0.12 (we) 534.48 256.35 P 0.12 (v) 544.75 256.35 P 0.12 (er) 549.12 256.35 P 0.12 (,) 555.75 256.35 P 1.1 (one achie) 317.88 246.35 P 1.1 (v) 352.99 246.35 P 1.1 (es diminishing speed returns as the size of the switch) 357.36 246.35 P 1.3 (transistors is increased, since the parasitic capacitance added by) 317.88 236.35 P 0.52 (these switches becomes comparable to the metal capacitance. As) 317.88 226.35 P 0.68 (well, increasing the size of the routing switch transistors requires) 317.88 216.35 P -0.07 (more layout area. Essentially we w) 317.88 206.35 P -0.07 (ant to choose the transistor size) 445.61 206.35 P 1.08 (that achie) 317.88 196.35 P 1.08 (v) 353.47 196.35 P 1.08 (es the best trade-of) 357.84 196.35 P 1.08 (f between the speed of the routing) 429.07 196.35 P 1.18 (and the area required. W) 317.88 186.35 P 1.18 (e belie) 414.03 186.35 P 1.18 (v) 438.73 186.35 P 1.18 (e that the best trade-of) 443.1 186.35 P 1.18 (f occurs) 528.08 186.35 P 1.44 (when the transistor sizes are chosen to minimize the area-delay) 317.88 176.35 P 0.06 (product of the resulting routing resources. W) 317.88 166.35 P 0.06 (e e) 481.55 166.35 P 0.06 (v) 491.62 166.35 P 0.06 (aluated the speed) 495.9 166.35 P 2.8 (of FPGA routing structures using dif) 317.88 156.35 P 2.8 (ferent transistor sizes in) 463.88 156.35 P 0.87 (TSMC\325) 317.88 146.35 P 0.87 (s 0.35) 344.89 146.35 P 4 F 0.87 (m) 370.38 146.35 P 1 F 0.87 (m, three-le) 375.56 146.35 P 0.87 (v) 415.19 146.35 P 0.87 (el metal CMOS process [23], and we) 419.56 146.35 P 0.74 (used the area model described in Section 3.3 to e) 317.88 136.35 P 0.74 (v) 500.27 136.35 P 0.74 (aluate the area) 504.55 136.35 P 1.12 (required. W) 317.88 126.35 P 1.12 (e found that for a v) 364.63 126.35 P 1.12 (ery wide range of wire se) 438.83 126.35 P 1.12 (gment) 535.5 126.35 P 317.88 112 558 119.5 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 318.38 117.5 470.88 117.5 2 L 0.5 H 2 Z 0 X 0 0 0 1 0 0 0 K N 0 0 612 792 C 1 9 Q 0 X 0 0 0 1 0 0 0 K (1.) 317.88 106 T -0.09 (Since this local routing is part of the logic block, and not part of) 328.68 106 P 318 250/G1008175 FmPA 1.26 (the \322general\323 FPGA routing, we count its area as part of the) 328.68 96 P -0.22 (logic block area, rather than as part of the FPGA routing area, in) 328.68 86 P (the later sections.) 328.68 76 T 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.2/DEST FmPD2 [/Rect[104 75 113 85]/Border[0 0 0]/Page 10/View[/XYZ null 338 838 FmDC exch pop null]/LNK FmPD [/Rect[441 641 450 651]/Border[0 0 0]/Page 10/View[/XYZ null 338 838 FmDC exch pop null]/LNK FmPD [/Rect[342 621 351 631]/Border[0 0 0]/Page 10/View[/XYZ null 338 805 FmDC exch pop null]/LNK FmPD [/Rect[440 513 445 523]/Border[0 0 0]/Page 10/View[/XYZ null 74 587 FmDC exch pop null]/LNK FmPD [/Rect[417 587 422 597]/Border[0 0 0]/Page 10/View[/XYZ null 74 702 FmDC exch pop null]/LNK FmPD [/Rect[426 587 431 597]/Border[0 0 0]/Page 10/View[/XYZ null 74 689 FmDC exch pop null]/LNK FmPD [/Rect[444 587 453 597]/Border[0 0 0]/Page 10/View[/XYZ null 338 772 FmDC exch pop null]/LNK FmPD [/Rect[373 473 382 483]/Border[0 0 0]/Page 10/View[/XYZ null 338 759 FmDC exch pop null]/LNK FmPD [/Rect[544 423 553 433]/Border[0 0 0]/Page 10/View[/XYZ null 74 488 FmDC exch pop null]/LNK FmPD [/Rect[448 393 453 403]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[392 327 397 339]/Border[0 0 0]/Page 10/View[/XYZ null 74 587 FmDC exch pop null]/LNK FmPD [/Rect[514 142 523 153]/Border[0 0 0]/Page 10/View[/XYZ null 338 726 FmDC exch pop null]/LNK FmPD [/Rect[242 303 276 313]/Border[0 0 0]/Page 3/View[/XYZ null 72 462 FmDC exch pop null]/LNK FmPD [/Rect[181 283 216 293]/Border[0 0 0]/Page 4/View[/XYZ null 336 292 FmDC exch pop null]/LNK FmPD [/Rect[97 243 132 253]/Border[0 0 0]/Page 6/View[/XYZ null 72 864 FmDC exch pop null]/LNK FmPD [/Rect[267 223 294 233]/Border[0 0 0]/Page 7/View[/XYZ null 336 283 FmDC exch pop null]/LNK FmPD [/Rect[54 213 59 223]/Border[0 0 0]/Page 7/View[/XYZ null 336 283 FmDC exch pop null]/LNK FmPD [/Rect[435 587 439 597]/Border[0 0 0]/Page 10/View[/XYZ null 74 676 FmDC exch pop null]/LNK FmPD [/Rect[442 133 484 143]/Border[0 0 0]/Page 4/View[/XYZ null 76 355 FmDC exch pop null]/LNK FmPD [/Rect[459 393 463 403]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[166 617 171 627]/Border[0 0 0]/Page 10/View[/XYZ null 74 587 FmDC exch pop null]/LNK FmPD [/Rect[175 617 180 627]/Border[0 0 0]/Page 10/View[/XYZ null 74 554 FmDC exch pop null]/LNK FmPD [/Rect[184 617 193 627]/Border[0 0 0]/Page 10/View[/XYZ null 74 521 FmDC exch pop null]/LNK FmPD [/Rect[198 617 207 627]/Border[0 0 0]/Page 10/View[/XYZ null 74 488 FmDC exch pop null]/LNK FmPD [/Rect[190 567 199 577]/Border[0 0 0]/Page 10/View[/XYZ null 74 435 FmDC exch pop null]/LNK FmPD [/Rect[203 567 212 577]/Border[0 0 0]/Page 10/View[/XYZ null 74 402 FmDC exch pop null]/LNK FmPD [/Rect[216 567 225 577]/Border[0 0 0]/Page 10/View[/XYZ null 74 369 FmDC exch pop null]/LNK FmPD [/Rect[230 567 239 577]/Border[0 0 0]/Page 10/View[/XYZ null 74 346 FmDC exch pop null]/LNK FmPD [/Rect[103 537 112 547]/Border[0 0 0]/Page 10/View[/XYZ null 74 313 FmDC exch pop null]/LNK FmPD [/Rect[118 537 127 547]/Border[0 0 0]/Page 10/View[/XYZ null 74 270 FmDC exch pop null]/LNK FmPD [/Rect[195 537 204 547]/Border[0 0 0]/Page 10/View[/XYZ null 74 237 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 63 567 729]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "2" 2 %%Page: "3" 3 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 1 9 Q 0 X 0 0 0 1 0 0 0 K 2.16 (lengths, pass transistor routing switches achie) 54 607.84 P 2.16 (v) 229.05 607.84 P 2.16 (e the best area-) 233.42 607.84 P 1.23 (delay product when the) 54 597.84 P 1.23 (y are ten times as wide as the minimum) 141.79 597.84 P 0.82 (contactable transistor width. Similarly) 54 587.84 P 0.82 (, we found that for a wide) 196.45 587.84 P 0.52 (range of wire se) 54 577.84 P 0.52 (gment lengths the tri-state routing b) 113.15 577.84 P 0.52 (uf) 244.32 577.84 P 0.52 (fer with the) 251.59 577.84 P 0.39 (best area-delay product is the tw) 54 567.84 P 0.39 (o-stage b) 172.57 567.84 P 0.39 (uf) 205.53 567.84 P 0.39 (fer sho) 212.8 567.84 P 0.39 (wn in Figure 2;) 237.7 567.84 P 0.71 (its output stage has \336v) 54 557.84 P 0.71 (e times the minimum dri) 137.22 557.84 P 0.71 (v) 228.35 557.84 P 0.71 (e strength. Note) 232.72 557.84 P 1.17 (that the transistor widths in Figure 2 are all in \322times minimum) 54 547.84 P 2.15 (contactable width\323 rather than in microns. F) 54 537.84 P 2.15 (or details on the) 229.91 537.84 P 0.22 (e) 54 527.83 P 0.22 (xperiments we performed to determine these best routing transis-) 57.86 527.83 P (tor sizes, see [6, 7].) 54 517.83 T 0.1 (Finally) 72 503.83 P 0.1 (, we ha) 96.92 503.83 P 0.1 (v) 122.69 503.83 P 0.1 (e to choose the metal width, spacing and layer) 127.06 503.83 P 54 648/G1006130 FmPA 1.51 (in which routing wires are laid out. Throughout this paper we) 54 493.83 P 0.79 (assume routing wires are laid out in metal 3; we ha) 54 483.83 P 0.79 (v) 245.18 483.83 P 0.79 (e found that) 249.55 483.83 P 0.22 (our results do not change signi\336cantly if routing wires are laid out) 54 473.83 P 0.66 (in metal 1 or 2, ho) 54 463.83 P 0.66 (we) 123.08 463.83 P 0.66 (v) 133.35 463.83 P 0.66 (er) 137.72 463.83 P 0.66 (. W) 144.21 463.83 P 0.66 (e also use minimum-width metal for) 160.07 463.83 P 1.19 (all routing wires. While increasing the metal width reduces the) 54 453.83 P 0.12 (metal resistance, it also increases the metal capacitance. Since the) 54 443.83 P 0.18 (resistance of a routing switch is considerably lar) 54 433.83 P 0.18 (ger than the metal) 228.84 433.83 P 2.23 (resistance of e) 54 423.83 P 2.23 (v) 109.71 423.83 P 2.23 (en f) 114.08 423.83 P 2.23 (airly long routing wire se) 129.96 423.83 P 2.23 (gments, we ha) 229.74 423.83 P 2.23 (v) 285.76 423.83 P 2.23 (e) 290.12 423.83 P 1.28 (found that the net ef) 54 413.83 P 1.28 (fect of wider metal wires is to increase the) 131.39 413.83 P -0.2 (routing delay) 54 403.83 P -0.2 (. Throughout this paper we also assume routing wires) 100.96 403.83 P 0.56 (use the minimum metal spacing; this results in the highest wiring) 54 393.83 P 0.34 (density during layout, at the cost of higher metal capacitance than) 54 383.83 P 0.47 (wider metal spacings w) 54 373.83 P 0.47 (ould yield. W) 140.06 373.83 P 0.47 (e ha) 192.26 373.83 P 0.47 (v) 207.29 373.83 P 0.47 (e also run man) 211.66 373.83 P 0.47 (y of the) 265.68 373.83 P 2.05 (e) 54 363.83 P 2.05 (xperiments in this paper with wider metal spacings, ho) 57.86 363.83 P 2.05 (we) 270.74 363.83 P 2.05 (v) 281.01 363.83 P 2.05 (er) 285.37 363.83 P 2.05 (.) 291.87 363.83 P 1.78 (While this increases the speed of) 54 353.83 P 3 F 1.78 (e) 185.18 353.83 P 1.78 (very) 189.04 353.83 P 1 F 1.78 ( FPGA architecture \050by) 204.53 353.83 P 1.31 (about 15%\051, it does not change an) 54 343.83 P 1.31 (y of our architectural conclu-) 183.93 343.83 P (sions.) 54 333.83 T 2 12 Q (3) 54 309.83 T (Experimental Methodology) 72 309.83 T 54 454/G999594 FmPA 1 9 Q 3.88 (W) 72 293.83 P 3.88 (e e) 79.78 293.83 P 3.88 (xplore dif) 93.76 293.83 P 3.88 (ferent architectures by implementing the) 132.65 293.83 P 54 438/G999609 FmPA 1.54 (twenty lar) 54 283.83 P 1.54 (gest MCNC benchmark circuits [24] into each FPGA) 91.62 283.83 P 0.47 (architecture of interest. These circuits range in size from 1064 to) 54 273.84 P 0.01 (8381 4-LUTs. W) 54 263.84 P 0.01 (e implement each circuit with an automatic CAD) 117.31 263.84 P 0.23 (\337o) 54 253.84 P 0.23 (w similar to that used by FPGA users: technology-independent) 63.28 253.84 P 1.63 (logic optimization, technology-mapping, placement and routing.) 54 243.84 P 0.53 (W) 54 233.84 P 0.53 (e then compare the circuit delay achie) 61.78 233.84 P 0.53 (v) 201.18 233.84 P 0.53 (ed and the area required) 205.54 233.84 P (by each architecture.) 54 223.84 T 2 11 Q (3.1) 54 201.5 T (CAD Flo) 75.6 201.5 T (w) 117.35 201.5 T 54 346/G999657 FmPA 1 9 Q 0.58 (Figure 3 illustrates the CAD \337o) 72 185.84 P 0.58 (w we use to e) 188.43 185.84 P 0.58 (v) 239.52 185.84 P 0.58 (aluate routing) 243.79 185.84 P 54 330/G999658 FmPA 0.35 (architectures. First, SIS [25] is used to optimize the logic of each) 54 175.84 P 0.71 (circuit. Ne) 54 165.84 P 0.71 (xt, we use Flo) 95.52 165.84 P 0.71 (wmap [26] to technology map each cir-) 147.91 165.84 P 0.33 (cuit into 4-LUTs and re) 54 155.84 P 0.33 (gisters, and Flo) 140.15 155.84 P 0.33 (wpack [26] to optimize the) 195.83 155.84 P 1.11 (mapping and reduce the number of LUTs required. VP) 54 145.84 P 1.11 (ack [27]) 263.28 145.84 P 1.33 (then groups these 4-LUTs and re) 54 135.84 P 1.33 (gisters into logic blocks of the) 178.73 135.84 P 0.12 (desired size \050clusters of at most four LUTs, using no more than 10) 54 125.84 P 0.59 (distinct inputs\051. V) 54 115.84 P 0.59 (ersatile Place and Route \050VPR\051 then places the) 121.77 115.84 P 0.45 (circuit [28], and the VPR timing-dri) 54 105.84 P 0.45 (v) 185.53 105.84 P 0.45 (en router [6, 7] is repeatedly) 189.89 105.84 P 1.25 (in) 54 95.84 P 1.25 (v) 60.64 95.84 P 1.25 (ok) 64.96 95.84 P 1.25 (ed with dif) 73.87 95.84 P 1.25 (ferent channel capacities to determine the mini-) 115.15 95.84 P -0.21 (mum number of tracks per channel, W) 54 85.84 P 1 7.2 Q -0.17 (min) 191.48 83.59 P 1 9 Q -0.21 (, required to route the cir-) 202.68 85.84 P 1.83 (cuit. FPGA manuf) 317.88 443.76 P 1.83 (acturers normally b) 391.78 443.76 P 1.83 (uild enough routing into) 465.25 443.76 P 0.05 (their FPGAs that \322a) 317.88 433.76 P 0.05 (v) 389.1 433.76 P 0.05 (erage\323 circuits ha) 393.46 433.76 P 0.05 (v) 456.36 433.76 P 0.05 (e some spare routing a) 460.72 433.76 P 0.05 (v) 541.73 433.76 P 0.05 (ail-) 546 433.76 P 0.33 (able. W) 317.88 423.76 P 0.33 (e model this by performing a \336nal \322lo) 348.05 423.76 P 0.33 (w-stress\323 routing of) 485.86 423.76 P 0.04 (each circuit with the number of tracks per channel set to 1.2) 317.88 413.76 P 4 F 0.04 (\327) 533.8 413.76 P 1 F 0.04 (W) 536.05 413.76 P 1 7.2 Q 0.03 (min) 544.55 411.51 P 1 9 Q 0.04 (.) 555.75 413.76 P 1.09 (Our delay model then estimates the circuit critical path, and our) 317.88 402.11 P 0.45 (area model estimates the total transistor area needed to lay out all) 317.88 392.11 P 0.58 (the routing in this FPGA. At the end of this CAD \337o) 317.88 382.11 P 0.58 (w) 515.93 382.11 P 0.58 (, then, we) 521.84 382.11 P 0.45 (ha) 317.88 372.11 P 0.45 (v) 326.2 372.11 P 0.45 (e enough information to compare both the speed and the area-) 330.56 372.11 P (ef) 317.88 362.11 T (\336cienc) 324.65 362.11 T (y of one architecture to another) 348.51 362.11 T (.) 460.73 362.11 T 3 10 Q (3.1.1 Overvie) 317.88 340.44 T (w of T) 371.88 340.44 T (iming-Driven Routing Algorithm) 396.34 340.44 T 318 484/G1006349 FmPA 1 9 Q -0.11 (Since we are comparing the speed and area of dif) 335.88 325.11 P -0.11 (ferent FPGA) 511.87 325.11 P 318 469/G1006341 FmPA 1.71 (routing architectures, the most important tool in the CAD \337o) 317.88 315.11 P 1.71 (w) 551.5 315.11 P 0.25 (abo) 317.88 305.11 P 0.25 (v) 330.74 305.11 P 0.25 (e is the router) 335.11 305.11 P 0.25 (. T) 384.58 305.11 P 0.25 (o allo) 396.6 305.11 P 0.25 (w f) 416.87 305.11 P 0.25 (air comparisons of dif) 428.77 305.11 P 0.25 (ferent routing) 508.52 305.11 P 0.22 (architectures, we created a ne) 317.88 295.11 P 0.22 (w router that optimizes well for both) 424.72 295.11 P 1.41 (speed and routability) 317.88 285.11 P 1.41 (, and can fully e) 395.61 285.11 P 1.41 (xploit the features of each) 458.87 285.11 P (FPGA architecture we study) 317.88 275.11 T (.) 419.53 275.11 T 1.01 (Lik) 335.88 261.11 P 1.01 (e its purely routability-dri) 348.29 261.11 P 1.01 (v) 443.85 261.11 P 1.01 (en predecessor [28], the VPR) 448.22 261.11 P 318 405/G1006399 FmPA 1.42 (timing-dri) 317.88 251.11 P 1.42 (v) 354.16 251.11 P 1.42 (en router [6, 7] uses man) 358.52 251.11 P 1.42 (y ideas from the P) 454.97 251.11 P 1.42 (ath\336nder) 526.01 251.11 P 0.95 (routing algorithm [29]. It repeatedly rips-up and re-routes e) 317.88 241.11 P 0.95 (v) 542.14 241.11 P 0.95 (ery) 546.51 241.11 P 1.7 (net in the circuit, and gradually resolv) 317.88 231.11 P 1.7 (es routing congestion by) 464.66 231.11 P 0.56 (gradually increasing the cost of o) 317.88 221.11 P 0.56 (v) 440.27 221.11 P 0.56 (erused routing resources. Lik) 444.63 221.11 P 0.56 (e) 554 221.11 P 0.05 (P) 317.88 211.11 P 0.05 (ath\336nder) 322.75 211.11 P 0.05 (, it also performs timing analysis repeatedly during rout-) 354.38 211.11 P -0.17 (ing, and uses the slack of each connection to determine the conges-) 317.88 201.11 P 2.83 (tion a) 317.88 191.11 P 2.83 (v) 340.78 191.11 P 2.83 (oidance / delay minimization trade-of) 345.1 191.11 P 2.83 (f to use for that) 491.68 191.11 P 0.47 (connection. The VPR timing-dri) 317.88 181.11 P 0.47 (v) 438.27 181.11 P 0.47 (en router contains some signi\336-) 442.64 181.11 P 0.8 (cant ne) 317.88 171.11 P 0.8 (w features, ho) 344.2 171.11 P 0.8 (we) 396.31 171.11 P 0.8 (v) 406.58 171.11 P 0.8 (er) 410.95 171.11 P 0.8 (. The most important enhancement is) 417.44 171.11 P -0.15 (that this router directly optimizes the Elmore delay [30] as it routes) 317.88 161.11 P 0.01 (each connection. The router uses the Elmore delay to guide it as it) 317.88 151.11 P 1.69 (selects the net topology) 317.88 141.11 P 1.69 (, wire se) 407.1 141.11 P 1.69 (gment lengths, and the type of) 440.58 141.11 P 0.17 (switch \050pass transistor or tri-state b) 317.88 131.11 P 0.17 (uf) 444.77 131.11 P 0.17 (fer\051 used to connect tw) 452.04 131.11 P 0.17 (o wire) 535.09 131.11 P -0.16 (se) 317.88 121.11 P -0.16 (gments. Note also that it mak) 325.24 121.11 P -0.16 (es all these decisions in one uni\336ed) 431.95 121.11 P 2.25 (step, since the limited \337e) 317.88 111.11 P 2.25 (xibility of FPGA routing means that) 416.49 111.11 P 1.37 (topology) 317.88 101.11 P 1.37 (, wire se) 349.3 101.11 P 1.37 (gment length and switch type decisions are all) 382.15 101.11 P 0.62 (coupled. Pre) 317.88 91.11 P 0.62 (vious academic FPGA routers ha) 366.13 91.11 P 0.62 (v) 487.41 91.11 P 0.62 (e optimized either) 491.77 91.11 P 0.84 (only wirelength or the linear delay model, in which each routing) 317.88 81.11 P 54 72 294.12 720 C 54 613.83 294.12 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 180.74 678.82 190.46 678.82 2 L 0.5 H 2 Z 0 X 0 0 0 1 0 0 0 K N 190.46 673.63 190.46 683.69 2 L N 195.92 668.42 195.92 673.65 192.63 673.65 192.63 683.72 195.92 683.72 195.92 688.76 6 L N 180.74 699.19 187.24 699.19 2 L N 190.56 693.95 190.56 704.01 2 L N 195.82 712.24 193.25 712.24 195.82 716.69 198.39 712.24 4 Y 0 Z N 195.82 712.24 193.25 712.24 195.82 716.69 198.39 712.24 4 Y V 195.82 688.8 195.82 694.03 192.53 694.03 192.53 704.09 195.82 704.09 195.82 711.99 6 L N 2 Z 90 450 1.71 1.83 188.93 699.25 A 180.79 699.15 180.79 678.73 2 L 0 Z N 193.25 663.54 198.72 663.54 2 L 1 Z N 190.52 665.85 201.45 665.85 2 L N 187.79 668.16 204.18 668.16 2 L N 1 9 Q (1) 196.21 675.81 T (1.9) 194.4 696.52 T (In) 164.16 687.93 T J 181.02 689.82 172.23 689.82 2 L 0 Z N 90 450 0.88 0.94 180.78 689.88 G 90 450 0.88 0.94 180.78 689.88 A 215.69 688.62 196.87 688.62 2 L N 90 450 1.07 1.14 195.9 688.69 G 90 450 1.07 1.14 195.9 688.69 A 215.35 676.91 227.16 676.91 2 L 2 Z N 227.16 670.62 227.16 682.81 2 L N 233.7 666.22 233.7 670.86 229.7 670.86 229.7 682.93 233.7 682.93 233.7 688.96 6 L N 215.35 701.59 223.24 701.59 2 L N 227.28 695.24 227.28 707.43 2 L N 233.62 714.42 231.05 714.42 233.62 718.86 236.18 714.42 4 Y 0 Z N 233.62 714.42 231.05 714.42 233.62 718.86 236.18 714.42 4 Y V 233.62 688.99 233.62 695.32 229.62 695.32 229.62 707.53 233.62 707.53 233.62 714.17 6 L N 2 Z 90 450 1.75 1.87 225.43 702.02 A 215.41 701.54 215.41 676.8 2 L 0 Z N 230.55 660.64 237.18 660.64 2 L 1 Z N 227.23 663.44 240.5 663.44 2 L N 223.91 666.23 243.82 666.23 2 L N (5) 232.22 673.97 T (9.5) 232.21 698.24 T J 90 450 1.07 1.14 215.4 688.69 G 0 Z 90 450 1.07 1.14 215.4 688.69 A 90 450 1.07 1.14 233.64 688.51 G 90 450 1.07 1.14 233.64 688.51 A (Out) 279.7 686.3 T 268.35 695.23 255.64 695.23 2 L 2 Z N 274.83 688.43 268.19 688.43 268.19 692.45 255.4 692.45 255.4 688.43 234.62 688.43 6 L N (5) 258.9 684.23 T 262 704 262 695.37 2 L N 246.63 704 276.26 718.86 R N (SRAM) 249.1 708.4 T 86.75 688.62 116.3 703.05 R N (SRAM) 88.96 692.96 T 101.72 688.62 101.72 678.66 2 L N 91.14 678.66 111.64 678.66 2 L N 80.7 667.33 91.41 667.33 91.41 674.05 112.04 674.05 112.04 667.33 122.35 667.33 6 L N (\050a\051 P) 74.09 652.29 T (ass transistor) 91.2 652.29 T (10) 97.43 665.03 T (In/Out) 55.53 665.09 T (In/Out) 125.59 665.09 T (\050b\051 T) 193.69 649.38 T (ri-state b) 211.62 649.38 T (uf) 243.18 649.38 T (fer) 250.45 649.38 T 2 F (Figur) 66.5 631.5 T (e 2:) 87.84 631.5 T 1 F ( T) 101.58 631.5 T (ransistor widths used to b) 111.27 631.5 T (uild routing switches.) 203.08 631.5 T 53 775/G1006228 FmPA 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 54 72 294.12 720 C 0 0 612 792 C 317.88 72 558 720 C 317.88 449.76 558 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 404.53 667.11 511.7 700.41 R 0.5 H 0 Z 0 X 0 0 0 1 0 0 0 K N 417.92 612.22 499.07 624.19 R N 391.05 588.47 531.2 602 R N 458.85 580.2 436.64 563.58 458.37 547.32 480.53 563.91 4 Y N 458.86 584.45 461.42 584.45 458.86 580 456.29 584.45 4 Y N 458.86 584.45 461.42 584.45 458.86 580 456.29 584.45 4 Y V 458.86 588.5 458.86 584.7 2 L 2 Z N 458.25 541.45 460.81 541.45 458.25 537 455.68 541.45 4 Y 0 Z N 458.25 541.45 460.81 541.45 458.25 537 455.68 541.45 4 Y V 458.25 547.24 458.25 541.7 2 L 2 Z N 401.78 635.05 514.49 657.13 R 0 Z N 498.42 556.35 556.52 577.87 R N 458.55 662.45 461.11 662.45 458.55 658 455.98 662.45 4 Y N 458.55 662.45 461.11 662.45 458.55 658 455.98 662.45 4 Y V 458.55 666.67 458.55 662.7 2 L 7 X V 2 Z 0 X N 1 9 Q (Min #) 448.55 566.2 T (tracks?) 446.71 557.33 T 536.13 594.85 536.13 592.28 531.69 594.85 536.13 597.42 4 Y 0 Z N 536.13 594.85 536.13 592.28 531.69 594.85 536.13 597.42 4 Y V 543.82 578.37 543.82 594.85 536.38 594.85 3 L 2 Z N (Circuit) 446.85 712.94 T (Adjust channel) 500.88 569.23 T (capacities \050W\051) 501.7 560.54 T (Logic optimization \050SIS\051) 413.42 691.54 T (T) 408.37 681.18 T (echnology map to 4-LUTs) 413.23 681.18 T (P) 406.02 648.83 T (ack re) 410.89 648.83 T (gisters and LUTs into) 432.49 648.83 T (Placement \050VPR\051) 427.3 615.96 T (Routing \050VPR, timing-dri) 394.63 593.6 T (v) 487.17 593.6 T (en router\051) 491.53 593.6 T (No) 483.85 567.98 T (Y) 461.94 541.53 T (es) 467.54 541.53 T 5 F (\334) 477.29 541.53 T 1 F (W) 488.41 541.53 T 1 8 Q (min) 496.91 539.03 T 1 9 Q ( determined) 509.36 541.53 T 396.17 646.96 396.17 649.53 400.62 646.96 396.17 644.39 4 Y 0 Z N 396.17 646.96 396.17 649.53 400.62 646.96 396.17 644.39 4 Y V 395.92 646.96 377.88 646.96 2 L 2 Z N (\0504 LUTs, 10 inputs\051) 320.85 633.29 T (Logic block) 334.01 652.11 T (parameters) 334.8 643.16 T 385.54 595.62 385.54 598.19 389.98 595.62 385.54 593.05 4 Y 0 Z N 385.54 595.62 385.54 598.19 389.98 595.62 385.54 593.05 4 Y V 385.29 595.62 366.55 595.62 2 L 2 Z N (Routing) 333.29 596.21 T (architecture) 323.9 586.64 T 401.93 513.38 515.12 536.35 R 0 Z N (Routing with W = 1.2 W) 406.73 527.89 T 1 8 Q (min) 496.31 525.39 T 459.34 507.95 461.9 507.95 459.34 503.5 456.77 507.95 4 Y N 459.34 507.95 461.9 507.95 459.34 503.5 456.77 507.95 4 Y V 459.34 513.47 459.34 508.2 2 L 2 Z N 378.71 482.51 542.55 502.64 R 0 Z N 1 9 Q (Determine critical path delay and) 399.33 494.59 T 396.81 524.64 396.81 527.21 401.26 524.64 396.81 522.07 4 Y N 396.81 524.64 396.81 527.21 401.26 524.64 396.81 522.07 4 Y V 376.03 594.65 376.03 524.64 396.56 524.64 3 L 2 Z N 2 F (Figur) 366.11 467.13 T (e 3:) 387.45 467.13 T 1 F ( Architecture e) 401.19 467.13 T (v) 456.69 467.13 T (aluation \337o) 460.97 467.13 T (w) 501.49 467.13 T (.) 507.41 467.13 T 318 611/G999797 FmPA 458.55 705.45 461.11 705.45 458.55 701 455.98 705.45 4 Y 0 Z N 458.55 705.45 461.11 705.45 458.55 701 455.98 705.45 4 Y V 458.55 710 458.55 705.7 2 L N (\050Flo) 415.61 671.49 T (wMap + Flo) 430.39 671.49 T (wpack\051) 474.74 671.49 T (logic clusters \050VP) 418.45 639.16 T (ack\051) 482.81 639.16 T 458.55 628.95 461.11 628.95 458.55 624.5 455.98 628.95 4 Y N 458.55 628.95 461.11 628.95 458.55 624.5 455.98 628.95 4 Y V 458.55 635.33 458.55 629.2 2 L N 458.55 606.95 461.11 606.95 458.55 602.5 455.98 606.95 4 Y N 458.55 606.95 461.11 606.95 458.55 602.5 455.98 606.95 4 Y V 458.55 612 458.55 607.2 2 L N 493.6 564 493.6 566.57 498.05 564 493.6 561.43 4 Y N 493.6 564 493.6 566.57 498.05 564 493.6 561.43 4 Y V 479.88 564 493.35 564 2 L N (\050VPR, timing-dri) 406.07 517.5 T (v) 467.35 517.5 T (en router\051) 471.71 517.5 T (transistor area to b) 381.66 485.51 T (uild FPGA routing \050VPR\051) 448.22 485.51 T 317.88 72 558 720 C 0 0 612 792 C 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.3/DEST FmPD2 0 791.99 0.01 792 C 0 0 612 792 C 401 617/M9.14981.Figurefirst.Figure.71.Architecture.evaluation.flow FmPA 0 791.99 0.01 792 C 0 0 612 792 C 401 617/I1.999800 FmPA 72 462/M9.32255.Heading2.72.Experimental.Methodology FmPA 72 462/I1.1004381 FmPA 0 792 0.01 792 C 0 0 612 792 C 102 781/M9.25000.Figure.Figure.2.Transistor.widths.used.in.a.pass.transistor.and.b.tristate.buffer.routing.s FmPA 0 792 0.01 792 C 0 0 612 792 C 102 781/I1.1006230 FmPA [/Rect[105 515 109 525]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[238 103 242 113]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[147 173 156 183]/Border[0 0 0]/Page 10/View[/XYZ null 338 660 FmDC exch pop null]/LNK FmPD [/Rect[176 163 185 173]/Border[0 0 0]/Page 10/View[/XYZ null 338 627 FmDC exch pop null]/LNK FmPD [/Rect[225 153 234 163]/Border[0 0 0]/Page 10/View[/XYZ null 338 627 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 792 C 0 0 612 792 C [/Rect[72 183 103 193]/Border[0 0 0]/Page 3/View[/XYZ null 401 617 FmDC exch pop null]/LNK FmPD [/Rect[217 281 226 291]/Border[0 0 0]/Page 10/View[/XYZ null 338 693 FmDC exch pop null]/LNK FmPD [/Rect[399 248 403 258]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[409 248 414 258]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[114 515 118 525]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[261 565 292 575]/Border[0 0 0]/Page 3/View[/XYZ null 102 781 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[160 545 192 555]/Border[0 0 0]/Page 3/View[/XYZ null 102 781 FmDC exch pop null]/LNK FmPD [/Rect[282 143 291 153]/Border[0 0 0]/Page 10/View[/XYZ null 338 584 FmDC exch pop null]/LNK FmPD [/Rect[83 103 92 113]/Border[0 0 0]/Page 10/View[/XYZ null 338 551 FmDC exch pop null]/LNK FmPD [/Rect[228 103 233 113]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[509 258 518 268]/Border[0 0 0]/Page 10/View[/XYZ null 338 551 FmDC exch pop null]/LNK FmPD [/Rect[388 238 397 248]/Border[0 0 0]/Page 10/View[/XYZ null 338 518 FmDC exch pop null]/LNK FmPD [/Rect[505 158 514 168]/Border[0 0 0]/Page 10/View[/XYZ null 338 485 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 63 567 729]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "3" 3 %%Page: "4" 4 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 1 9 Q 0 X 0 0 0 1 0 0 0 K 0.44 (switch has a \336x) 54 714 P 0.44 (ed delay) 110.94 714 P 0.44 (.) 141.04 714 P 1 7.2 Q 0.35 (1) 143.29 717.6 P 1 9 Q 0.44 ( The delay of a pass transistor is highly) 146.89 714 P 0.21 (dependent on the topology of the net containing it, ho) 54 704 P 0.21 (we) 248.68 704 P 0.21 (v) 258.95 704 P 0.21 (er) 263.31 704 P 0.21 (, so by) 269.94 704 P 0.64 (optimizing the Elmore delay our router is able to mak) 54 694 P 0.64 (e better net) 252.86 694 P 1.88 (topology choices and determine when using a b) 54 684 P 1.88 (uf) 238.23 684 P 1.88 (fered routing) 245.5 684 P (switch is preferable to using a pass transistor) 54 674 T (.) 214.73 674 T 0.5 (This ne) 72 660 P 0.5 (w router requires only slightly \0506% on a) 99.02 660 P 0.5 (v) 246.03 660 P 0.5 (erage\051 more) 250.4 660 P 54 804/G1006420 FmPA 0.31 (tracks than the VPR routability-dri) 54 650 P 0.31 (v) 180.02 650 P 0.31 (en router to successfully route) 184.39 650 P 1.38 (circuits. Since the VPR routability-dri) 54 640 P 1.38 (v) 199.65 640 P 1.38 (en router requires fe) 204.01 640 P 1.38 (wer) 280.63 640 P 0.28 (tracks to successfully route a set of standard benchmarks than an) 54 630 P 0.28 (y) 289.62 630 P 1.08 (other router for which results are a) 54 620 P 1.08 (v) 184.77 620 P 1.08 (ailable [28], this implies the) 189.05 620 P 1.15 (ne) 54 610 P 1.15 (w timing-dri) 62.27 610 P 1.15 (v) 108.45 610 P 1.15 (en router optimizes for routability v) 112.82 610 P 1.15 (ery well. In) 247.18 610 P -0.09 (addition, the VPR timing-dri) 54 600 P -0.09 (v) 157.01 600 P -0.09 (en router produces circuits which are) 161.37 600 P 3 F 2.12 (2.6 times) 54 590 P 1 F 2.12 ( f) 88.62 590 P 2.12 (aster) 95.89 590 P 2.12 (, on a) 112.52 590 P 2.12 (v) 136.32 590 P 2.12 (erage, than those produced by the VPR) 140.69 590 P -0.09 (routability-dri) 54 580 P -0.09 (v) 104.27 580 P -0.09 (en router) 108.64 580 P -0.09 (. Clearly timing-dri) 140.29 580 P -0.09 (v) 211.79 580 P -0.09 (en routing is essential) 216.15 580 P (to obtain good circuit speed.) 54 570 T 2 11 Q (3.2) 54 547.67 T (Delay Model) 75.6 547.67 T 54 692/G999705 FmPA 1 9 Q 0.4 (Our delay v) 72 532 P 0.4 (alues are all based on the delays in TSMC\325) 115.06 532 P 0.4 (s 0.35) 272.22 532 P 54 676/G999807 FmPA 4 F 0.25 (m) 54 522 P 1 F 0.25 (m, 3.3 V CMOS process. T) 59.18 522 P 0.25 (o determine the critical path of a cir-) 160.68 522 P (cuit, we must:) 54 512 T (1.) 68.4 498 T -0.06 (Determine the delay of e) 82.8 498 P -0.06 (v) 171.32 498 P -0.06 (ery connection internal to a logic) 175.68 498 P 54 642/G999815 FmPA (block,) 82.8 487 T (2.) 68.4 472 T 1.78 (Determine the delay of e) 82.8 472 P 1.78 (v) 178.68 472 P 1.78 (ery connection between logic) 183.05 472 P 54 616/G999821 FmPA (blocks, and) 82.8 462 T (3.) 68.4 448 T 0.92 (Perform a path-based timing analysis of the circuit using) 82.8 448 P 54 592/G999816 FmPA (these delay v) 82.8 438 T (alues.) 129.56 438 T 0.14 (W) 72 424 P 0.14 (e found the delay of the connections within logic blocks by) 79.78 424 P 54 568/G999817 FmPA 0.39 (performing SPICE simulations of e) 54 414 P 0.39 (v) 182.33 414 P 0.39 (ery structure in a logic block.) 186.7 414 P 0.04 (See [6, 7] for transistor) 54 404 P 0.04 (-le) 137.22 404 P 0.04 (v) 146.49 404 P 0.04 (el schematics of the logic block we use,) 150.85 404 P (and a listing of v) 54 394 T (arious important delays.) 114.27 394 T 1.24 (After a routing is complete, we can determine the delay of) 72 380 P 54 524/G999826 FmPA -0.06 (e) 54 370 P -0.06 (v) 57.77 370 P -0.06 (ery routed connection. W) 62.14 370 P -0.06 (e model pass transistors and b) 154.9 370 P -0.06 (uf) 262.17 370 P -0.06 (fers by) 269.44 370 P 1.77 (equi) 54 360 P 1.77 (v) 69.27 360 P 1.77 (alent circuits composed of resistors, capacitors, and ideal-) 73.55 360 P -0.19 (ized, constant delay elements. The v) 54 350 P -0.19 (alues of the v) 185.59 350 P -0.19 (arious equi) 233.02 350 P -0.19 (v) 272.35 350 P -0.19 (alent) 276.62 350 P 1.73 (resistances, capacitances and b) 54 340 P 1.73 (uf) 169.97 340 P 1.73 (fer intrinsic delays were deter-) 177.24 340 P 0.57 (mined from SPICE simulations with the TSMC 0.35) 54 330 P 4 F 0.57 (m) 249.87 330 P 1 F 0.57 (m process.) 255.05 330 P 0.64 (After a routing is complete, VPR uses these simpli\336ed models of) 54 320 P -0.02 (pass transistors and b) 54 310 P -0.02 (uf) 130.51 310 P -0.02 (fers, as well as metal capacitance and resis-) 137.79 310 P 1.08 (tance data, to b) 54 300 P 1.08 (uild an equi) 114.88 300 P 1.08 (v) 159.31 300 P 1.08 (alent RC-tree for each net. It then) 163.59 300 P 0.83 (computes the Elmore delay from the source to each of the sinks.) 54 290 P 0.57 (W) 54 280 P 0.57 (e ha) 61.78 280 P 0.57 (v) 76.91 280 P 0.57 (e found the accurac) 81.27 280 P 0.57 (y of this delay model to be quite good) 153.07 280 P 0.68 (\321 the connection delays it predicts are almost al) 54 270 P 0.68 (w) 234.85 270 P 0.68 (ays within 9%) 241.26 270 P (of SPICE [6, 7].) 54 260 T 3 (Finally) 72 246 P 3 (, VPR performs a path-based timing-analysis [32]) 96.92 246 P 54 390/G1000127 FmPA -0.21 (using these connection delay v) 54 236 P -0.21 (alues to determine the circuit critical) 163.43 236 P (path.) 54 226 T 2 11 Q (3.3) 54 203.67 T (Ar) 75.6 203.67 T (ea Model) 88.23 203.67 T 54 348/G1006453 FmPA 1 9 Q 0.21 (Since the area of typical commercial FPGAs is dominated by) 72 188 P 54 332/G1006465 FmPA 1.52 (transistor area,) 54 178 P 1 7.2 Q 1.21 (2) 108.5 181.6 P 1 9 Q 1.52 ( the most accurate w) 112.1 178 P 1.52 (ay to assess the area of an) 192.05 178 P 0.41 (FPGA architecture, short of actually laying out each FPGA archi-) 54 168 P 0.74 (tecture studied, is to estimate the total transistor area required by) 54 158 P 1.28 (its layout. Our area model is based on counting the number of) 54 148 P 3 F 3.93 (minimum-width tr) 54 138 P 3.93 (ansistor ar) 122.55 138 P 3.93 (eas) 165.41 138 P 1 F 3.93 ( required to implement each) 177.41 138 P 54 122 294.12 129.5 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 54.5 127.5 207 127.5 2 L 0.5 H 2 Z 0 X 0 0 0 1 0 0 0 K N 0 0 612 792 C 1 9 Q 0 X 0 0 0 1 0 0 0 K (1.) 54 116 T 4.59 (The Xilinx commercial FPGA router optimizes a more) 64.8 116 P 54 260/G1008989 FmPA (adv) 64.8 106 T (anced \050Pen\336eld-Rubinstein\051 delay model [31].) 77.57 106 T (2.) 54 96 T 0.02 (FPGA architects at both Xilinx and Altera ha) 64.8 96 P 0.02 (v) 227.46 96 P 0.02 (e con\336rmed to us) 231.83 96 P 54 240/G1006519 FmPA 2.46 (that transistor area determines the die size of their current) 64.8 86 P (FPGAs.) 64.8 76 T 1.3 (FPGA architecture. A minimum-width transistor area is simply) 317.88 714 P 0.08 (the layout area occupied by the smallest transistor that can be con-) 317.88 704 P -0.01 (tacted in a process, plus the minimum spacing to another transistor) 317.88 694 P 1.1 (abo) 317.88 684 P 1.1 (v) 330.74 684 P 1.1 (e it and to its right. By counting the number of minimum-) 335.11 684 P 0.18 (width transistor areas required to implement an FPGA, rather than) 317.88 674 P 2.97 (the number of square microns which these transistors w) 317.88 664 P 2.97 (ould) 542 664 P 1.51 (occup) 317.88 654 P 1.51 (y) 339.28 654 P 1.51 (, we obtain a process-independent estimate of the FPGA) 343.2 654 P 0.71 (area. T) 317.88 644 P 0.71 (ransistors lar) 346.21 644 P 0.71 (ger than minimum-width are counted as se) 393 644 P 0.71 (v-) 550.5 644 P 0.86 (eral minimum-width transistor areas. VPR computes the routing) 317.88 634 P 1.57 (area of an FPGA by \322b) 317.88 624 P 1.57 (uilding\323 e) 408.29 624 P 1.57 (v) 445.38 624 P 1.57 (ery structure required by the) 449.74 624 P 2.44 (FPGA) 317.88 614 P 2.44 (\325) 339.89 614 P 2.44 (s routing, and summing the number of minimum-width) 342.39 614 P 0.06 (transistor areas required by each. F) 317.88 604 P 0.06 (or details of the transistor le) 446.32 604 P 0.06 (v) 547.14 604 P 0.06 (el) 551.5 604 P 1.47 (schematics VPR assumes when \322b) 317.88 594 P 1.47 (uilding\323 v) 447.57 594 P 1.47 (arious FPGA struc-) 485.07 594 P (tures, see [6, 7].) 317.88 584 T 0.52 (T) 335.88 570 P 0.52 (o allo) 340.66 570 P 0.52 (w a) 361.2 570 P 0.52 (v) 374.28 570 P 0.52 (eraging of results from circuits of dif) 378.65 570 P 0.52 (ferent sizes,) 514.5 570 P 318 714/G1000517 FmPA 0.57 (we use a normalized area metric: the number of minimum-width) 317.88 560 P 0.09 (transistor areas per tile \050i.e. per logic block\051. All the results in this) 317.88 550 P 0.03 (paper list only the area of an FPGA) 317.88 540 P 0.03 (\325) 444.84 540 P 0.03 (s routing, since the logic block) 447.34 540 P 0.85 (is held constant throughout all the e) 317.88 530 P 0.85 (xperiments. The logic block) 451.35 530 P 0.42 (used in this paper occupies 1678 minimum-width transistor areas,) 317.88 520 P 0.86 (and hence the addition of 1678 to an) 317.88 510 P 0.86 (y of the routing area results) 454.98 510 P (presented in this paper yields the total area per tile.) 317.88 500 T 0.18 (Prior researchers ha) 335.88 486 P 0.18 (v) 407.53 486 P 0.18 (e e) 411.9 486 P 0.18 (v) 422.1 486 P 0.18 (aluated routing area either by count-) 426.37 486 P 318 630/G1000508 FmPA 2.27 (ing the number of tracks per channel required to successfully) 317.88 476 P 0.14 (route, or by counting the number of programmable switches in the) 317.88 466 P 0.33 (routing. Counting the number of tracks required to route a circuit) 317.88 456 P 1.81 (is not a good area metric for architecture studies \050such as this) 317.88 446 P -0.22 (study\051 in which the number of switches per track se) 317.88 436 P -0.22 (gment can v) 501.51 436 P -0.22 (ary) 544.84 436 P -0.22 (,) 555.75 436 P 2.12 (since the area required by each routing track is then v) 317.88 426 P 2.12 (ariable.) 531.26 426 P 0.06 (Counting the number of programmable switches in the routing is a) 317.88 416 P 0.42 (better area metric, b) 317.88 406 P 0.42 (ut is still not suf) 390.92 406 P 0.42 (\336ciently accurate for our pur-) 450.37 406 P 0.32 (poses. Modern FPGAs use three dif) 317.88 396 P 0.32 (ferent types of programmable) 450.32 396 P 1.52 (switch, and the dif) 317.88 386 P 1.52 (ferent switches require considerably dif) 388.7 386 P 1.52 (ferent) 537.01 386 P 0.74 (layout areas. The connection blocks from routing tracks to logic) 317.88 376 P 0.99 (block input pins are implemented with multiple) 317.88 366 P 0.99 (x) 494.68 366 P 0.99 (ers; the connec-) 499.04 366 P 1.69 (tion blocks from logic block output pins to routing tracks, and) 317.88 356 P -0.09 (some of the routing switches, are implemented via pass transistors;) 317.88 346 P 0.98 (and some routing switches are tri-state b) 317.88 336 P 0.98 (uf) 469.06 336 P 0.98 (fers. T) 476.33 336 P 0.98 (able 1 lists the) 503.31 336 P 1.46 (area required by each of these switch types, including an) 317.88 326 P 1.46 (y area) 534.81 326 P 2.06 (required by SRAM bits to control each switch. The area per) 317.88 316 P 0.1 (switch v) 317.88 306 P 0.1 (aries by a) 348.01 306 P 3 F 0.1 ( factor of 6.8) 382.69 306 P 1 F 0.1 ( from the most area-ef) 429.5 306 P 0.1 (\336cient switch) 509.65 306 P 0.35 (to the least area-ef) 317.88 296 P 0.35 (\336cient. Clearly) 384.92 296 P 0.35 (, simply counting the number of) 440.77 296 P 0.47 (programmable switches in a routing architecture does not pro) 317.88 286 P 0.47 (vide) 542.5 286 P (a good area estimate.) 317.88 276 T 2 12 Q (4) 317.88 140 T (Experimental Results: Single W) 335.88 140 T (ir) 502.33 140 T (e) 510.78 140 T 318 284/G1010302 FmPA (Segment Length Ar) 335.88 126 T (chitectur) 436.32 126 T (es) 482.09 126 T 1 9 Q 0.41 (In this section we e) 335.88 110 P 0.41 (v) 406.8 110 P 0.41 (aluate architectures in which e) 411.08 110 P 0.41 (v) 521.98 110 P 0.41 (ery rout-) 526.35 110 P 318 254/G1010313 FmPA 0.13 (ing wire se) 317.88 100 P 0.13 (gment has the same length, and in which all the routing) 357.49 100 P 0.53 (switches in switch blocks are tri-state b) 317.88 90 P 0.53 (uf) 462.34 90 P 0.53 (fers. W) 469.61 90 P 0.53 (e ran the twenty) 498.68 90 P -0.05 (lar) 317.88 80 P -0.05 (gest MCNC benchmarks through the \337o) 327.21 80 P -0.05 (w of Figure 3 and deter-) 471 80 P 2 F (T) 341.62 259 T (able 1:) 346.79 259 T 1 F ( Comparison of programmable switch areas.) 372.54 259 T 318 403/G1008878 FmPA (Switch Description) 334.49 242 T 318 386/G1008882 FmPA (Minimum-W) 427.37 242 T (idth T) 474.51 242 T (ransistor Areas) 495.95 242 T 420 386/G1008884 FmPA (Multiple) 320.28 225 T (x) 351.15 225 T (er \05032 inputs\051) 355.51 225 T 318 369/G1008886 FmPA (2.88 per switch \05092 / 32 inputs\051) 431.28 226 T 420 370/G1008888 FmPA (Multiple) 320.28 212 T (x) 351.15 212 T (er \0504 inputs\051) 355.51 212 T 318 356/G1008890 FmPA (4.5 per switch \05018 / 4 inputs\051) 434.66 212 T 420 356/G1008892 FmPA (P) 320.28 199 T (ass transistor) 325.15 199 T 318 343/G1008894 FmPA (\05010x minimum dri) 320.28 189 T (v) 386.06 189 T (e\051) 390.42 189 T (11.5) 480.9 194 T 420 338/G1008896 FmPA (T) 320.28 176 T (ri-state b) 325.46 176 T (uf) 357.02 176 T (fer) 364.3 176 T 318 320/G1008898 FmPA (\0505x minimum dri) 320.28 166 T (v) 381.56 166 T (e\051) 385.92 166 T (19.7) 480.9 171 T 420 315/G1008900 FmPA 318.28 251.75 318.28 161.25 2 L V 0.5 H 0 Z N 419.95 252.25 419.95 160.75 2 L V N 557.6 251.75 557.6 161.25 2 L V N 318.03 252 557.85 252 2 L V N 318.53 236.25 557.35 236.25 2 L V N 318.53 233.75 557.35 233.75 2 L V N 318.03 220 557.85 220 2 L V N 318.03 207 557.85 207 2 L V N 318.03 184 557.85 184 2 L V N 318.03 161 557.85 161 2 L V N 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.4/DEST FmPD2 373 409/M9.33194.TableTitle.Table.73 FmPA 373 409/I1.1008877 FmPA 336 292/M9.37788.Heading3.725.Experimental.Philosophy FmPA 336 292/I1.1010300 FmPA 76 355/M9.39827.Heading2.33.Area.Model FmPA 76 355/I1.1007587 FmPA 336 292/M9.16767.Heading2.73.Single.Wire.Length.Architectures FmPA 336 292/I1.1010301 FmPA 76 699/M9.31669.Heading3.723.Delay.Model FmPA 76 699/I1.1004508 FmPA [/Rect[94 257 98 267]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[282 243 291 253]/Border[0 0 0]/Page 10/View[/XYZ null 338 429 FmDC exch pop null]/LNK FmPD [/Rect[499 333 526 343]/Border[0 0 0]/Page 4/View[/XYZ null 373 409 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 792 C 0 0 612 792 C [/Rect[489 77 520 87]/Border[0 0 0]/Page 3/View[/XYZ null 401 617 FmDC exch pop null]/LNK FmPD [/Rect[357 581 361 591]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[230 103 239 113]/Border[0 0 0]/Page 10/View[/XYZ null 338 452 FmDC exch pop null]/LNK FmPD [/Rect[81 401 86 411]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[103 257 107 267]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[366 581 370 591]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[219 617 228 627]/Border[0 0 0]/Page 10/View[/XYZ null 338 551 FmDC exch pop null]/LNK FmPD [/Rect[72 401 77 411]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 63 567 729]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "4" 4 %%Page: "5" 5 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 54 541.33 558 720 C 54 546.33 558 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 76 610 537 781 414.9 153.9 104.39 565.68 FMBEGINEPSF %%BeginDocument: /jayar/d0/vaughn/thesis/place/fpga99/grap/area_delay_one_length.eps %!PS-Adobe-2.0 EPSF-1.2 %%Title: stdin (ditroff) %%Creator: gractus.eecg:vaughn (Vaughn Betz,EECG,LP 392,1653,7662197,G,G ) %%CreationDate: Thu Dec 3 17:46:41 1998 %%For:vaughn vaughn %%Pages: 1 %%DocumentFonts: Times-Italic Times-BoldItalic Helvetica DIThacks Symbol Courier Helvetica-Bold Times-Roman Times-Bold Courier-Bold %%BoundingBox: 76 610 537 781 %%EndProlog %%Page 1 1 %! % Start of psdit.pro -- prolog for ditroff translator % Copyright (c) 1985,1987 Adobe Systems Incorporated. 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/CharProcs 50 dict def CharProcs begin /space{}def /.notdef{}def /ru{500 0 rls}def /rn{0 750 moveto 500 0 rls}def /vr{20 800 moveto 0 -770 rls}def /bv{20 800 moveto 0 -1000 rls}def /br{20 770 moveto 0 -1040 rls}def /ul{0 -250 moveto 500 0 rls}def /ob{200 250 rmoveto currentpoint newpath 200 0 360 arc closepath stroke}def /bu{200 400 rmoveto currentpoint newpath 200 0 360 arc closepath fill}def /sq{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath stroke}def /bx{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath fill}def /ci{355 333 rmoveto currentpoint newpath 333 0 360 arc 50 setlinewidth stroke}def /lt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 add exch s4 a4p stroke}def /lb{20 800 moveto 0 -550 rlineto currx -200 2cx s4 add exch s4 a4p stroke}def /rt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 sub exch s4 a4p stroke}def /rb{20 800 moveto 0 -500 rlineto currx -200 2cx s4 sub exch s4 a4p stroke}def /lk{20 800 moveto 20 300 -280 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /rk{20 800 moveto 20 300 320 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /lf{20 800 moveto 0 -1000 rlineto s4 0 rls}def /rf{20 800 moveto 0 -1000 rlineto s4 neg 0 rls}def /lc{20 -200 moveto 0 1000 rlineto s4 0 rls}def /rc{20 -200 moveto 0 1000 rlineto s4 neg 0 rls}def end /Metrics 50 dict def Metrics begin /.notdef 0 def /space 500 def /ru 500 def /br 0 def /lt 250 def /lb 250 def /rt 250 def /rb 250 def /lk 250 def /rk 250 def /rc 250 def /lc 250 def /rf 250 def /lf 250 def /bv 250 def /ob 350 def /bu 350 def /ci 750 def /bx 750 def /sq 750 def /rn 500 def /ul 500 def /vr 0 def end DITfd begin /s2 500 def /s4 250 def /s3 333 def /a4p{arcto pop pop pop pop}def /2cx{2 copy exch}def /rls{rlineto stroke}def /currx{currentpoint pop}def /dround{transform round exch round exch itransform} def end end /DIThacks exch definefont pop ditstart (psc)xT 576 1 1 xr 1(Times-Roman)xf 1 f 2(Times-Italic)xf 2 f 3(Times-Bold)xf 3 f 4(Times-BoldItalic)xf 4 f 5(Helvetica)xf 5 f 6(Helvetica-Bold)xf 6 f 7(Courier)xf 7 f 8(Courier-Bold)xf 8 f 9(Symbol)xf 9 f 10(DIThacks)xf 10 f 10 s 1 f xi 10 s 0 xH 0 xS 1 f 1582 1248 MXY 0 -1152 Dl 1900 0 Dl 3483 MX 0 1152 Dl -1900 0 Dl 1779 1429(Wire)N 1960(Segment)X 2260(Length)X 2507(\(Logic)X 2741(Blocks)X 2983(Spanned\))X 723 448(Routing)N 1000(Area)X 737 544(\(Min.-Width)N 778 640(Transistor)N 833 736(Areas\))N 766 832(\(20)N 893(Circuit)X 607 928(Arithmetic)N 974(Average\))X 3771 544(Critical)N 4031(Path)X 3910 640(\(ns\))N 3798 736(\(20)N 3925(Circuit)X 3643 832(Geometric)N 4002(Average\))X 1749 1248 MXY 0 -57 Dl 1729 1336(1)N 2075 1248 MXY 0 -57 Dl 2055 1336(2)N 2400 1248 MXY 0 -57 Dl 2380 1336(4)N 2726 1248 MXY 0 -57 Dl 2706 1336(8)N 3052 1248 MXY 0 -57 Dl 3012 1336(16)N 3378 1248 MXY 0 -57 Dl 3294 1336(Long)N 1582 1148 MXY 57 0 Dl 1402 1164(6000)N 1582 901 MXY 57 0 Dl 1402 917(8000)N 1582 653 MXY 57 0 Dl 1362 669(10000)N 1582 405 MXY 57 0 Dl 1362 421(12000)N 1582 158 MXY 57 0 Dl 1362 174(14000)N 3483 1126 MXY -57 0 Dl 3503 1142(40)N 3483 883 MXY -57 0 Dl 3503 899(50)N 3483 641 MXY -57 0 Dl 3503 657(60)N 3483 398 MXY -57 0 Dl 3503 414(70)N 3483 156 MXY -57 0 Dl 3503 172(80)N 5 s 10 f 1742 924(g)N 10 s 1749 908 MXY 24 15 Dl 1800 939 MXY 24 15 Dl 1850 972 MXY 24 15 Dl 1900 1003 MXY 24 15 Dl 1950 1036 MXY 24 15 Dl 2001 1067 MXY 24 15 Dl 2051 1099 MXY 24 15 Dl 5 s 2068 1130(g)N 10 s 2075 1114 MXY 28 4 Dl 2134 1123 MXY 28 4 Dl 2193 1132 MXY 28 4 Dl 2253 1140 MXY 28 4 Dl 2313 1148 MXY 28 4 Dl 2372 1156 MXY 28 4 Dl 5 s 2393 1177(g)N 10 s 2400 1161 MXY 28 -4 Dl 2460 1151 MXY 28 -4 Dl 2520 1141 MXY 28 -4 Dl 2579 1131 MXY 28 -4 Dl 2638 1121 MXY 28 -4 Dl 2698 1111 MXY 28 -4 Dl 5 s 2719 1122(g)N 10 s 2726 1106 MXY 25 -13 Dl 2776 1081 MXY 25 -13 Dl 2826 1055 MXY 25 -13 Dl 2876 1030 MXY 25 -13 Dl 2926 1004 MXY 25 -13 Dl 2976 979 MXY 25 -13 Dl 3026 953 MXY 25 -13 Dl 5 s 3045 956(g)N 10 s 3052 940 MXY 10 -26 Dl 3074 886 MXY 10 -26 Dl 3097 832 MXY 10 -26 Dl 3119 778 MXY 10 -26 Dl 3142 724 MXY 10 -26 Dl 3164 670 MXY 10 -26 Dl 3187 616 MXY 10 -26 Dl 3209 563 MXY 10 -26 Dl 3231 508 MXY 10 -26 Dl 3254 455 MXY 10 -26 Dl 3276 401 MXY 10 -26 Dl 3299 347 MXY 10 -26 Dl 3321 293 MXY 10 -26 Dl 3344 239 MXY 10 -26 Dl 3366 185 MXY 10 -26 Dl 5 s 3371 174(g)N 1742 367(g)N 10 s 1749 351 MXY 325 449 Dl 5 s 2068 817(g)N 10 s 2075 801 MXY 325 189 Dl 5 s 2393 1006(g)N 10 s 2400 990 MXY 325 14 Dl 5 s 2719 1020(g)N 10 s 2726 1004 MXY 325 -80 Dl 5 s 3045 940(g)N 10 s 3052 924 MXY 325 -730 Dl 5 s 3371 210(g)N 1 p xt xs %%Trailer %%EOF %%EndDocument FMENDEPSF 2 9 Q 0 X 0 0 0 1 0 0 0 K (Figur) 179.5 553.33 T (e 4:) 200.84 553.33 T 1 F ( Speed and area of FPGAs vs. routing wire se) 214.58 553.33 T (gment length.) 380.67 553.33 T 54 697/G1010312 FmPA J J (Critical path) 261.33 656 T (Routing area) 348 599.33 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 54 541.33 558 720 C 0 0 612 792 C 1 9 Q 0 X 0 0 0 1 0 0 0 K -0.12 (mined the routing area required and the critical path delay achie) 53.33 532 P -0.12 (v) 281.8 532 P -0.12 (ed) 286.17 532 P 0.94 (by each circuit in each architecture of interest. Throughout this) 53.33 522 P 0.72 (paper we compare architectures on the basis of their a) 53.33 512 P 0.72 (v) 253.35 512 P 0.72 (erage per-) 257.72 512 P 0.95 (formance across the 20 benchmark circuits; the indi) 53.33 502 P 0.95 (vidual circuit) 245.97 502 P (results track the o) 53.33 492 T (v) 116.94 492 T (erall a) 121.3 492 T (v) 143.36 492 T (erage quite well, ho) 147.73 492 T (we) 218.48 492 T (v) 228.75 492 T (er) 233.12 492 T (.) 239.62 492 T -0.12 (The solid curv) 71.33 478 P -0.12 (e in Figure 4 is the a) 122.96 478 P -0.12 (v) 195.57 478 P -0.12 (erage \050o) 199.94 478 P -0.12 (v) 228.92 478 P -0.12 (er the twenty cir-) 233.29 478 P 53 622/G1007800 FmPA 1.76 (cuits\051 of the critical path delay for each architecture, while the) 53.33 468 P 0.34 (dashed curv) 53.33 458 P 0.34 (e is the a) 96.77 458 P 0.34 (v) 129.35 458 P 0.34 (erage routing area required in each architec-) 133.71 458 P 0.47 (ture. The horizontal axis in both Figures 4 is the length \050in logic) 53.33 448 P 0.11 (blocks\051 of the routing wire se) 53.33 438 P 0.11 (gments; the \322Long\323 point refers to an) 159.5 438 P 1.49 (architecture in which each routing wire spans the entire chip \050a) 53.33 428 P 0.16 (long line in Xilinx\325) 53.33 418 P 0.16 (s terminology\051. Recall that each architecture in) 122.58 418 P -0.04 (Figure 4 potentially contains a dif) 53.33 408 P -0.04 (ferent number of tracks per chan-) 174.66 408 P 0.86 (nel \321 each circuit is routed in an FPGA with 20% more routing) 53.33 398 P 1.37 (tracks than the minimum the circuit needs to route in an FPGA) 53.33 388 P (with the gi) 53.33 378 T (v) 91.61 378 T (en architecture.) 95.97 378 T 0.36 (From Figure 4, one can see that the f) 71.33 364 P 0.36 (astest FPGA which uses) 206.34 364 P 53 508/G1000839 FmPA 0.15 (only one length of wire uses wires of length 4 or length 8. Shorter) 53.33 354 P 2.46 (wires lead to poor speed because long connections must pass) 53.33 344 P 0.74 (through too man) 53.33 334 P 0.74 (y b) 114.18 334 P 0.74 (uf) 125.99 334 P 0.74 (fers. V) 133.26 334 P 0.74 (ery long wires de) 160.48 334 P 0.74 (grade speed in tw) 224.8 334 P 0.74 (o) 290.17 334 P 0.31 (w) 53.33 324 P 0.31 (ays. First, short connections are forced to use long wires, which) 59.74 324 P -0.13 (are slo) 53.33 314 P -0.13 (wer than short wires due to their lar) 76.72 314 P -0.13 (ger capacitance. Second,) 203.85 314 P -0.2 (e) 53.33 304 P -0.2 (v) 57.1 304 P -0.2 (en connections that tra) 61.47 304 P -0.2 (v) 141.93 304 P -0.2 (el the entire length of a long wire become) 146.29 304 P 0.34 (slo) 53.33 294 P 0.34 (w when the wire is too long because the metal resistance of the) 63.61 294 P 0.64 (wire becomes lar) 53.33 284 P 0.64 (ge, and e) 115.93 284 P 0.64 (v) 149.22 284 P 0.64 (entually reduces speed belo) 153.59 284 P 0.64 (w that of a) 254.51 284 P (lar) 53.33 274 T (ger number of short wires connected by b) 62.67 274 T (uf) 212.2 274 T (fers.) 219.47 274 T 0.1 (Figure 4 also sho) 71.33 260 P 0.1 (ws that wire se) 133.16 260 P 0.1 (gments of length 4 lead to the) 187.07 260 P 53 404/G1006650 FmPA 0.57 (most area-ef) 53.33 250 P 0.57 (\336cient FPGA architecture. As we increase the length) 98.41 250 P 0.31 (of the routing wires tw) 53.33 240 P 0.31 (o competing f) 136.48 240 P 0.31 (actors determine the resulting) 187 240 P 1.43 (architecture\325) 53.33 230 P 1.43 (s area-ef) 98.32 230 P 1.43 (\336cienc) 130.25 230 P 1.43 (y) 154.11 230 P 1.43 (. First, longer wires are less \322\337e) 158.02 230 P 1.43 (xi-) 284.67 230 P 0.68 (ble\323; the) 53.33 220 P 0.68 (y cannot be split in the middle, so short connections will) 84.62 220 P 0.01 (w) 53.33 210 P 0.01 (aste part of a wire se) 59.74 210 P 0.01 (gment. This means the number of tracks per) 133.87 210 P 1.68 (channel required to successfully route a circuit increases as the) 53.33 200 P 1.25 (wire se) 53.33 190 P 1.25 (gment length increases. On the other hand, longer wires) 80.19 190 P -0.18 (pass through more switch blocks before terminating, so the fraction) 53.33 180 P 0.08 (of \322internal\323 switch points in switch blocks increases. As Figure 5) 53.33 170 P 1.62 (sho) 53.33 160 P 1.62 (ws, these internal switch points require fe) 65.61 160 P 1.62 (wer programmable) 224.82 160 P 1.51 (switches, resulting in decreased area. When the disjoint switch) 53.33 150 P 1.5 (block is emplo) 53.33 140 P 1.5 (yed, each internal switch point requires only one) 109.23 140 P 0.95 (programmable switch, while \322end\323 switch points require six pro-) 53.33 130 P (grammable switches.) 53.33 120 T 0.59 (Length 4 wire se) 71.33 106 P 0.59 (gments achie) 133.21 106 P 0.59 (v) 180.82 106 P 0.59 (e the best combination of lo) 185.19 106 P 0.59 (w) 288.17 106 P 53 250/G1009880 FmPA 0.66 (delay and high area-ef) 53.33 96 P 0.66 (\336cienc) 135.3 96 P 0.66 (y) 159.16 96 P 0.66 (. An architecture using all length 8) 163.07 96 P 0.88 (wires can achie) 53.33 86 P 0.88 (v) 110.35 86 P 0.88 (e slightly \0501.3%\051 better speed, b) 114.71 86 P 0.88 (ut requires 7.4%) 233.67 86 P 0.92 (more routing area. While real FPGA architectures can of course) 53.33 76 P 0.03 (use more than one wire length, this result is e) 316.67 532 P 0.03 (v) 479.69 532 P 0.03 (ocati) 484.01 532 P 0.03 (v) 501.28 532 P 0.03 (e. It leads one) 505.64 532 P 0.6 (to e) 316.67 522 P 0.6 (xpect that the best FPGA architectures will either include sig-) 330.38 522 P -0.12 (ni\336cant numbers of length 4 or length 8 wires, or will include some) 316.67 512 P (wires shorter and some wires longer than length 4 or 8.) 316.67 502 T 2 11 Q (4.1) 316.67 479.67 T (Ar) 338.27 479.67 T (ea Model Re) 350.89 479.67 T (visited) 409.38 479.67 T 317 624/G1010317 FmPA 1 9 Q 0.28 (Recall that our area-ef) 334.67 464 P 0.28 (\336cienc) 415.5 464 P 0.28 (y metric throughout this paper is) 439.36 464 P 317 608/G1009871 FmPA 0.2 (transistor area, since current commercial FPGAs are dominated by) 316.67 454 P 1.59 (transistor area. T) 316.67 444 P 1.59 (o con\336rm that the FPGAs we e) 383.71 444 P 1.59 (v) 504.54 444 P 1.59 (aluate in this) 508.81 444 P 0.16 (paper are all transistor) 316.67 434 P 0.16 (-area limited, we also monitored the a) 397.18 434 P 0.16 (v) 534.15 434 P 0.16 (erage) 538.52 434 P 1.99 (number of tracks per routing channel \050W) 316.67 424 P 1 7.2 Q 1.6 (min) 475.59 421.75 P 1 9 Q 1.99 (\051 required by each) 486.8 424 P -0.12 (architecture to route the benchmark circuits, since this indicates the) 316.67 412.35 P -0.22 (amount of routing metal area required by the FPGA. W) 316.67 402.35 P -0.22 (e found that) 515.45 402.35 P 0.26 (the architectures that were ef) 316.67 392.35 P 0.26 (\336cient in terms of transistor area gen-) 421.45 392.35 P 1.83 (erally had a) 316.67 382.35 P 1.83 (v) 362.14 382.35 P 1.83 (erage W) 366.5 382.35 P 1 7.2 Q 1.47 (min) 398.57 380.1 P 1 9 Q 1.83 ( v) 409.77 382.35 P 1.83 (alues \050and hence metal routing area\051) 418.13 382.35 P -0.03 (within a) 316.67 370.7 P 4 F -0.03 (\261) 348.11 370.7 P 1 F -0.03 (20% range, and all these architectures are clearly transis-) 353.05 370.7 P -0.18 (tor) 316.67 360.7 P -0.18 (-area limited. An FPGA emplo) 326.49 360.7 P -0.18 (ying all length 1 wires, for e) 438.98 360.7 P -0.18 (xam-) 539.51 360.7 P 3.04 (ple, requires 17.6% fe) 316.67 350.7 P 3.04 (wer tracks per channel than an FPGA) 404.79 350.7 P 0.54 (emplo) 316.67 340.7 P 0.54 (ying length 4 wires, while a length 8 FPGA requires 20.9%) 339.08 340.7 P (more tracks per channel than a length 4 FPGA.) 316.67 330.7 T 0.7 (A fe) 334.67 316.7 P 0.7 (w architectures with v) 350.88 316.7 P 0.7 (ery poor area-ef) 432.57 316.7 P 0.7 (\336cienc) 491.21 316.7 P 0.7 (y according) 515.07 316.7 P 317 461/G1009883 FmPA 0.51 (to our transistor) 316.67 306.7 P 0.51 (-based area metric had much greater W) 374.51 306.7 P 1 7.2 Q 0.41 (min) 519.02 304.45 P 1 9 Q 0.51 ( v) 530.22 306.7 P 0.51 (alues,) 537.26 306.7 P -0.21 (ho) 316.67 295.05 P -0.21 (we) 325.44 295.05 P -0.21 (v) 335.71 295.05 P -0.21 (er) 340.08 295.05 P -0.21 (. An FPGA emplo) 346.57 295.05 P -0.21 (ying all long lines, for e) 413.4 295.05 P -0.21 (xample, requires) 498.22 295.05 P 0.74 (3.2x as man) 316.67 285.05 P 0.74 (y tracks per channel as an FPGA emplo) 361.25 285.05 P 0.74 (ying length 4) 509.03 285.05 P 1.13 (wires. Depending on the number of metal layers a) 316.67 275.05 P 1.13 (v) 508.6 275.05 P 1.13 (ailable then,) 512.88 275.05 P -0.09 (such an architecture may become metal \050rather than transistor\051 lim-) 316.67 265.05 P 1.5 (ited. If such poor architectures are in f) 316.67 255.05 P 1.5 (act metal-limited, rather) 468.27 255.05 P -0.1 (than transistor) 316.67 245.05 P -0.1 (-limited, the) 367.64 245.05 P -0.1 (y are simply e) 411.41 245.05 P -0.1 (v) 461.64 245.05 P -0.1 (en w) 466 245.05 P -0.1 (orse choices than the) 483.06 245.05 P (results presented here indicate.) 316.67 235.05 T 316.67 70.67 558 538 C 316.67 70.67 556.43 214.64 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 358.4 210.63 358.4 193.3 2 L 0.5 H 2 Z 0 X 0 0 0 1 0 0 0 K N 368.9 210.63 368.9 193.3 2 L N 379.41 210.63 379.41 193.3 2 L N 388.84 162.75 407 162.75 2 L 2 H N 388.84 173.25 407 173.25 2 L 1 H N 388.84 183.76 407 183.76 2 L N 358.4 152.57 358.4 135.23 2 L 0.5 H N 368.9 152.57 368.9 135.23 2 L N 379.41 152.57 379.41 135.23 2 L N 330.01 162.75 349.82 162.75 2 L 2 H N 330.01 173.26 349.82 173.26 2 L 1 H N 330.01 183.76 349.82 183.76 2 L N J 354.58 156.97 356.66 158.47 357.18 153.37 352.5 155.47 4 Y 0.5 H 0 Z N 354.58 156.97 356.66 158.47 357.18 153.37 352.5 155.47 4 Y V J 350.33 162.84 354.43 157.17 2 L J 350.33 162.84 350.92 162.03 2 L N [2.499 4.998] 2.499 I 350.92 162.03 353.85 157.98 2 L N J 353.85 157.98 354.43 157.17 2 L N J 355.94 187.82 353.43 188.38 356.91 192.15 358.44 187.25 4 Y N 355.94 187.82 353.43 188.38 356.91 192.15 358.44 187.25 4 Y V J 350.33 162.84 355.88 187.57 2 L J 350.33 162.84 350.55 163.82 2 L N [2.122 4.244] 2.122 I 350.55 163.82 355.66 186.59 2 L N J 355.66 186.59 355.88 187.57 2 L N J 363.55 154.92 364.34 152.48 359.32 153.57 362.77 157.37 4 Y N 363.55 154.92 364.34 152.48 359.32 153.57 362.77 157.37 4 Y V J 388.34 162.84 363.79 155 2 L J 388.34 162.84 387.39 162.54 2 L N [2.161 4.321] 2.161 I 387.39 162.54 364.75 155.3 2 L N J 364.75 155.3 363.79 155 2 L N J 362.14 189.71 360.3 187.91 359.04 192.89 363.98 191.5 4 Y N 362.14 189.71 360.3 187.91 359.04 192.89 363.98 191.5 4 Y V J 387.58 163.6 362.32 189.53 2 L J 387.58 163.6 386.88 164.32 2 L N [2.011 4.023] 2.011 I 386.88 164.32 363.02 188.81 2 L N J 363.02 188.81 362.32 189.53 2 L N J 380.47 165.93 381.05 168.44 384.81 164.93 379.89 163.43 4 Y N 380.47 165.93 381.05 168.44 384.81 164.93 379.89 163.43 4 Y V [1.971 3.942] 0.985 I 351.09 163.45 M 360 166.94 370.61 168.21 380.23 165.99 D N J 355.87 160.7 355.33 158.22 351.58 161.65 356.42 163.18 4 Y N 355.87 160.7 355.33 158.22 351.58 161.65 356.42 163.18 4 Y V [1.964 3.928] 0.982 I 385.3 163.12 M 374.86 160.7 365.35 158.61 356.12 160.65 D N J 501.34 208.18 501.34 190.72 2 L 2 Z N 511.92 208.18 511.92 190.72 2 L N 521.42 170.53 539.71 170.53 2 L 1 H N 521.42 181.11 539.71 181.11 2 L N 490.76 208.51 490.76 134.67 2 L 0.5 H N 501.34 149.7 501.34 134.9 2 L N 511.92 149.7 511.92 134.9 2 L N 462.67 159.95 539.33 159.95 2 L 2 H 0 Z N 463 170.53 482.12 170.53 2 L 1 H 2 Z N 463 181.11 482.12 181.11 2 L N J 494.5 187.13 492.67 185.34 491.4 190.31 496.34 188.92 4 Y 0.5 H 0 Z N 494.5 187.13 492.67 185.34 491.4 190.31 496.34 188.92 4 Y V J 520.14 160.81 494.68 186.95 2 L J 520.14 160.81 519.45 161.53 2 L N [2.029 4.058] 2.029 I 519.45 161.53 495.38 186.23 2 L N J 495.38 186.23 494.68 186.95 2 L N 1 9 Q (1 switch required) 469.08 113.18 T ( by bold wire) 475.32 103.36 T J (\050a\051 \322End\323 switch point) 326.14 123.91 T (\050b\051 \322Internal\323 switch point) 452.7 123 T 2 F (Figur) 331.51 87.47 T (e 5:) 352.85 87.47 T 1 F ( Switches required by a disjoint switch block at) 366.59 87.47 T 316 231/G1006719 FmPA (\050a\051 end and \050b\051 interior of wires.) 377.56 77.47 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (6 switches required) 331.76 113.57 T (by bold wires) 342.26 103.24 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 316.67 70.67 558 538 C 0 0 612 792 C 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.5/DEST FmPD2 0 791.99 0.01 791.99 C 0 0 612 792 C 367 237/M9.15588.Figure.Figure.5.Switches.required.by.a.disjoint.switch.block.at.a.end.and.b.interior.of.wir FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C 367 237/I1.1006721 FmPA 71 514/M9.23339.Heading3.732.Best.Single.Wire.Length FmPA 71 514/I1.1001303 FmPA 0 792 0.01 792 C 0 0 612 792 C 215 703/M9.22089.Figure.Figure.72.Circuit.speed.vs.switch.block.topology.Fc.and.routing.segment.length FmPA 0 792 0.01 792 C 0 0 612 792 C 215 703/I1.1010311 FmPA 0 792 0.01 792 C 0 0 612 792 C [/Rect[71 257 102 267]/Border[0 0 0]/Page 5/View[/XYZ null 215 703 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[264 167 295 177]/Border[0 0 0]/Page 5/View[/XYZ null 367 237 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[138 475 168 485]/Border[0 0 0]/Page 5/View[/XYZ null 215 703 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[93 361 124 371]/Border[0 0 0]/Page 5/View[/XYZ null 215 703 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[209 445 214 455]/Border[0 0 0]/Page 5/View[/XYZ null 215 703 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[53 405 84 415]/Border[0 0 0]/Page 5/View[/XYZ null 215 703 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 532 567 729]/ARTICLE FmPD2 [/Title(A)/Rect[44 62 304 547]/ARTICLE FmPD2 [/Title(A)/Rect[308 62 567 547]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "5" 5 %%Page: "6" 6 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 2 12 Q 0 X 0 0 0 1 0 0 0 K (5) 54 712 T (Experimental Results: T) 72 712 T (w) 199.44 712 T (o T) 207.98 712 T (ypes of W) 224.1 712 T (ir) 274.55 712 T (e) 283 712 T 54 856/G1000941 FmPA (Segment Ar) 72 698 T (chitectur) 132.77 698 T (es) 178.54 698 T 1 9 Q 0.02 (In this section we e) 72 682 P 0.02 (xamine some) 141.43 682 P 0.02 (what more comple) 188.98 682 P 0.02 (x architec-) 255.87 682 P 54 826/G1004594 FmPA 0.95 (tures: those that contain tw) 54 672 P 0.95 (o) 157.92 672 P 3 F 0.95 (types) 165.62 672 P 1 F 0.95 ( of wire se) 184.12 672 P 0.95 (gments. T) 224.58 672 P 0.95 (w) 264.02 672 P 0.95 (o wire) 270.42 672 P 0.8 (se) 54 662 P 0.8 (gments are of dif) 61.36 662 P 0.8 (ferent types if their lengths are dif) 124.76 662 P 0.8 (ferent, or if) 251.79 662 P 1.55 (the) 54 652 P 1.55 (y use dif) 64.86 652 P 1.55 (ferent types of routing switches to connect to other) 98.74 652 P (wires \050e.g. pass transistors vs. tri-state b) 54 642 T (uf) 197.55 642 T (fers\051.) 204.82 642 T 2 11 Q (5.1) 54 619.67 T (T) 75.6 619.67 T (ri-State Buffer Routing Switches Only) 82.12 619.67 T 54 764/G1004595 FmPA 1 9 Q 2.14 (W) 72 604 P 2.14 (e in) 79.78 604 P 2.14 (v) 94.8 604 P 2.14 (estig) 99.17 604 P 2.14 (ated a lar) 116.12 604 P 2.14 (ge number of architectures that con-) 153.22 604 P 54 748/G1000958 FmPA 0.54 (tained tw) 54 594 P 0.54 (o dif) 87.7 594 P 0.54 (ferent lengths of routing wires, and in which all the) 104.76 594 P 0.16 (switch block routing switches were tri-state b) 54 584 P 0.16 (uf) 218.23 584 P 0.16 (fers [6]. W) 225.5 584 P 0.16 (e found) 266.72 584 P 0.95 (that we could achie) 54 574 P 0.95 (v) 126.35 574 P 0.95 (e only small impro) 130.72 574 P 0.95 (v) 201.18 574 P 0.95 (ements compared to the) 205.54 574 P -0.06 (best single wire length architecture \050length = 4\051. T) 54 564 P -0.06 (able 2 compares) 235.76 564 P 0.29 (the performance of the tw) 54 554 P 0.29 (o best architectures e) 148.04 554 P 0.29 (xplored in this sec-) 224.51 554 P 0.65 (tion to the best single wire length architecture. Both these archi-) 54 544 P -0.01 (tectures are f) 54 534 P -0.01 (airly similar to an architecture in which all wires ha) 100.36 534 P -0.01 (v) 285.76 534 P -0.01 (e) 290.12 534 P 0.67 (length 4 \321 one has 25% length 2 wires and 75% length 8 wires,) 54 524 P 0.87 (while the other has 75% length 4 wires and 25% length 8 wires.) 54 514 P 0.84 (The a) 54 504 P 0.84 (v) 74.9 504 P 0.84 (erage speedup vs. a length 4 architecture is only 4.2% for) 79.27 504 P -0.13 (the \336rst architecture, and 4.9% for the second. Both of these archi-) 54 494 P 1.1 (tectures are slightly) 54 484 P 3 F 1.1 (less) 130.04 484 P 1 F 1.1 ( dense than an architecture that contains) 143.54 484 P 1.14 (only length 4 wires. Clearly length 4 wires pro) 54 474 P 1.14 (vide an ef) 234.08 474 P 1.14 (\336cient) 271.62 474 P (w) 54 464 T (ay to mak) 60.41 464 T (e both short and long connections!) 95.81 464 T 2 11 Q (5.2) 317.88 712.67 T (Length 4 Buffer) 339.48 712.67 T (ed W) 414.45 712.67 T (ir) 439 712.67 T (es Plus P) 446.74 712.67 T (ass-) 488.19 712.67 T 318 857/G1001036 FmPA (T) 339.48 699.67 T (ransistor) 346 699.67 T (-Switched W) 387.76 699.67 T (ir) 447.75 699.67 T (es) 455.5 699.67 T 1 9 Q 2.39 (Since a routing architecture composed solely of length 4) 335.88 684 P 318 828/G1001037 FmPA -0.14 (wires that use tri-state b) 317.88 674 P -0.14 (uf) 403.11 674 P -0.14 (fers as their routing switches performs so) 410.39 674 P 1.52 (well, in this section we in) 317.88 664 P 1.52 (v) 417.12 664 P 1.52 (estig) 421.49 664 P 1.52 (ate architectures in which some) 438.44 664 P 0.33 (routing tracks contain wires of this type. The other routing tracks) 317.88 654 P 0.57 (contain wires that connect to each other with pass transistor rout-) 317.88 644 P 0.34 (ing switches. W) 317.88 634 P 0.34 (e will in) 378.17 634 P 0.34 (v) 407.99 634 P 0.34 (estig) 412.36 634 P 0.34 (ate dif) 429.31 634 P 0.34 (ferent lengths of these \322pass-) 452.17 634 P 1.88 (transistor) 317.88 624 P 1.88 (-switched\323 wires, and dif) 351.2 624 P 1.88 (ferent proportions of the tw) 447.09 624 P 1.88 (o) 553.5 624 P (types of wires.) 317.88 614 T -0 (The solid line in Figure 6 sho) 335.88 600 P -0 (ws the speed achie) 441.64 600 P -0 (v) 508.64 600 P -0 (ed by FPGA) 513.01 600 P 318 744/G1010342 FmPA -0.05 (architectures in which 50% of the routing tracks use length 4 wires) 317.88 590 P -0.17 (connected by b) 317.88 580 P -0.17 (uf) 371.85 580 P -0.17 (fered switches, and the other 50% consist of some) 379.12 580 P 0.34 (other length of wires connected with pass transistors. The dashed) 317.88 570 P 0.51 (line in Figure 6 sho) 317.88 560 P 0.51 (ws the routing area required by each architec-) 389.71 560 P 0.09 (ture. The horizontal axis in Figure 6 is the length of the pass-tran-) 317.88 550 P 0.62 (sistor) 317.88 540 P 0.62 (-switched wires used. The best area-ef) 337.2 540 P 0.62 (\336cienc) 480.91 540 P 0.62 (y occurs when) 504.77 540 P 1.22 (the pass-transistor) 317.88 530 P 1.22 (-switched wires are length 2, b) 384.17 530 P 1.22 (ut length 4 and) 500.58 530 P 0.62 (length 8 wires also ha) 317.88 520 P 0.62 (v) 398.67 520 P 0.62 (e reasonable area-ef) 403.04 520 P 0.62 (\336cienc) 476.01 520 P 0.62 (y) 499.87 520 P 0.62 (, and the) 503.78 520 P 0.62 (y lead) 535.64 520 P (to superior speed.) 317.88 510 T 0.36 (Figures 7 and 8 in) 335.88 496 P 0.36 (v) 401.96 496 P 0.36 (estig) 406.33 496 P 0.36 (ate the performance of length 4 b) 423.28 496 P 0.36 (uf) 544.73 496 P 0.36 (f-) 552.01 496 P 318 640/G1010411 FmPA -0.11 (ered wires combined with either length 1, 2, 4, or 8 pass-transistor) 317.88 486 P -0.11 (-) 555 486 P 0.16 (switched wires in dif) 317.88 476 P 0.16 (ferent proportions, \050i.e. not just 50 / 50\051. The) 393.36 476 P 1.66 (horizontal axis in these \336gures is the fraction of routing tracks) 317.88 466 P 0.8 (composed of the pass-transistor) 317.88 456 P 0.8 (-switched wires; the remainder of) 433.83 456 P 0.83 (the routing tracks are composed of length 4 b) 317.88 446 P 0.83 (uf) 487.28 446 P 0.83 (fered wires. The) 494.55 446 P 1.82 (\3220\323 point on the horizontal axis corresponds to an architecture) 317.88 436 P 1.13 (composed solely of length 4 b) 317.88 426 P 1.13 (uf) 431.6 426 P 1.13 (fered wires, while the \3221\323 point) 438.87 426 P -0.1 (corresponds to architectures composed solely of wires that connect) 317.88 416 P 0.22 (to each other via pass transistors. Figure 7 sho) 317.88 406 P 0.22 (ws the speed of the) 488.13 406 P 2.2 (v) 317.88 396 P 2.2 (arious architectures, while Figure 8 sho) 322.15 396 P 2.2 (ws their routing area.) 474.91 396 P -0.06 (Clearly) 317.88 386 P -0.06 (, adding length 1 wires to an architecture is not a good idea.) 343.79 386 P 0.73 (If 33% of the routing tracks are length 1 pass-transistor) 317.88 376 P 0.73 (-switched) 523.01 376 P 1.28 (wires, then area-ef) 317.88 366 P 1.28 (\336cienc) 386.94 366 P 1.28 (y impro) 410.8 366 P 1.28 (v) 440.2 366 P 1.28 (es by 8% \050vs. all tracks being) 444.56 366 P 0.53 (length 4 b) 317.88 356 P 0.53 (uf) 354.76 356 P 0.53 (fered wires\051, b) 362.03 356 P 0.53 (ut speed de) 415.14 356 P 0.53 (grades by 7%. Lar) 456.56 356 P 0.53 (ger frac-) 526.74 356 P 0.15 (tions of length 1 wires de) 317.88 346 P 0.15 (grade both area and speed \321 these wires) 409.74 346 P 0.55 (are simply too short to be of much use. Man) 317.88 336 P 0.55 (y commercial archi-) 484.43 336 P -0.11 (tectures mak) 317.88 326 P -0.11 (e hea) 363.42 326 P -0.11 (vy use of length 1 wires [3, 4, 33], b) 381.87 326 P -0.11 (ut our results) 511.21 326 P -0.04 (suggest the) 317.88 316 P -0.04 (y could impro) 357.96 316 P -0.04 (v) 408.25 316 P -0.04 (e both their speed and area-ef) 412.62 316 P -0.04 (\336cienc) 518.43 316 P -0.04 (y by) 542.28 316 P 1.79 (using longer wires instead. Note that the most widely studied) 317.88 306 P 3.91 (architecture in academic research, an architecture composed) 317.88 296 P 2.91 (entirely of length 1 wires connected by pass transistors, has) 317.88 286 P 1.69 (e) 317.88 276 P 1.69 (xtremely poor speed \321 it is 2.8 times slo) 321.74 276 P 1.69 (wer than the f) 483.29 276 P 1.69 (astest) 538 276 P (architecture in Figure 7.) 317.88 266 T 2 F -0.06 (T) 55.61 447 P -0.06 (able 2:) 60.78 447 P 1 F -0.06 ( Best b) 86.47 447 P -0.06 (uf) 113.37 447 P -0.06 (fered, tw) 120.64 447 P -0.06 (o dif) 152.48 447 P -0.06 (ferent length architectures vs. best) 168.94 447 P 54 591/G1006791 FmPA (single-length architecture \05020 circuit a) 90.87 437 T (v) 228.15 437 T (erage\051.) 232.52 437 T (Architecture) 60.16 395 T 54 539/G1006797 FmPA (Critical) 116.61 410 T 111 554/G1006799 FmPA (P) 122.17 400 T (ath) 127.04 400 T (Delay) 119.36 390 T (\050ns\051) 123.11 380 T (Speedup) 157.47 410 T 149 554/G1006825 FmPA (vs. Length) 153.97 400 T -0.35 (4, Buf) 152.58 390 P -0.35 (fered) 174.51 390 P (FPGA) 161.46 380 T (Routing) 206.66 420 T 197 564/G1006801 FmPA (Area) 212.42 410 T (\050Minimum-) 200.16 400 T (W) 210.1 390 T (idth) 218.23 390 T (T) 203.08 380 T (ransistor) 208.26 380 T (Areas\051) 209.17 370 T (Routing) 255.21 415 T 245 559/G1006835 FmPA (Area vs.) 254.72 405 T (Length 4,) 252.47 395 T (Buf) 253.84 385 T (fered) 267.11 385 T (FPGA) 258.21 375 T (All length 4,) 56.13 353 T 54 497/G1006803 FmPA (b) 56.13 343 T (uf) 60.45 343 T (fered) 67.72 343 T (45.57) 119.98 349 T 111 493/G1006805 FmPA (\321) 168.46 349 T 149 493/G1006827 FmPA (5901) 212.17 349 T 197 493/G1006807 FmPA (\321) 265.22 349 T 245 493/G1006837 FmPA (25% length 2,) 56.13 330 T 54 474/G1006809 FmPA (75% length 8) 56.13 320 T (43.74) 119.98 325 T 111 469/G1006811 FmPA (+4.2%) 161.05 325 T 149 469/G1006829 FmPA (6034) 212.17 325 T 197 469/G1006813 FmPA (+2.3%) 257.8 325 T 245 469/G1006839 FmPA (75% length 4,) 56.13 307 T 54 451/G1006815 FmPA (25% length 8) 56.13 297 T (43.44) 119.98 302 T 111 446/G1006817 FmPA (+4.9%) 161.05 302 T 149 446/G1006831 FmPA (5948) 212.17 302 T 197 446/G1006819 FmPA (+0.8%) 257.8 302 T 245 446/G1006841 FmPA 54.13 429.75 54.13 292.25 2 L V 0.5 H 0 Z N 111.18 430.25 111.18 291.75 2 L V N 149.04 430.25 149.04 291.75 2 L V N 196.89 430.25 196.89 291.75 2 L V N 245.44 430.25 245.44 291.75 2 L V N 293.99 429.75 293.99 292.25 2 L V N 53.88 430 294.24 430 2 L V N 54.38 364.25 293.74 364.25 2 L V N 54.38 361.75 293.74 361.75 2 L V N 53.88 338 294.24 338 2 L V 2 H N 53.88 315 294.24 315 2 L V 0.5 H N 53.88 292 294.24 292 2 L V N 54 72 558 250.33 C 54 72 558 250.33 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 76 611 537 781 414.9 153 99.72 88.78 FMBEGINEPSF %%BeginDocument: /jayar/d0/vaughn/thesis/place/fpga99/grap/area_delay_50p_50l4buf.eps %!PS-Adobe-2.0 EPSF-1.2 %%Title: stdin (ditroff) %%Creator: gractus.eecg:vaughn (Vaughn Betz,EECG,LP 392,1653,7662197,G,G ) %%CreationDate: Wed Sep 30 15:01:04 1998 %%For:vaughn vaughn %%Pages: 1 %%DocumentFonts: Times-Italic Times-BoldItalic Helvetica DIThacks Symbol Courier Helvetica-Bold Times-Roman Times-Bold Courier-Bold %%BoundingBox: 76 611 537 781 %%EndProlog %%Page 1 1 %! % Start of psdit.pro -- prolog for ditroff translator % Copyright (c) 1985,1987 Adobe Systems Incorporated. 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gsave /cf currentfont def cf fractm makefont setfont 0 .3 dm 2 copy neg rmoveto fnum show rmoveto currentfont cf setfont(\244)show setfont fden show grestore ditwid 0 rmoveto} def /oce {grestore ditwid 0 rmoveto}def /dm {ditsiz mul}def /ocprocs 50 dict def ocprocs begin (14){(1)(4)fraction}def (12){(1)(2)fraction}def (34){(3)(4)fraction}def (13){(1)(3)fraction}def (23){(2)(3)fraction}def (18){(1)(8)fraction}def (38){(3)(8)fraction}def (58){(5)(8)fraction}def (78){(7)(8)fraction}def (sr){gsave .05 dm .16 dm rmoveto(\326)show oce}def (is){gsave 0 .15 dm rmoveto(\362)show oce}def (->){gsave 0 .02 dm rmoveto(\256)show oce}def (<-){gsave 0 .02 dm rmoveto(\254)show oce}def (==){gsave 0 .05 dm rmoveto(\272)show oce}def end % DIThacks fonts for some special chars 50 dict dup begin /FontType 3 def /FontName /DIThacks def /FontMatrix [.001 0.0 0.0 .001 0.0 0.0] def /FontBBox [-220 -280 900 900] def% a lie but ... /Encoding 256 array def 0 1 255{Encoding exch /.notdef put}for Encoding dup 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/CharProcs 50 dict def CharProcs begin /space{}def /.notdef{}def /ru{500 0 rls}def /rn{0 750 moveto 500 0 rls}def /vr{20 800 moveto 0 -770 rls}def /bv{20 800 moveto 0 -1000 rls}def /br{20 770 moveto 0 -1040 rls}def /ul{0 -250 moveto 500 0 rls}def /ob{200 250 rmoveto currentpoint newpath 200 0 360 arc closepath stroke}def /bu{200 400 rmoveto currentpoint newpath 200 0 360 arc closepath fill}def /sq{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath stroke}def /bx{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath fill}def /ci{355 333 rmoveto currentpoint newpath 333 0 360 arc 50 setlinewidth stroke}def /lt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 add exch s4 a4p stroke}def /lb{20 800 moveto 0 -550 rlineto currx -200 2cx s4 add exch s4 a4p stroke}def /rt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 sub exch s4 a4p stroke}def /rb{20 800 moveto 0 -500 rlineto currx -200 2cx s4 sub exch s4 a4p stroke}def /lk{20 800 moveto 20 300 -280 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /rk{20 800 moveto 20 300 320 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /lf{20 800 moveto 0 -1000 rlineto s4 0 rls}def /rf{20 800 moveto 0 -1000 rlineto s4 neg 0 rls}def /lc{20 -200 moveto 0 1000 rlineto s4 0 rls}def /rc{20 -200 moveto 0 1000 rlineto s4 neg 0 rls}def end /Metrics 50 dict def Metrics begin /.notdef 0 def /space 500 def /ru 500 def /br 0 def /lt 250 def /lb 250 def /rt 250 def /rb 250 def /lk 250 def /rk 250 def /rc 250 def /lc 250 def /rf 250 def /lf 250 def /bv 250 def /ob 350 def /bu 350 def /ci 750 def /bx 750 def /sq 750 def /rn 500 def /ul 500 def /vr 0 def end DITfd begin /s2 500 def /s4 250 def /s3 333 def /a4p{arcto pop pop pop pop}def /2cx{2 copy exch}def /rls{rlineto stroke}def /currx{currentpoint pop}def /dround{transform round exch round exch itransform} def end end /DIThacks exch definefont pop ditstart (psc)xT 576 1 1 xr 1(Times-Roman)xf 1 f 2(Times-Italic)xf 2 f 3(Times-Bold)xf 3 f 4(Times-BoldItalic)xf 4 f 5(Helvetica)xf 5 f 6(Helvetica-Bold)xf 6 f 7(Courier)xf 7 f 8(Courier-Bold)xf 8 f 9(Symbol)xf 9 f 10(DIThacks)xf 10 f 10 s 1 f xi 10 s 0 xH 0 xS 1 f 1582 1248 MXY 0 -1152 Dl 1900 0 Dl 3483 MX 0 1152 Dl -1900 0 Dl 1700 1429(Length)N 1947(of)X 2034(Pass-Transistor-Switched)X 2873(Wire)X 3054(Segments)X 723 448(Routing)N 1000(Area)X 737 544(\(Min.-Width)N 778 640(Transistor)N 833 736(Areas\))N 766 832(\(20)N 893(Circuit)X 607 928(Arithmetic)N 974(Average\))X 3771 544(Critical)N 4031(Path)X 3910 640(\(ns\))N 3798 736(\(20)N 3925(Circuit)X 3643 832(Geometric)N 4002(Average\))X 1749 1248 MXY 0 -57 Dl 1729 1336(1)N 2075 1248 MXY 0 -57 Dl 2055 1336(2)N 2400 1248 MXY 0 -57 Dl 2380 1336(4)N 2726 1248 MXY 0 -57 Dl 2706 1336(8)N 3052 1248 MXY 0 -57 Dl 3012 1336(16)N 3378 1248 MXY 0 -57 Dl 3294 1336(Long)N 1582 1176 MXY 57 0 Dl 1402 1192(5000)N 1582 1032 MXY 57 0 Dl 1402 1048(5200)N 1582 888 MXY 57 0 Dl 1402 904(5400)N 1582 744 MXY 57 0 Dl 1402 760(5600)N 1582 600 MXY 57 0 Dl 1402 616(5800)N 1582 456 MXY 57 0 Dl 1402 472(6000)N 1582 312 MXY 57 0 Dl 1402 328(6200)N 1582 168 MXY 57 0 Dl 1402 184(6400)N 3483 1165 MXY -57 0 Dl 3503 1181(42)N 3483 1000 MXY -57 0 Dl 3503 1016(44)N 3483 836 MXY -57 0 Dl 3503 852(46)N 3483 672 MXY -57 0 Dl 3503 688(48)N 3483 507 MXY -57 0 Dl 3503 523(50)N 3483 343 MXY -57 0 Dl 3503 359(52)N 3483 178 MXY -57 0 Dl 3503 194(54)N 5 s 10 f 1742 842(g)N 10 s 1749 826 MXY 22 17 Dl 1793 860 MXY 22 17 Dl 1836 894 MXY 22 17 Dl 1879 929 MXY 22 17 Dl 1922 963 MXY 22 17 Dl 1966 998 MXY 22 17 Dl 2009 1032 MXY 22 17 Dl 2052 1066 MXY 22 17 Dl 5 s 2068 1100(g)N 10 s 2075 1084 MXY 28 -5 Dl 2134 1071 MXY 28 -5 Dl 2194 1059 MXY 28 -5 Dl 2253 1046 MXY 28 -5 Dl 2313 1034 MXY 28 -5 Dl 2373 1021 MXY 28 -5 Dl 5 s 2393 1031(g)N 10 s 2400 1015 MXY 26 -11 Dl 2450 993 MXY 26 -11 Dl 2500 970 MXY 26 -11 Dl 2550 949 MXY 26 -11 Dl 2600 926 MXY 26 -11 Dl 2650 904 MXY 26 -11 Dl 2700 882 MXY 26 -11 Dl 5 s 2719 886(g)N 10 s 2726 870 MXY 26 -11 Dl 2776 849 MXY 26 -11 Dl 2826 827 MXY 26 -11 Dl 2876 806 MXY 26 -11 Dl 2926 784 MXY 26 -11 Dl 2976 763 MXY 26 -11 Dl 3025 741 MXY 26 -11 Dl 5 s 3045 746(g)N 10 s 3052 730 MXY 14 -24 Dl 3083 680 MXY 14 -24 Dl 3114 630 MXY 14 -24 Dl 3145 580 MXY 14 -24 Dl 3176 530 MXY 14 -24 Dl 3207 480 MXY 14 -24 Dl 3238 430 MXY 14 -24 Dl 3269 381 MXY 14 -24 Dl 3300 331 MXY 14 -24 Dl 3331 281 MXY 14 -24 Dl 3362 231 MXY 14 -24 Dl 5 s 3371 223(g)N 1742 304(g)N 10 s 1749 288 MXY 325 574 Dl 5 s 2068 878(g)N 10 s 2075 862 MXY 325 238 Dl 5 s 2393 1117(g)N 10 s 2400 1101 MXY 325 43 Dl 5 s 2719 1160(g)N 10 s 2726 1144 MXY 325 -40 Dl 5 s 3045 1120(g)N 10 s 3052 1104 MXY 325 -399 Dl 5 s 3371 720(g)N 1 p xt xs %%Trailer %%EOF %%EndDocument FMENDEPSF 2 9 Q 0 X 0 0 0 1 0 0 0 K (Figur) 122.36 76.4 T (e 6:) 143.7 76.4 T 1 F ( Comparison of FPGAs with 50% length 4 b) 157.44 76.4 T (uf) 319.51 76.4 T (fered and 50% pass-transistor) 326.78 76.4 T (-switched wires.) 433.33 76.4 T 54 220/G1010360 FmPA (Critical) 246.27 190.47 T (Routing) 360.27 199.47 T (area) 366.27 190.47 T ( path) 250.77 181.47 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 54 72 558 250.33 C 0 0 612 792 C 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.6/DEST FmPD2 86 597/M9.29923.TableTitle.Table.74.Best.buffered.two.different.length.architectures.vs.best.singlelength.a FmPA 86 597/I1.1006790 FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C 157 226/M9.36771.Figure.Figure.77.Speed.of.architectures.with.50.length.4.buffered.and.50.passtransistor.wir FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C 157 226/I1.1010359 FmPA 339 864/M9.11029.Heading3.742.Length.4.Buffered.Wires.Plus.PassTransistor.Switched.Wires FmPA 339 864/I1.1001340 FmPA 72 864/M9.10729.Heading2.74.Two.Types.of.Wire.Segment.Architectures FmPA 72 864/I1.1001604 FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[397 597 427 607]/Border[0 0 0]/Page 6/View[/XYZ null 157 226 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[344 557 375 567]/Border[0 0 0]/Page 6/View[/XYZ null 157 226 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[420 547 450 557]/Border[0 0 0]/Page 6/View[/XYZ null 157 226 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 792 C 0 0 612 792 C [/Rect[365 493 370 503]/Border[0 0 0]/Page 7/View[/XYZ null 91 509 FmDC exch pop null]/LNK FmPD [/Rect[244 581 249 591]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[231 561 257 571]/Border[0 0 0]/Page 6/View[/XYZ null 86 597 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[388 493 393 503]/Border[0 0 0]/Page 7/View[/XYZ null 94 237 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 792 C 0 0 612 792 C [/Rect[443 403 473 413]/Border[0 0 0]/Page 7/View[/XYZ null 91 509 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[426 393 458 403]/Border[0 0 0]/Page 7/View[/XYZ null 94 237 FmDC exch pop null]/LNK FmPD [/Rect[473 323 477 333]/Border[0 0 0]/Page 10/View[/XYZ null 74 702 FmDC exch pop null]/LNK FmPD [/Rect[482 323 486 333]/Border[0 0 0]/Page 10/View[/XYZ null 74 689 FmDC exch pop null]/LNK FmPD [/Rect[491 323 500 333]/Border[0 0 0]/Page 10/View[/XYZ null 338 396 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 792 C 0 0 612 792 C [/Rect[372 263 402 273]/Border[0 0 0]/Page 7/View[/XYZ null 91 509 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 248 567 729]/ARTICLE FmPD2 [/Title(A)/Rect[45 63 567 259]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "6" 6 %%Page: "7" 7 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 1 9 Q 0 X 0 0 0 1 0 0 0 K 0.89 (Adding longer pass-transistor) 72 323.3 P 0.89 (-switched wires to an architec-) 180.09 323.3 P 54 467/G1001170 FmPA 1.17 (ture yields better results. Figure 7 sho) 54 313.3 P 1.17 (ws that making between) 203.37 313.3 P 0.48 (17% and 83% of the routing tracks pass-transistor) 54 303.3 P 0.48 (-switched wires) 236.9 303.3 P 0.1 (of length 4 or 8 increases the FPGA speed. P) 54 293.3 P 0.1 (ass transistors do not) 218.58 293.3 P 0.33 (ha) 54 283.3 P 0.33 (v) 62.32 283.3 P 0.33 (e the intrinsic delay of the multi-stage b) 66.68 283.3 P 0.33 (uf) 212.04 283.3 P 0.33 (fers used in b) 219.31 283.3 P 0.33 (uf) 268.36 283.3 P 0.33 (fered) 275.63 283.3 P 1.27 (routing switches, and the) 54 273.3 P 1.27 (y ha) 147.67 273.3 P 1.27 (v) 164.01 273.3 P 1.27 (e higher dri) 168.37 273.3 P 1.27 (v) 212.18 273.3 P 1.27 (e strength than a tri-) 216.55 273.3 P 0.89 (state b) 317.88 714 P 0.89 (uf) 341.84 714 P 0.89 (fer for the same area, since the) 349.11 714 P 0.89 (y use only one transistor) 464.54 714 P 0.89 (,) 555.75 714 P 0.5 (rather than se) 317.88 704 P 0.5 (v) 367.14 704 P 0.5 (eral. On the other hand, the delay through a series) 371.51 704 P 1.07 (chain of pass transistors gro) 317.88 694 P 1.07 (ws quadratically with the number of) 422.42 694 P 0.44 (pass transistors. The net ef) 317.88 684 P 0.44 (fect is that pass transistor switches are) 417.86 684 P 0.89 (f) 317.88 674 P 0.89 (aster than b) 320.79 674 P 0.89 (uf) 363.88 674 P 0.89 (fers for connections that pass through a fe) 371.15 674 P 0.89 (w series) 527.87 674 P 0.98 (switches, b) 317.88 664 P 0.98 (ut b) 358.68 664 P 0.98 (uf) 373.23 664 P 0.98 (fers are f) 380.51 664 P 0.98 (aster for connections that pass through) 414.36 664 P 0.34 (man) 317.88 654 P 0.34 (y series switches. If long wires are used, fe) 333.24 654 P 0.34 (wer series routing) 492.83 654 P 0.86 (switches are needed for long connections, making pass transistor) 317.88 644 P 1.85 (switches more competiti) 317.88 634 P 1.85 (v) 409.34 634 P 1.85 (e with b) 413.7 634 P 1.85 (uf) 446.22 634 P 1.85 (fers for longer connections.) 453.49 634 P 1.82 (Consequently a mix of moderate length b) 317.88 624 P 1.82 (uf) 477.61 624 P 1.82 (fered and moderate) 484.89 624 P 1.71 (length pass-transistor wires leads to better speed than using all) 317.88 614 P (b) 317.88 604 T (uf) 322.2 604 T (fered routing switches or all pass transistor routing switches.) 329.47 604 T 0.79 (Figure 8 sho) 335.88 590 P 0.79 (ws that increasing the fraction of routing tracks) 382.24 590 P 318 734/G1001069 FmPA 1.37 (using length 2, 4 or 8 pass-transistor wires impro) 317.88 580 P 1.37 (v) 504.9 580 P 1.37 (es the FPGA) 509.27 580 P -0.1 (area-ef) 317.88 570 P -0.1 (\336cienc) 342.63 570 P -0.1 (y until this fraction reaches approximately 83%; after) 366.49 570 P 0.41 (that area-ef) 317.88 560 P 0.41 (\336cienc) 358.79 560 P 0.41 (y de) 382.65 560 P 0.41 (grades \050or le) 398.17 560 P 0.41 (v) 443.75 560 P 0.41 (els of) 448.12 560 P 0.41 (f, for length 4 wires\051. A) 468.05 560 P 0.42 (pass transistor switch requires less area than a tri-state b) 317.88 550 P 0.42 (uf) 523.18 550 P 0.42 (fer) 530.45 550 P 0.42 (, and) 540.08 550 P 2.24 (since pass transistors are bidirectional, one pass transistor can) 317.88 540 P -0.07 (replace tw) 317.88 530 P -0.07 (o tri-state b) 354.95 530 P -0.07 (uf) 395.63 530 P -0.07 (fers in the routing. On the other hand, pass) 402.9 530 P 0.44 (transistor switches are not well-suited to routing high-f) 317.88 520 P 0.44 (anout nets.) 518.57 520 P -0 (T) 317.88 510 P -0 (o maintain reasonable speed, a high-f) 322.66 510 P -0 (anout net routed using pass-) 457.02 510 P 1.15 (transistor switches tends to use a \322star\323 topology) 317.88 500 P 1.15 (. This requires) 500.56 500 P 0.14 (more wiring, and hence more routing tracks, and hence more area.) 317.88 490 P 2.25 (Making all routing switches pass transistors forces e) 317.88 480 P 2.25 (v) 521.64 480 P 2.25 (en high-) 526 480 P 0.12 (f) 317.88 470 P 0.12 (anout nets to be routed using pass transistors, de) 320.79 470 P 0.12 (grading area-ef) 495.38 470 P 0.12 (\336-) 550 470 P (cienc) 317.88 460 T (y) 336.73 460 T (.) 340.65 460 T 1.24 (Considering both area and speed, the best architectures use) 335.88 446 P 318 590/G1006893 FmPA 0.12 (50% - 83% pass-transistor switched wires of length 4 or 8. Archi-) 317.88 436 P 0.71 (tectures with 50% pass-transistor) 317.88 426 P 0.71 (-switched wires achie) 439.06 426 P 0.71 (v) 518.22 426 P 0.71 (e the best) 522.59 426 P 4.35 (speed, while those with 83% pass-transistor) 317.88 416 P 4.35 (-switched wires) 496.92 416 P 0.59 (achie) 317.88 406 P 0.59 (v) 336.64 406 P 0.59 (e the best area-ef) 341.01 406 P 0.59 (\336cienc) 403.77 406 P 0.59 (y) 427.62 406 P 0.59 (. A major conclusion to be dra) 431.54 406 P 0.59 (wn) 547 406 P 0.41 (from these results is simply that the best routing architecture con-) 317.88 396 P 0.09 (tains a mix of pass transistors and tri-state b) 317.88 386 P 0.09 (uf) 476.39 386 P 0.09 (fers. This f) 483.66 386 P 0.09 (act is not) 525.33 386 P 1.27 (widely kno) 317.88 376 P 1.27 (wn. Prior academic research has focused on FPGAs) 359.17 376 P 0.03 (that contain only pass transistors, while a ne) 317.88 366 P 0.03 (w FPGA compan) 476.82 366 P 0.03 (y has) 539.23 366 P 1.72 (made the f) 317.88 356 P 1.72 (act that their FPGAs contain no pass transistors \050all) 359.23 356 P (routing switches are tri-state b) 317.88 346 T (uf) 426.68 346 T (fers\051 a mark) 433.95 346 T (eting feature [34].) 477.34 346 T 2 11 Q (5.3) 317.88 323.67 T (Length 8 Buffer) 339.48 323.67 T (ed W) 414.45 323.67 T (ir) 439 323.67 T (es Plus P) 446.74 323.67 T (ass-) 488.19 323.67 T 318 468/G1001298 FmPA (T) 339.48 310.67 T (ransistor) 346 310.67 T (-Switched W) 387.76 310.67 T (ir) 447.75 310.67 T (es) 455.5 310.67 T 1 9 Q 0.87 (W) 335.88 295 P 0.87 (e ha) 343.66 295 P 0.87 (v) 359.09 295 P 0.87 (e found that combining length 8 b) 363.45 295 P 0.87 (uf) 490.5 295 P 0.87 (fered wires with) 497.77 295 P 318 439/G1001296 FmPA 1.87 (some pass-transistor) 317.88 285 P 1.87 (-switched wires also results in good FPGA) 392.81 285 P 1.13 (architectures. Using length 8 b) 317.88 275 P 1.13 (uf) 435.84 275 P 1.13 (fered wires instead of length 4) 443.11 275 P 1.18 (b) 317.88 265 P 1.18 (uf) 322.2 265 P 1.18 (fered wires slightly increases the FPGA speed, at the cost of) 329.47 265 P 2.36 (slightly decreased area-ef) 317.88 255 P 2.36 (\336cienc) 414.33 255 P 2.36 (y) 438.19 255 P 2.36 (. Otherwise, the architectural) 442.1 255 P 2.02 (conclusions we found when combining pass-transistor) 317.88 245 P 2.02 (-switched) 523.01 245 P 0.39 (wires with length 8 b) 317.88 235 P 0.39 (uf) 395.27 235 P 0.39 (fered wires are v) 402.54 235 P 0.39 (ery similar to those of the) 463.8 235 P (pre) 317.88 225 T (vious section:) 329.15 225 T (1.) 332.28 211 T 0.96 (The best combination of area and delay results when the) 346.68 211 P 318 355/G1001326 FmPA (pass-transistor switched wires are of length 4 or 8.) 346.68 200 T (2.) 332.28 185 T -0.08 (The best architectures contain from 50% to 83% pass-tran-) 346.68 185 P 318 329/G1001330 FmPA -0.17 (sistor switched routing tracks, with the 50% pass-transistor) 346.68 175 P 0.04 (architectures gi) 346.68 165 P 0.04 (ving the best speed, and the 83% pass-tran-) 401.73 165 P (sistor architectures yielding the best area-ef) 346.68 155 T (\336cienc) 503.16 155 T (y) 527.02 155 T (.) 530.94 155 T 2 12 Q (6) 317.88 131 T (Ov) 335.88 131 T (erall Ar) 351.1 131 T (chitectur) 391.2 131 T (e Comparison) 436.97 131 T 318 275/G1002641 FmPA 1 9 Q 1.85 (In the pre) 335.88 115 P 1.85 (vious sections we ha) 373.85 115 P 1.85 (v) 453.47 115 P 1.85 (e e) 457.83 115 P 1.85 (xamined FPGA routing) 469.79 115 P 318 259/G1004638 FmPA 1.66 (architectures of gradually increasing comple) 317.88 105 P 1.66 (xity and look) 484.36 105 P 1.66 (ed for) 535.1 105 P 2.48 (important architectural trends by v) 317.88 95 P 2.48 (arying the k) 452.06 95 P 2.48 (e) 499.92 95 P 2.48 (y architectural) 503.79 95 P 0.31 (parameters. In this section we pro) 317.88 85 P 0.31 (vide an o) 443.3 85 P 0.31 (v) 476.77 85 P 0.31 (ervie) 481.13 85 P 0.31 (w by comparing) 498.9 85 P 1.1 (some of the best architectures we ha) 317.88 75 P 1.1 (v) 454.79 75 P 1.1 (e found ag) 459.15 75 P 1.1 (ainst each other) 499.31 75 P 54 72 294.12 720 C 54 333.3 293.76 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 56 599 289 769 209.7 153 82.92 565.33 FMBEGINEPSF %%BeginDocument: /jayar/d0/vaughn/thesis/place/fpga99/grap/Tcrit_pass_l4buf.eps %!PS-Adobe-2.0 EPSF-1.2 %%Title: stdin (ditroff) %%Creator: gractus.eecg:vaughn (Vaughn Betz,EECG,LP 392,1653,7662197,G,G ) %%CreationDate: Thu Dec 3 18:00:02 1998 %%For:vaughn vaughn %%Pages: 1 %%DocumentFonts: Times-Italic Times-BoldItalic Helvetica DIThacks Symbol Courier Helvetica-Bold Times-Roman Times-Bold Courier-Bold %%BoundingBox: 56 599 289 769 %%EndProlog %%Page 1 1 %! % Start of psdit.pro -- prolog for ditroff translator % Copyright (c) 1985,1987 Adobe Systems Incorporated. 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/fontnum 1 def /fontsize 10 def /fontheight 10 def /fontslant 0 def /xi {0 72 11 mul translate 72 resolution div dup neg scale 0 0 moveto /fontnum 1 def /fontsize 10 def /fontheight 10 def /fontslant 0 def F /pagesave save def}def /PB{save /psv exch def currentpoint translate resolution 72 div dup neg scale 0 0 moveto}def /PE{psv restore}def /m1 matrix def /m2 matrix def /m3 matrix def /oldmat matrix def /tan{dup sin exch cos div}bind def /point{resolution 72 div mul}bind def /dround {transform round exch round exch itransform}bind def /xT{/devname exch def}def /xr{/mh exch def /my exch def /resolution exch def}def /xp{}def /xs{docsave restore end}def /xt{}def /xf{/fontname exch def /slotno exch def fontnames slotno get fontname eq not {fonts slotno fontname findfont put fontnames slotno fontname put}if}def /xH{/fontheight exch def F}bind def /xS{/fontslant exch def F}bind def /s{/fontsize exch def /fontheight fontsize def F}bind def /f{/fontnum exch def F}bind def /F{fontheight 0 le {/fontheight fontsize def}if fonts fontnum get fontsize point 0 0 fontheight point neg 0 0 m1 astore fontslant 0 ne{1 0 fontslant tan 1 0 0 m2 astore m3 concatmatrix}if makefont setfont .04 fontsize point mul 0 dround pop setlinewidth}bind def /X{exch currentpoint exch pop moveto show}bind def /N{3 1 roll moveto show}bind def /Y{exch currentpoint pop exch moveto show}bind def /S /show load def /ditpush{}def/ditpop{}def /AX{3 -1 roll currentpoint exch pop moveto 0 exch ashow}bind def /AN{4 2 roll moveto 0 exch ashow}bind def /AY{3 -1 roll currentpoint pop exch moveto 0 exch ashow}bind def /AS{0 exch ashow}bind def /MX{currentpoint exch pop moveto}bind def /MY{currentpoint pop exch moveto}bind def /MXY /moveto load def /cb{pop}def % action on unknown char -- nothing for now /n{}def/w{}def /p{pop showpage pagesave restore /pagesave save def}def /abspoint{currentpoint exch pop add exch currentpoint pop add exch}def /dstroke{currentpoint stroke moveto}bind def /Dl{2 copy gsave rlineto stroke grestore rmoveto}bind def /arcellipse{oldmat currentmatrix pop currentpoint translate 1 diamv diamh div scale /rad diamh 2 div def rad 0 rad -180 180 arc oldmat setmatrix}def /Dc{gsave dup /diamv exch def /diamh exch def arcellipse dstroke grestore diamh 0 rmoveto}def /De{gsave /diamv exch def /diamh exch def arcellipse dstroke grestore diamh 0 rmoveto}def /Da{currentpoint /by exch def /bx exch def /fy exch def /fx exch def /cy exch def /cx exch def /rad cx cx mul cy cy mul add sqrt def /ang1 cy neg cx neg atan def /ang2 fy fx atan def cx bx add cy by add 2 copy rad ang1 ang2 arcn stroke exch fx add exch fy add moveto}def /Barray 200 array def % 200 values in a wiggle /D~{mark}def /D~~{counttomark Barray exch 0 exch getinterval astore /Bcontrol exch def pop /Blen Bcontrol length def Blen 4 ge Blen 2 mod 0 eq and {Bcontrol 0 get Bcontrol 1 get abspoint /Ycont exch def /Xcont exch def Bcontrol 0 2 copy get 2 mul put Bcontrol 1 2 copy get 2 mul put Bcontrol Blen 2 sub 2 copy get 2 mul put Bcontrol Blen 1 sub 2 copy get 2 mul put /Ybi /Xbi currentpoint 3 1 roll def def 0 2 Blen 4 sub {/i exch def Bcontrol i get 3 div Bcontrol i 1 add get 3 div Bcontrol i get 3 mul Bcontrol i 2 add get add 6 div Bcontrol i 1 add get 3 mul Bcontrol i 3 add get add 6 div /Xbi Xcont Bcontrol i 2 add get 2 div add def /Ybi Ycont Bcontrol i 3 add get 2 div add def /Xcont Xcont Bcontrol i 2 add get add def /Ycont Ycont Bcontrol i 3 add get add def Xbi currentpoint pop sub Ybi currentpoint exch pop sub rcurveto }for dstroke}if}def end /ditstart{$DITroff begin /nfonts 60 def % NFONTS makedev/ditroff dependent! /fonts[nfonts{0}repeat]def /fontnames[nfonts{()}repeat]def /docsave save def }def % character outcalls /oc {/pswid exch def /cc exch def /name exch def /ditwid pswid fontsize mul resolution mul 72000 div def /ditsiz fontsize resolution mul 72 div def ocprocs name known{ocprocs name get exec}{name cb} ifelse}def /fractm [.65 0 0 .6 0 0] def /fraction {/fden exch def /fnum exch def gsave /cf currentfont def cf fractm makefont setfont 0 .3 dm 2 copy neg rmoveto fnum show rmoveto currentfont cf setfont(\244)show setfont fden show grestore ditwid 0 rmoveto} def /oce {grestore ditwid 0 rmoveto}def /dm {ditsiz mul}def /ocprocs 50 dict def ocprocs begin (14){(1)(4)fraction}def (12){(1)(2)fraction}def (34){(3)(4)fraction}def (13){(1)(3)fraction}def (23){(2)(3)fraction}def (18){(1)(8)fraction}def (38){(3)(8)fraction}def (58){(5)(8)fraction}def (78){(7)(8)fraction}def (sr){gsave .05 dm .16 dm rmoveto(\326)show oce}def (is){gsave 0 .15 dm rmoveto(\362)show oce}def (->){gsave 0 .02 dm rmoveto(\256)show oce}def (<-){gsave 0 .02 dm rmoveto(\254)show oce}def (==){gsave 0 .05 dm rmoveto(\272)show oce}def end % DIThacks fonts for some special chars 50 dict dup begin /FontType 3 def /FontName /DIThacks def /FontMatrix [.001 0.0 0.0 .001 0.0 0.0] def /FontBBox [-220 -280 900 900] def% a lie but ... /Encoding 256 array def 0 1 255{Encoding exch /.notdef put}for Encoding dup 8#040/space put %space dup 8#110/rc put %right ceil dup 8#111/lt put %left top curl dup 8#112/bv put %bold vert dup 8#113/lk put %left mid curl dup 8#114/lb put %left bot curl dup 8#115/rt put %right top curl dup 8#116/rk put %right mid curl dup 8#117/rb put %right bot curl dup 8#120/rf put %right floor dup 8#121/lf put %left floor dup 8#122/lc put %left ceil dup 8#140/sq put %square dup 8#141/bx put %box dup 8#142/ci put %circle dup 8#143/br put %box rule dup 8#144/rn put %root extender dup 8#145/vr put %vertical rule dup 8#146/ob put %outline bullet dup 8#147/bu put %bullet dup 8#150/ru put %rule dup 8#151/ul put %underline pop /DITfd 100 dict def /BuildChar{0 begin /cc exch def /fd exch def /charname fd /Encoding get cc get def /charwid fd /Metrics get charname get def /charproc fd /CharProcs get charname get def charwid 0 fd /FontBBox get aload pop setcachedevice 40 setlinewidth newpath 0 0 moveto gsave charproc grestore end}def /BuildChar load 0 DITfd put %/UniqueID 5 def /CharProcs 50 dict def CharProcs begin /space{}def /.notdef{}def /ru{500 0 rls}def /rn{0 750 moveto 500 0 rls}def /vr{20 800 moveto 0 -770 rls}def /bv{20 800 moveto 0 -1000 rls}def /br{20 770 moveto 0 -1040 rls}def /ul{0 -250 moveto 500 0 rls}def /ob{200 250 rmoveto currentpoint newpath 200 0 360 arc closepath stroke}def /bu{200 400 rmoveto currentpoint newpath 200 0 360 arc closepath fill}def /sq{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath stroke}def /bx{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath fill}def /ci{355 333 rmoveto currentpoint newpath 333 0 360 arc 50 setlinewidth stroke}def /lt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 add exch s4 a4p stroke}def /lb{20 800 moveto 0 -550 rlineto currx -200 2cx s4 add exch s4 a4p stroke}def /rt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 sub exch s4 a4p stroke}def /rb{20 800 moveto 0 -500 rlineto currx -200 2cx s4 sub exch s4 a4p stroke}def /lk{20 800 moveto 20 300 -280 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /rk{20 800 moveto 20 300 320 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /lf{20 800 moveto 0 -1000 rlineto s4 0 rls}def /rf{20 800 moveto 0 -1000 rlineto s4 neg 0 rls}def /lc{20 -200 moveto 0 1000 rlineto s4 0 rls}def /rc{20 -200 moveto 0 1000 rlineto s4 neg 0 rls}def end /Metrics 50 dict def Metrics begin /.notdef 0 def /space 500 def /ru 500 def /br 0 def /lt 250 def /lb 250 def /rt 250 def /rb 250 def /lk 250 def /rk 250 def /rc 250 def /lc 250 def /rf 250 def /lf 250 def /bv 250 def /ob 350 def /bu 350 def /ci 750 def /bx 750 def /sq 750 def /rn 500 def /ul 500 def /vr 0 def end DITfd begin /s2 500 def /s4 250 def /s3 333 def /a4p{arcto pop pop pop pop}def /2cx{2 copy exch}def /rls{rlineto stroke}def /currx{currentpoint pop}def /dround{transform round exch round exch itransform} def end end /DIThacks exch definefont pop ditstart (psc)xT 576 1 1 xr 1(Times-Roman)xf 1 f 2(Times-Italic)xf 2 f 3(Times-Bold)xf 3 f 4(Times-BoldItalic)xf 4 f 5(Helvetica)xf 5 f 6(Helvetica-Bold)xf 6 f 7(Courier)xf 7 f 8(Courier-Bold)xf 8 f 9(Symbol)xf 9 f 10(DIThacks)xf 10 f 10 s 1 f xi 10 s 0 xH 0 xS 1 f 576 1344 MXY 0 -1152 Dl 1728 0 Dl 0 1152 Dl -1728 0 Dl 455 1525(Fraction)N 742(of)X 829(Tracks)X 1068(Using)X 1279(Pass-Transistor-Switched)X 2118(Wires)X 681 1344 MXY 0 -57 Dl 661 1432(0)N 985 1344 MXY 0 -57 Dl 935 1432(0.2)N 1288 1344 MXY 0 -57 Dl 1238 1432(0.4)N 1591 1344 MXY 0 -57 Dl 1541 1432(0.6)N 1894 1344 MXY 0 -57 Dl 1844 1432(0.8)N 2198 1344 MXY 0 -57 Dl 2178 1432(1)N 576 1273 MXY 57 0 Dl 476 1289(40)N 576 1147 MXY 57 0 Dl 476 1163(50)N 576 1020 MXY 57 0 Dl 476 1036(60)N 576 894 MXY 57 0 Dl 476 910(70)N 576 768 MXY 57 0 Dl 476 784(80)N 576 641 MXY 57 0 Dl 476 657(90)N 576 515 MXY 57 0 Dl 436 531(100)N 576 388 MXY 57 0 Dl 436 404(110)N 576 262 MXY 57 0 Dl 436 278(120)N 827(Length)X 1074(1)X 1134(Pass-Transistor)X 1648(Wires)X 681 262 MXY 28 0 Dl 728 MX 28 0 Dl 774 MX 28 0 Dl 7 s 9 f 725 278(D)N 10 s 1 f 827 379(Length)N 1074(2)X 1134(Pass-Transistor)X 1648(Wires)X 681 363 MXY 121 0 Dl 5 s 10 f 735 379(g)N 10 s 1 f 827 481(Length)N 1074(4)X 1134(Pass-Transistor)X 1648(Wires)X 681 465 MXY 28 0 Dl 728 MX 28 0 Dl 774 MX 28 0 Dl 9 f 722 481(*)N 1 f 827 581(Length)N 1074(8)X 1134(Pass-Transistor)X 1648(Wires)X 681 565 MXY 121 0 Dl 7 s 10 f 732 581(f)N 9 f 664 1218(D)N 10 s 681 1202 MXY 28 -1 Dl 739 1199 MXY 28 -1 Dl 796 1196 MXY 28 -1 Dl 853 1193 MXY 28 -1 Dl 911 1190 MXY 28 -1 Dl 7 s 923 1205(D)N 10 s 940 1189 MXY 28 -2 Dl 993 1183 MXY 28 -2 Dl 1046 1178 MXY 28 -2 Dl 1100 1172 MXY 28 -2 Dl 1153 1166 MXY 28 -2 Dl 7 s 1165 1179(D)N 10 s 1182 1163 MXY 28 -5 Dl 1239 1152 MXY 28 -5 Dl 1297 1141 MXY 28 -5 Dl 1354 1129 MXY 28 -5 Dl 1411 1118 MXY 28 -5 Dl 7 s 1423 1129(D)N 10 s 1440 1113 MXY 26 -10 Dl 1497 1088 MXY 26 -10 Dl 1555 1064 MXY 26 -10 Dl 1613 1040 MXY 26 -10 Dl 1670 1015 MXY 26 -10 Dl 7 s 1680 1020(D)N 10 s 1697 1004 MXY 24 -14 Dl 1752 971 MXY 24 -14 Dl 1806 938 MXY 24 -14 Dl 1861 905 MXY 24 -14 Dl 1915 872 MXY 24 -14 Dl 7 s 1922 873(D)N 10 s 1939 857 MXY 12 -26 Dl 1964 803 MXY 12 -26 Dl 1989 748 MXY 12 -26 Dl 2013 694 MXY 12 -26 Dl 2038 640 MXY 12 -26 Dl 2063 585 MXY 12 -26 Dl 2087 531 MXY 12 -26 Dl 2112 477 MXY 12 -26 Dl 2136 422 MXY 12 -26 Dl 2161 368 MXY 12 -26 Dl 2185 314 MXY 12 -26 Dl 7 s 2181 304(D)N 5 s 10 f 674 1218(g)N 10 s 681 1202 MXY 257 14 Dl 5 s 933 1233(g)N 10 s 940 1217 MXY 242 -5 Dl 5 s 1175 1228(g)N 10 s 1182 1212 MXY 257 -10 Dl 5 s 1433 1217(g)N 10 s 1440 1201 MXY 257 -10 Dl 5 s 1690 1207(g)N 10 s 1697 1191 MXY 242 -40 Dl 5 s 1932 1166(g)N 10 s 1939 1150 MXY 257 -240 Dl 5 s 2191 926(g)N 10 s 9 f 661 1218(*)N 681 1202 MXY 28 3 Dl 739 1209 MXY 28 3 Dl 796 1217 MXY 28 3 Dl 854 1224 MXY 28 3 Dl 911 1232 MXY 28 3 Dl 920 1251(*)N 940 1235 MXY 28 0 Dl 993 MX 28 0 Dl 1046 MX 28 0 Dl 1100 MX 28 0 Dl 1153 1234 MXY 28 0 Dl 1162 1250(*)N 1182 1234 MXY 28 0 Dl 1239 1235 MXY 28 0 Dl 1296 1236 MXY 28 0 Dl 1354 MX 28 0 Dl 1411 1237 MXY 28 0 Dl 1420 1254(*)N 1440 1238 MXY 28 -1 Dl 1497 1235 MXY 28 -1 Dl 1554 1233 MXY 28 -1 Dl 1611 1230 MXY 28 -1 Dl 1668 1228 MXY 28 -1 Dl 1677 1243(*)N 1697 1227 MXY 28 0 Dl 1751 1226 MXY 28 0 Dl 1804 1225 MXY 28 0 Dl 1858 1224 MXY 28 0 Dl 1911 MX 28 0 Dl 1919 1240(*)N 1939 1224 MXY 26 -10 Dl 1998 1199 MXY 26 -10 Dl 2055 1175 MXY 26 -10 Dl 2113 1150 MXY 26 -10 Dl 2171 1126 MXY 26 -10 Dl 2178 1130(*)N 7 s 10 f 671 1218(f)N 10 s 681 1202 MXY 257 39 Dl 7 s 930 1257(f)N 10 s 940 1241 MXY 242 3 Dl 7 s 1172 1260(f)N 10 s 1182 1244 MXY 257 0 Dl 7 s 1430 1260(f)N 10 s 1440 1244 MXY 257 -14 Dl 7 s 1687 1245(f)N 10 s 1697 1229 MXY 242 -1 Dl 7 s 1929 1244(f)N 10 s 1939 1228 MXY 257 -22 Dl 7 s 2188 1221(f)N 1 p xt xs %%Trailer %%EOF %%EndDocument FMENDEPSF 1 9 Q 0 X 0 0 0 1 0 0 0 K (\050a\051 All architectures) 155 555 T (\050b\051 Close-up of architectures with good speed) 113.5 375 T 2 F (Figur) 56.09 359.46 T (e 7:) 77.43 359.46 T 1 F ( Speed of FPGAs with a mix of length 4 b) 91.17 359.46 T (uf) 244.74 359.46 T (fered wires) 252.01 359.46 T 54 503/G1010377 FmPA (and pass-transistor) 111.14 349.46 T (-switched wires.) 178.2 349.46 T (Critical P) 0 -270 61.83 620.67 TF (ath \050ns\051) 0 -270 61.83 654.79 TF (\05020 Circuit Geometric A) 0 -270 74.33 592.83 TF (v) 0 -270 74.33 680.4 TF (erage\051) 0 -270 74.33 684.77 TF (Critical P) 0 -270 62.33 447.33 TF (ath \050ns\051) 0 -270 62.33 481.45 TF (\05020 Circuit Geometric A) 0 -270 73.5 415.5 TF (v) 0 -270 73.5 503.07 TF (erage\051) 0 -270 73.5 507.43 TF 0 56 593 289 768 209.7 157.5 83.15 384.75 FMBEGINEPSF %%BeginDocument: /jayar/d0/vaughn/thesis/place/fpga99/grap/Tcrit_pass_l4buf_closeup.eps %!PS-Adobe-2.0 EPSF-1.2 %%Title: stdin (ditroff) %%Creator: gractus.eecg:vaughn (Vaughn Betz,EECG,LP 392,1653,7662197,G,G ) %%CreationDate: Thu Dec 3 18:02:25 1998 %%For:vaughn vaughn %%Pages: 1 %%DocumentFonts: Times-Italic Times-BoldItalic Helvetica DIThacks Symbol Courier Helvetica-Bold Times-Roman Times-Bold Courier-Bold %%BoundingBox: 56 593 289 768 %%EndProlog %%Page 1 1 %! % Start of psdit.pro -- prolog for ditroff translator % Copyright (c) 1985,1987 Adobe Systems Incorporated. All Rights Reserved. % GOVERNMENT END USERS: See Notice file in TranScript library directory % -- probably /usr/lib/ps/Notice % RCS: $Header: /nfs/relay/cs/src/transcript/lib/RCS/psdit.pro,v 1.1 93/09/07 16:24:02 ken Exp $ /$DITroff 140 dict def $DITroff begin %% Psfig additions /DocumentInitState [ matrix currentmatrix currentlinewidth currentlinecap currentlinejoin currentdash currentgray currentmiterlimit ] cvx def /startFig { /SavedState save def userdict maxlength dict begin currentpoint transform DocumentInitState setmiterlimit setgray setdash setlinejoin setlinecap setlinewidth setmatrix itransform moveto /ury exch def /urx exch def /lly exch def /llx exch def /y exch 72 mul resolution div def /x exch 72 mul resolution div def currentpoint /cy exch def /cx exch def /sx x urx llx sub div def % scaling for x /sy y ury lly sub div def % scaling for y sx sy scale % scale by (sx,sy) cx sx div llx sub cy sy div ury sub translate /DefFigCTM matrix currentmatrix def /initmatrix { DefFigCTM setmatrix } def /defaultmatrix { DefFigCTM exch copy } def /initgraphics { DocumentInitState setmiterlimit setgray setdash setlinejoin setlinecap setlinewidth setmatrix DefFigCTM setmatrix } def /showpage { initgraphics } def } def % Args are llx lly urx ury (in figure coordinates) /clipFig { currentpoint 6 2 roll newpath 4 copy 4 2 roll moveto 6 -1 roll exch lineto exch lineto exch lineto closepath clip newpath moveto } def % doclip, if called, will always be just after a `startfig' /doclip { llx lly urx ury clipFig } def /endFig { end SavedState restore } def /globalstart { % Push details about the enviornment on the stack. fontnum fontsize fontslant fontheight firstpage mh my resolution slotno currentpoint pagesave restore gsave } def /globalend { grestore moveto /slotno exch def /resolution exch def /my exch def /mh exch def /firstpage exch def /fontheight exch def /fontslant exch def /fontsize exch def /fontnum exch def F /pagesave save def } def %% end Psfig additions /fontnum 1 def /fontsize 10 def /fontheight 10 def /fontslant 0 def /xi {0 72 11 mul translate 72 resolution div dup neg scale 0 0 moveto /fontnum 1 def /fontsize 10 def /fontheight 10 def /fontslant 0 def F /pagesave save def}def /PB{save /psv exch def currentpoint translate resolution 72 div dup neg scale 0 0 moveto}def /PE{psv restore}def /m1 matrix def /m2 matrix def /m3 matrix def /oldmat matrix def /tan{dup sin exch cos div}bind def /point{resolution 72 div mul}bind def /dround {transform round exch round exch itransform}bind def /xT{/devname exch def}def /xr{/mh exch def /my exch def /resolution exch def}def /xp{}def /xs{docsave restore end}def /xt{}def /xf{/fontname exch def /slotno exch def fontnames slotno get fontname eq not {fonts slotno fontname findfont put fontnames slotno fontname put}if}def /xH{/fontheight exch def F}bind def /xS{/fontslant exch def F}bind def /s{/fontsize exch def /fontheight fontsize def F}bind def /f{/fontnum exch def F}bind def /F{fontheight 0 le {/fontheight fontsize def}if fonts fontnum get fontsize point 0 0 fontheight point neg 0 0 m1 astore fontslant 0 ne{1 0 fontslant tan 1 0 0 m2 astore m3 concatmatrix}if makefont setfont .04 fontsize point mul 0 dround pop setlinewidth}bind def /X{exch currentpoint exch pop moveto show}bind def /N{3 1 roll moveto show}bind def /Y{exch currentpoint pop exch moveto show}bind def /S /show load def /ditpush{}def/ditpop{}def /AX{3 -1 roll currentpoint exch pop moveto 0 exch ashow}bind def /AN{4 2 roll moveto 0 exch ashow}bind def /AY{3 -1 roll currentpoint pop exch moveto 0 exch ashow}bind def /AS{0 exch ashow}bind def /MX{currentpoint exch pop moveto}bind def /MY{currentpoint pop exch moveto}bind def /MXY /moveto load def /cb{pop}def % action on unknown char -- nothing for now /n{}def/w{}def /p{pop showpage pagesave restore /pagesave save def}def /abspoint{currentpoint exch pop add exch currentpoint pop add exch}def /dstroke{currentpoint stroke moveto}bind def /Dl{2 copy gsave rlineto stroke grestore rmoveto}bind def /arcellipse{oldmat currentmatrix pop currentpoint translate 1 diamv diamh div scale /rad diamh 2 div def rad 0 rad -180 180 arc oldmat setmatrix}def /Dc{gsave dup /diamv exch def /diamh exch def arcellipse dstroke grestore diamh 0 rmoveto}def /De{gsave /diamv exch def /diamh exch def arcellipse dstroke grestore diamh 0 rmoveto}def /Da{currentpoint /by exch def /bx exch def /fy exch def /fx exch def /cy exch def /cx exch def /rad cx cx mul cy cy mul add sqrt def /ang1 cy neg cx neg atan def /ang2 fy fx atan def cx bx add cy by add 2 copy rad ang1 ang2 arcn stroke exch fx add exch fy add moveto}def /Barray 200 array def % 200 values in a wiggle /D~{mark}def /D~~{counttomark Barray exch 0 exch getinterval astore /Bcontrol exch def pop /Blen Bcontrol length def Blen 4 ge Blen 2 mod 0 eq and {Bcontrol 0 get Bcontrol 1 get abspoint /Ycont exch def /Xcont exch def Bcontrol 0 2 copy get 2 mul put Bcontrol 1 2 copy get 2 mul put Bcontrol Blen 2 sub 2 copy get 2 mul put Bcontrol Blen 1 sub 2 copy get 2 mul put /Ybi /Xbi currentpoint 3 1 roll def def 0 2 Blen 4 sub {/i exch def Bcontrol i get 3 div Bcontrol i 1 add get 3 div Bcontrol i get 3 mul Bcontrol i 2 add get add 6 div Bcontrol i 1 add get 3 mul Bcontrol i 3 add get add 6 div /Xbi Xcont Bcontrol i 2 add get 2 div add def /Ybi Ycont Bcontrol i 3 add get 2 div add def /Xcont Xcont Bcontrol i 2 add get add def /Ycont Ycont Bcontrol i 3 add get add def Xbi currentpoint pop sub Ybi currentpoint exch pop sub rcurveto }for dstroke}if}def end /ditstart{$DITroff begin /nfonts 60 def % NFONTS makedev/ditroff dependent! /fonts[nfonts{0}repeat]def /fontnames[nfonts{()}repeat]def /docsave save def }def % character outcalls /oc {/pswid exch def /cc exch def /name exch def /ditwid pswid fontsize mul resolution mul 72000 div def /ditsiz fontsize resolution mul 72 div def ocprocs name known{ocprocs name get exec}{name cb} ifelse}def /fractm [.65 0 0 .6 0 0] def /fraction {/fden exch def /fnum exch def gsave /cf currentfont def cf fractm makefont setfont 0 .3 dm 2 copy neg rmoveto fnum show rmoveto currentfont cf setfont(\244)show setfont fden show grestore ditwid 0 rmoveto} def /oce {grestore ditwid 0 rmoveto}def /dm {ditsiz mul}def /ocprocs 50 dict def ocprocs begin (14){(1)(4)fraction}def (12){(1)(2)fraction}def (34){(3)(4)fraction}def (13){(1)(3)fraction}def (23){(2)(3)fraction}def (18){(1)(8)fraction}def (38){(3)(8)fraction}def (58){(5)(8)fraction}def (78){(7)(8)fraction}def (sr){gsave .05 dm .16 dm rmoveto(\326)show oce}def (is){gsave 0 .15 dm rmoveto(\362)show oce}def (->){gsave 0 .02 dm rmoveto(\256)show oce}def (<-){gsave 0 .02 dm rmoveto(\254)show oce}def (==){gsave 0 .05 dm rmoveto(\272)show oce}def end % DIThacks fonts for some special chars 50 dict dup begin /FontType 3 def /FontName /DIThacks def /FontMatrix [.001 0.0 0.0 .001 0.0 0.0] def /FontBBox [-220 -280 900 900] def% a lie but ... /Encoding 256 array def 0 1 255{Encoding exch /.notdef put}for Encoding dup 8#040/space put %space dup 8#110/rc put %right ceil dup 8#111/lt put %left top curl dup 8#112/bv put %bold vert dup 8#113/lk put %left mid curl dup 8#114/lb put %left bot curl dup 8#115/rt put %right top curl dup 8#116/rk put %right mid curl dup 8#117/rb put %right bot curl dup 8#120/rf put %right floor dup 8#121/lf put %left floor dup 8#122/lc put %left ceil dup 8#140/sq put %square dup 8#141/bx put %box dup 8#142/ci put %circle dup 8#143/br put %box rule dup 8#144/rn put %root extender dup 8#145/vr put %vertical rule dup 8#146/ob put %outline bullet dup 8#147/bu put %bullet dup 8#150/ru put %rule dup 8#151/ul put %underline pop /DITfd 100 dict def /BuildChar{0 begin /cc exch def /fd exch def /charname fd /Encoding get cc get def /charwid fd /Metrics get charname get def /charproc fd /CharProcs get charname get def charwid 0 fd /FontBBox get aload pop setcachedevice 40 setlinewidth newpath 0 0 moveto gsave charproc grestore end}def /BuildChar load 0 DITfd put %/UniqueID 5 def /CharProcs 50 dict def CharProcs begin /space{}def /.notdef{}def /ru{500 0 rls}def /rn{0 750 moveto 500 0 rls}def /vr{20 800 moveto 0 -770 rls}def /bv{20 800 moveto 0 -1000 rls}def /br{20 770 moveto 0 -1040 rls}def /ul{0 -250 moveto 500 0 rls}def /ob{200 250 rmoveto currentpoint newpath 200 0 360 arc closepath stroke}def /bu{200 400 rmoveto currentpoint newpath 200 0 360 arc closepath fill}def /sq{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath stroke}def /bx{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath fill}def /ci{355 333 rmoveto currentpoint newpath 333 0 360 arc 50 setlinewidth stroke}def /lt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 add exch s4 a4p stroke}def /lb{20 800 moveto 0 -550 rlineto currx -200 2cx s4 add exch s4 a4p stroke}def /rt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 sub exch s4 a4p stroke}def /rb{20 800 moveto 0 -500 rlineto currx -200 2cx s4 sub exch s4 a4p stroke}def /lk{20 800 moveto 20 300 -280 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /rk{20 800 moveto 20 300 320 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /lf{20 800 moveto 0 -1000 rlineto s4 0 rls}def /rf{20 800 moveto 0 -1000 rlineto s4 neg 0 rls}def /lc{20 -200 moveto 0 1000 rlineto s4 0 rls}def /rc{20 -200 moveto 0 1000 rlineto s4 neg 0 rls}def end /Metrics 50 dict def Metrics begin /.notdef 0 def /space 500 def /ru 500 def /br 0 def /lt 250 def /lb 250 def /rt 250 def /rb 250 def /lk 250 def /rk 250 def /rc 250 def /lc 250 def /rf 250 def /lf 250 def /bv 250 def /ob 350 def /bu 350 def /ci 750 def /bx 750 def /sq 750 def /rn 500 def /ul 500 def /vr 0 def end DITfd begin /s2 500 def /s4 250 def /s3 333 def /a4p{arcto pop pop pop pop}def /2cx{2 copy exch}def /rls{rlineto stroke}def /currx{currentpoint pop}def /dround{transform round exch round exch itransform} def end end /DIThacks exch definefont pop ditstart (psc)xT 576 1 1 xr 1(Times-Roman)xf 1 f 2(Times-Italic)xf 2 f 3(Times-Bold)xf 3 f 4(Times-BoldItalic)xf 4 f 5(Helvetica)xf 5 f 6(Helvetica-Bold)xf 6 f 7(Courier)xf 7 f 8(Courier-Bold)xf 8 f 9(Symbol)xf 9 f 10(DIThacks)xf 10 f 10 s 1 f xi 10 s 0 xH 0 xS 1 f 576 1391 MXY 0 -1152 Dl 1728 0 Dl 0 1152 Dl -1728 0 Dl 455 1573(Fraction)N 742(of)X 829(Tracks)X 1068(Using)X 1279(Pass-Transistor-Switched)X 2118(Wires)X 576 1391 MXY 57 0 Dl 476 1407(41)N 576 1227 MXY 57 0 Dl 476 1243(43)N 576 1062 MXY 57 0 Dl 476 1078(45)N 576 898 MXY 57 0 Dl 476 914(47)N 576 733 MXY 57 0 Dl 476 749(49)N 576 569 MXY 57 0 Dl 476 585(51)N 576 404 MXY 57 0 Dl 476 420(53)N 576 239 MXY 57 0 Dl 476 255(55)N 681 1391 MXY 0 -57 Dl 661 1479(0)N 985 1391 MXY 0 -57 Dl 935 1479(0.2)N 1288 1391 MXY 0 -57 Dl 1238 1479(0.4)N 1591 1391 MXY 0 -57 Dl 1541 1479(0.6)N 1894 1391 MXY 0 -57 Dl 1844 1479(0.8)N 2198 1391 MXY 0 -57 Dl 2178 1479(1)N 827 338(Length)N 1074(1)X 1134(Pass-Transistor)X 1648(Wires)X 681 322 MXY 28 0 Dl 728 MX 28 0 Dl 774 MX 28 0 Dl 7 s 9 f 725 338(D)N 10 s 1 f 827 432(Length)N 1074(2)X 1134(Pass-Transistor)X 1648(Wires)X 681 416 MXY 121 0 Dl 5 s 10 f 735 432(g)N 10 s 1 f 827 527(Length)N 1074(4)X 1134(Pass-Transistor)X 1648(Wires)X 681 511 MXY 28 0 Dl 728 MX 28 0 Dl 774 MX 28 0 Dl 9 f 722 527(*)N 1 f 827 622(Length)N 1074(8)X 1134(Pass-Transistor)X 1648(Wires)X 681 606 MXY 121 0 Dl 7 s 10 f 732 622(f)N 9 f 664 1027(D)N 10 s 681 1011 MXY 27 -9 Dl 739 992 MXY 27 -9 Dl 797 974 MXY 27 -9 Dl 854 955 MXY 27 -9 Dl 912 936 MXY 27 -9 Dl 7 s 923 942(D)N 10 s 940 926 MXY 23 -16 Dl 983 897 MXY 23 -16 Dl 1027 866 MXY 23 -16 Dl 1071 835 MXY 23 -16 Dl 1115 806 MXY 23 -16 Dl 1158 775 MXY 23 -16 Dl 7 s 1165 775(D)N 10 s 1182 759 MXY 17 -22 Dl 1216 715 MXY 17 -22 Dl 1251 672 MXY 17 -22 Dl 1285 629 MXY 17 -22 Dl 1319 585 MXY 17 -22 Dl 1353 542 MXY 17 -22 Dl 1388 498 MXY 17 -22 Dl 1422 455 MXY 17 -22 Dl 7 s 1423 448(D)N 10 s 1440 432 MXY 9 -27 Dl 1460 377 MXY 9 -27 Dl 1480 322 MXY 9 -27 Dl 1500 266 MXY 9 -27 Dl 5 s 10 f 674 1027(g)N 10 s 681 1011 MXY 257 98 Dl 5 s 933 1126(g)N 10 s 940 1110 MXY 242 -33 Dl 5 s 1175 1092(g)N 10 s 1182 1076 MXY 257 -69 Dl 5 s 1433 1023(g)N 10 s 1440 1007 MXY 257 -67 Dl 5 s 1690 955(g)N 10 s 1697 939 MXY 242 -263 Dl 5 s 1932 691(g)N 10 s 1939 675 MXY 71 -436 Dl 9 f 661 1027(*)N 681 1011 MXY 21 18 Dl 729 1051 MXY 21 18 Dl 776 1091 MXY 21 18 Dl 823 1132 MXY 21 18 Dl 870 1171 MXY 21 18 Dl 917 1212 MXY 21 18 Dl 920 1246(*)N 940 1230 MXY 28 -1 Dl 993 1228 MXY 28 -1 Dl 1046 1226 MXY 28 -1 Dl 1100 1224 MXY 28 -1 Dl 1153 1221 MXY 28 -1 Dl 1162 1236(*)N 1182 1220 MXY 28 2 Dl 1239 1226 MXY 28 2 Dl 1296 1231 MXY 28 2 Dl 1354 1237 MXY 28 2 Dl 1411 1242 MXY 28 2 Dl 1420 1261(*)N 1440 1245 MXY 27 -8 Dl 1497 1229 MXY 27 -8 Dl 1555 1213 MXY 27 -8 Dl 1612 1197 MXY 27 -8 Dl 1669 1180 MXY 27 -8 Dl 1677 1188(*)N 1697 1172 MXY 28 -2 Dl 1751 1168 MXY 28 -2 Dl 1804 1164 MXY 28 -2 Dl 1858 1160 MXY 28 -2 Dl 1911 1155 MXY 28 -2 Dl 1919 1169(*)N 1939 1153 MXY 9 -27 Dl 1959 1100 MXY 9 -27 Dl 1978 1048 MXY 9 -27 Dl 1997 995 MXY 9 -27 Dl 2016 943 MXY 9 -27 Dl 2035 890 MXY 9 -27 Dl 2054 838 MXY 9 -27 Dl 2073 785 MXY 9 -27 Dl 2092 732 MXY 9 -27 Dl 2111 680 MXY 9 -27 Dl 2130 628 MXY 9 -27 Dl 2150 575 MXY 9 -27 Dl 2169 522 MXY 9 -27 Dl 2188 470 MXY 9 -27 Dl 2178 459(*)N 7 s 10 f 671 1027(f)N 10 s 681 1011 MXY 257 255 Dl 7 s 930 1283(f)N 10 s 940 1267 MXY 242 21 Dl 7 s 1172 1305(f)N 10 s 1182 1289 MXY 257 0 Dl 7 s 1430 1305(f)N 10 s 1440 1289 MXY 257 -97 Dl 7 s 1687 1207(f)N 10 s 1697 1191 MXY 242 -8 Dl 7 s 1929 1198(f)N 10 s 1939 1182 MXY 257 -147 Dl 7 s 2188 1051(f)N 1 p xt xs %%Trailer %%EOF %%EndDocument FMENDEPSF 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 54 72 294.12 720 C 0 0 612 792 C 54 72 294.12 720 C 54 72 293.76 263.65 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 49 599 289 769 216 153 77.35 102.39 FMBEGINEPSF %%BeginDocument: /jayar/d0/vaughn/thesis/place/fpga99/grap/area_pass_l4buf.eps %!PS-Adobe-2.0 EPSF-1.2 %%Title: stdin (ditroff) %%Creator: gractus.eecg:vaughn (Vaughn Betz,EECG,LP 392,1653,7662197,G,G ) %%CreationDate: Fri Dec 4 12:12:59 1998 %%For:vaughn vaughn %%Pages: 1 %%DocumentFonts: Times-Italic Times-BoldItalic Helvetica DIThacks Symbol Courier Helvetica-Bold Times-Roman Times-Bold Courier-Bold %%BoundingBox: 49 599 289 769 %%EndProlog %%Page 1 1 %! % Start of psdit.pro -- prolog for ditroff translator % Copyright (c) 1985,1987 Adobe Systems Incorporated. All Rights Reserved. % GOVERNMENT END USERS: See Notice file in TranScript library directory % -- probably /usr/lib/ps/Notice % RCS: $Header: /nfs/relay/cs/src/transcript/lib/RCS/psdit.pro,v 1.1 93/09/07 16:24:02 ken Exp $ /$DITroff 140 dict def $DITroff begin %% Psfig additions /DocumentInitState [ matrix currentmatrix currentlinewidth currentlinecap currentlinejoin currentdash currentgray currentmiterlimit ] cvx def /startFig { /SavedState save def userdict maxlength dict begin currentpoint transform DocumentInitState setmiterlimit setgray setdash setlinejoin setlinecap setlinewidth setmatrix itransform moveto /ury exch def /urx exch def /lly exch def /llx exch def /y exch 72 mul resolution div def /x exch 72 mul resolution div def currentpoint /cy exch def /cx exch def /sx x urx llx sub div def % scaling for x /sy y ury lly sub div def % scaling for y sx sy scale % scale by (sx,sy) cx sx div llx sub cy sy div ury sub translate /DefFigCTM matrix currentmatrix def /initmatrix { DefFigCTM setmatrix } def /defaultmatrix { DefFigCTM exch copy } def /initgraphics { DocumentInitState setmiterlimit setgray setdash setlinejoin setlinecap setlinewidth setmatrix DefFigCTM setmatrix } def /showpage { initgraphics } def } def % Args are llx lly urx ury (in figure coordinates) /clipFig { currentpoint 6 2 roll newpath 4 copy 4 2 roll moveto 6 -1 roll exch lineto exch lineto exch lineto closepath clip newpath moveto } def % doclip, if called, will always be just after a `startfig' /doclip { llx lly urx ury clipFig } def /endFig { end SavedState restore } def /globalstart { % Push details about the enviornment on the stack. fontnum fontsize fontslant fontheight firstpage mh my resolution slotno currentpoint pagesave restore gsave } def /globalend { grestore moveto /slotno exch def /resolution exch def /my exch def /mh exch def /firstpage exch def /fontheight exch def /fontslant exch def /fontsize exch def /fontnum exch def F /pagesave save def } def %% end Psfig additions /fontnum 1 def /fontsize 10 def /fontheight 10 def /fontslant 0 def /xi {0 72 11 mul translate 72 resolution div dup neg scale 0 0 moveto /fontnum 1 def /fontsize 10 def /fontheight 10 def /fontslant 0 def F /pagesave save def}def /PB{save /psv exch def currentpoint translate resolution 72 div dup neg scale 0 0 moveto}def /PE{psv restore}def /m1 matrix def /m2 matrix def /m3 matrix def /oldmat matrix def /tan{dup sin exch cos div}bind def /point{resolution 72 div mul}bind def /dround {transform round exch round exch itransform}bind def /xT{/devname exch def}def /xr{/mh exch def /my exch def /resolution exch def}def /xp{}def /xs{docsave restore end}def /xt{}def /xf{/fontname exch def /slotno exch def fontnames slotno get fontname eq not {fonts slotno fontname findfont put fontnames slotno fontname put}if}def /xH{/fontheight exch def F}bind def /xS{/fontslant exch def F}bind def /s{/fontsize exch def /fontheight fontsize def F}bind def /f{/fontnum exch def F}bind def /F{fontheight 0 le {/fontheight fontsize def}if fonts fontnum get fontsize point 0 0 fontheight point neg 0 0 m1 astore fontslant 0 ne{1 0 fontslant tan 1 0 0 m2 astore m3 concatmatrix}if makefont setfont .04 fontsize point mul 0 dround pop setlinewidth}bind def /X{exch currentpoint exch pop moveto show}bind def /N{3 1 roll moveto show}bind def /Y{exch currentpoint pop exch moveto show}bind def /S /show load def /ditpush{}def/ditpop{}def /AX{3 -1 roll currentpoint exch pop moveto 0 exch ashow}bind def /AN{4 2 roll moveto 0 exch ashow}bind def /AY{3 -1 roll currentpoint pop exch moveto 0 exch ashow}bind def /AS{0 exch ashow}bind def /MX{currentpoint exch pop moveto}bind def /MY{currentpoint pop exch moveto}bind def /MXY /moveto load def /cb{pop}def % action on unknown char -- nothing for now /n{}def/w{}def /p{pop showpage pagesave restore /pagesave save def}def /abspoint{currentpoint exch pop add exch currentpoint pop add exch}def /dstroke{currentpoint stroke moveto}bind def /Dl{2 copy gsave rlineto stroke grestore rmoveto}bind def /arcellipse{oldmat currentmatrix pop currentpoint translate 1 diamv diamh div scale /rad diamh 2 div def rad 0 rad -180 180 arc oldmat setmatrix}def /Dc{gsave dup /diamv exch def /diamh exch def arcellipse dstroke grestore diamh 0 rmoveto}def /De{gsave /diamv exch def /diamh exch def arcellipse dstroke grestore diamh 0 rmoveto}def /Da{currentpoint /by exch def /bx exch def /fy exch def /fx exch def /cy exch def /cx exch def /rad cx cx mul cy cy mul add sqrt def /ang1 cy neg cx neg atan def /ang2 fy fx atan def cx bx add cy by add 2 copy rad ang1 ang2 arcn stroke exch fx add exch fy add moveto}def /Barray 200 array def % 200 values in a wiggle /D~{mark}def /D~~{counttomark Barray exch 0 exch getinterval astore /Bcontrol exch def pop /Blen Bcontrol length def Blen 4 ge Blen 2 mod 0 eq and {Bcontrol 0 get Bcontrol 1 get abspoint /Ycont exch def /Xcont exch def Bcontrol 0 2 copy get 2 mul put Bcontrol 1 2 copy get 2 mul put Bcontrol Blen 2 sub 2 copy get 2 mul put Bcontrol Blen 1 sub 2 copy get 2 mul put /Ybi /Xbi currentpoint 3 1 roll def def 0 2 Blen 4 sub {/i exch def Bcontrol i get 3 div Bcontrol i 1 add get 3 div Bcontrol i get 3 mul Bcontrol i 2 add get add 6 div Bcontrol i 1 add get 3 mul Bcontrol i 3 add get add 6 div /Xbi Xcont Bcontrol i 2 add get 2 div add def /Ybi Ycont Bcontrol i 3 add get 2 div add def /Xcont Xcont Bcontrol i 2 add get add def /Ycont Ycont Bcontrol i 3 add get add def Xbi currentpoint pop sub Ybi currentpoint exch pop sub rcurveto }for dstroke}if}def end /ditstart{$DITroff begin /nfonts 60 def % NFONTS makedev/ditroff dependent! /fonts[nfonts{0}repeat]def /fontnames[nfonts{()}repeat]def /docsave save def }def % character outcalls /oc {/pswid exch def /cc exch def /name exch def /ditwid pswid fontsize mul resolution mul 72000 div def /ditsiz fontsize resolution mul 72 div def ocprocs name known{ocprocs name get exec}{name cb} ifelse}def /fractm [.65 0 0 .6 0 0] def /fraction {/fden exch def /fnum exch def gsave /cf currentfont def cf fractm makefont setfont 0 .3 dm 2 copy neg rmoveto fnum show rmoveto currentfont cf setfont(\244)show setfont fden show grestore ditwid 0 rmoveto} def /oce {grestore ditwid 0 rmoveto}def /dm {ditsiz mul}def /ocprocs 50 dict def ocprocs begin (14){(1)(4)fraction}def (12){(1)(2)fraction}def (34){(3)(4)fraction}def (13){(1)(3)fraction}def (23){(2)(3)fraction}def (18){(1)(8)fraction}def (38){(3)(8)fraction}def (58){(5)(8)fraction}def (78){(7)(8)fraction}def (sr){gsave .05 dm .16 dm rmoveto(\326)show oce}def (is){gsave 0 .15 dm rmoveto(\362)show oce}def (->){gsave 0 .02 dm rmoveto(\256)show oce}def (<-){gsave 0 .02 dm rmoveto(\254)show oce}def (==){gsave 0 .05 dm rmoveto(\272)show oce}def end % DIThacks fonts for some special chars 50 dict dup begin /FontType 3 def /FontName /DIThacks def /FontMatrix [.001 0.0 0.0 .001 0.0 0.0] def /FontBBox [-220 -280 900 900] def% a lie but ... /Encoding 256 array def 0 1 255{Encoding exch /.notdef put}for Encoding dup 8#040/space put %space dup 8#110/rc put %right ceil dup 8#111/lt put %left top curl dup 8#112/bv put %bold vert dup 8#113/lk put %left mid curl dup 8#114/lb put %left bot curl dup 8#115/rt put %right top curl dup 8#116/rk put %right mid curl dup 8#117/rb put %right bot curl dup 8#120/rf put %right floor dup 8#121/lf put %left floor dup 8#122/lc put %left ceil dup 8#140/sq put %square dup 8#141/bx put %box dup 8#142/ci put %circle dup 8#143/br put %box rule dup 8#144/rn put %root extender dup 8#145/vr put %vertical rule dup 8#146/ob put %outline bullet dup 8#147/bu put %bullet dup 8#150/ru put %rule dup 8#151/ul put %underline pop /DITfd 100 dict def /BuildChar{0 begin /cc exch def /fd exch def /charname fd /Encoding get cc get def /charwid fd /Metrics get charname get def /charproc fd /CharProcs get charname get def charwid 0 fd /FontBBox get aload pop setcachedevice 40 setlinewidth newpath 0 0 moveto gsave charproc grestore end}def /BuildChar load 0 DITfd put %/UniqueID 5 def /CharProcs 50 dict def CharProcs begin /space{}def /.notdef{}def /ru{500 0 rls}def /rn{0 750 moveto 500 0 rls}def /vr{20 800 moveto 0 -770 rls}def /bv{20 800 moveto 0 -1000 rls}def /br{20 770 moveto 0 -1040 rls}def /ul{0 -250 moveto 500 0 rls}def /ob{200 250 rmoveto currentpoint newpath 200 0 360 arc closepath stroke}def /bu{200 400 rmoveto currentpoint newpath 200 0 360 arc closepath fill}def /sq{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath stroke}def /bx{80 0 rmoveto currentpoint dround newpath moveto 640 0 rlineto 0 640 rlineto -640 0 rlineto closepath fill}def /ci{355 333 rmoveto currentpoint newpath 333 0 360 arc 50 setlinewidth stroke}def /lt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 add exch s4 a4p stroke}def /lb{20 800 moveto 0 -550 rlineto currx -200 2cx s4 add exch s4 a4p stroke}def /rt{20 -200 moveto 0 550 rlineto currx 800 2cx s4 sub exch s4 a4p stroke}def /rb{20 800 moveto 0 -500 rlineto currx -200 2cx s4 sub exch s4 a4p stroke}def /lk{20 800 moveto 20 300 -280 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /rk{20 800 moveto 20 300 320 300 s4 arcto pop pop 1000 sub currentpoint stroke moveto 20 300 4 2 roll s4 a4p 20 -200 lineto stroke}def /lf{20 800 moveto 0 -1000 rlineto s4 0 rls}def /rf{20 800 moveto 0 -1000 rlineto s4 neg 0 rls}def /lc{20 -200 moveto 0 1000 rlineto s4 0 rls}def /rc{20 -200 moveto 0 1000 rlineto s4 neg 0 rls}def end /Metrics 50 dict def Metrics begin /.notdef 0 def /space 500 def /ru 500 def /br 0 def /lt 250 def /lb 250 def /rt 250 def /rb 250 def /lk 250 def /rk 250 def /rc 250 def /lc 250 def /rf 250 def /lf 250 def /bv 250 def /ob 350 def /bu 350 def /ci 750 def /bx 750 def /sq 750 def /rn 500 def /ul 500 def /vr 0 def end DITfd begin /s2 500 def /s4 250 def /s3 333 def /a4p{arcto pop pop pop pop}def /2cx{2 copy exch}def /rls{rlineto stroke}def /currx{currentpoint pop}def /dround{transform round exch round exch itransform} def end end /DIThacks exch definefont pop ditstart (psc)xT 576 1 1 xr 1(Times-Roman)xf 1 f 2(Times-Italic)xf 2 f 3(Times-Bold)xf 3 f 4(Times-BoldItalic)xf 4 f 5(Helvetica)xf 5 f 6(Helvetica-Bold)xf 6 f 7(Courier)xf 7 f 8(Courier-Bold)xf 8 f 9(Symbol)xf 9 f 10(DIThacks)xf 10 f 10 s 1 f xi 10 s 0 xH 0 xS 1 f 576 1344 MXY 0 -1152 Dl 1728 0 Dl 0 1152 Dl -1728 0 Dl 443 1525(Fraction)N 730(of)X 817(Tracks)X 1056(Using)X 1267(Pass-Transistor-Switched)X 2106(Wires)X 681 1344 MXY 0 -57 Dl 661 1432(0)N 985 1344 MXY 0 -57 Dl 935 1432(0.2)N 1288 1344 MXY 0 -57 Dl 1238 1432(0.4)N 1591 1344 MXY 0 -57 Dl 1541 1432(0.6)N 1894 1344 MXY 0 -57 Dl 1844 1432(0.8)N 2198 1344 MXY 0 -57 Dl 2178 1432(1)N 576 1273 MXY 57 0 Dl 396 1289(4800)N 576 1108 MXY 57 0 Dl 396 1124(5000)N 576 944 MXY 57 0 Dl 396 960(5200)N 576 780 MXY 57 0 Dl 396 796(5400)N 576 615 MXY 57 0 Dl 396 631(5600)N 576 451 MXY 57 0 Dl 396 467(5800)N 576 287 MXY 57 0 Dl 396 303(6000)N 1142 278(Length)N 1389(1)X 1449(Pass-Transistor)X 1963(Wires)X 1015 262 MXY 28 0 Dl 1092 MX 28 0 Dl 7 s 9 f 1051 278(D)N 10 s 1 f 1142 356(Length)N 1389(2)X 1449(Pass-Transistor)X 1963(Wires)X 1015 340 MXY 105 0 Dl 5 s 10 f 1061 356(g)N 10 s 1 f 1142 434(Length)N 1389(4)X 1449(Pass-Transistor)X 1963(Wires)X 1015 418 MXY 28 0 Dl 1092 MX 28 0 Dl 9 f 1048 434(*)N 1 f 1142 512(Length)N 1389(8)X 1449(Pass-Transistor)X 1963(Wires)X 1015 496 MXY 105 0 Dl 7 s 10 f 1058 512(f)N 9 f 664 384(D)N 10 s 681 368 MXY 18 22 Dl 716 410 MXY 18 22 Dl 750 451 MXY 18 22 Dl 784 493 MXY 18 22 Dl 819 534 MXY 18 22 Dl 853 575 MXY 18 22 Dl 887 617 MXY 18 22 Dl 921 658 MXY 18 22 Dl 7 s 923 697(D)N 10 s 940 681 MXY 28 6 Dl 993 693 MXY 28 6 Dl 1047 705 MXY 28 6 Dl 1100 717 MXY 28 6 Dl 1154 729 MXY 28 6 Dl 7 s 1165 751(D)N 10 s 1182 735 MXY 28 -2 Dl 1239 729 MXY 28 -2 Dl 1296 724 MXY 28 -2 Dl 1354 718 MXY 28 -2 Dl 1411 712 MXY 28 -2 Dl 7 s 1423 725(D)N 10 s 1440 709 MXY 28 -1 Dl 1497 707 MXY 28 -1 Dl 1554 705 MXY 28 -1 Dl 1611 702 MXY 28 -1 Dl 1668 MX 28 -1 Dl 7 s 1680 716(D)N 10 s 1697 700 MXY 24 -14 Dl 1752 667 MXY 24 -14 Dl 1806 635 MXY 24 -14 Dl 1861 603 MXY 24 -14 Dl 1915 571 MXY 24 -14 Dl 7 s 1922 572(D)N 10 s 1939 556 MXY 23 -17 Dl 1987 522 MXY 23 -17 Dl 2033 488 MXY 23 -17 Dl 2081 453 MXY 23 -17 Dl 2127 419 MXY 23 -17 Dl 2174 384 MXY 23 -17 Dl 7 s 2181 383(D)N 5 s 10 f 674 384(g)N 10 s 681 368 MXY 257 246 Dl 5 s 933 631(g)N 10 s 940 615 MXY 242 215 Dl 5 s 1175 846(g)N 10 s 1182 830 MXY 257 173 Dl 5 s 1433 1020(g)N 10 s 1440 1004 MXY 257 92 Dl 5 s 1690 1112(g)N 10 s 1697 1096 MXY 242 63 Dl 5 s 1932 1175(g)N 10 s 1939 1159 MXY 257 -19 Dl 5 s 2191 1157(g)N 10 s 9 f 661 384(*)N 681 368 MXY 25 13 Dl 728 394 MXY 25 13 Dl 775 420 MXY 25 13 Dl 821 445 MXY 25 13 Dl 868 471 MXY 25 13 Dl 914 496 MXY 25 13 Dl 920 527(*)N 940 511 MXY 20 19 Dl 984 552 MXY 20 19 Dl 1028 594 MXY 20 19 Dl 1072 636 MXY 20 19 Dl 1116 678 MXY 20 19 Dl 1161 720 MXY 20 19 Dl 1162 756(*)N 1182 740 MXY 23 16 Dl 1229 773 MXY 23 16 Dl 1275 807 MXY 23 16 Dl 1323 841 MXY 23 16 Dl 1369 875 MXY 23 16 Dl 1416 909 MXY 23 16 Dl 1420 941(*)N 1440 925 MXY 24 16 Dl 1486 956 MXY 24 16 Dl 1533 988 MXY 24 16 Dl 1579 1019 MXY 24 16 Dl 1627 1050 MXY 24 16 Dl 1673 1082 MXY 24 16 Dl 1677 1114(*)N 1697 1098 MXY 24 14 Dl 1752 1129 MXY 24 14 Dl 1806 1160 MXY 24 14 Dl 1861 1192 MXY 24 14 Dl 1915 1223 MXY 24 14 Dl 1919 1254(*)N 1939 1238 MXY 28 3 Dl 1997 1244 MXY 28 3 Dl 2054 1252 MXY 28 3 Dl 2112 1259 MXY 28 3 Dl 2169 1266 MXY 28 3 Dl 2178 1285(*)N 7 s 10 f 671 384(f)N 10 s 681 368 MXY 257 101 Dl 7 s 930 486(f)N 10 s 940 470 MXY 242 211 Dl 7 s 1172 698(f)N 10 s 1182 682 MXY 257 78 Dl 7 s 1430 776(f)N 10 s 1440 760 MXY 257 115 Dl 7 s 1687 892(f)N 10 s 1697 876 MXY 242 -1 Dl 7 s 1929 890(f)N 10 s 1939 874 MXY 257 -86 Dl 7 s 2188 804(f)N 1 p xt xs %%Trailer %%EOF %%EndDocument FMENDEPSF 2 9 Q 0 X 0 0 0 1 0 0 0 K (Figur) 59.18 86.98 T (e 8:) 80.52 86.98 T 1 F ( Area of FPGAs with a mix of length 4 b) 94.26 86.98 T (uf) 243.32 86.98 T (fered wires) 250.59 86.98 T 56 231/G1010389 FmPA (and pass-transistor) 111.98 76.98 T (-switched wires.) 179.04 76.98 T (Routing area \050Min.-W) 0 -270 60.67 111.3 TF (idth T) 0 -270 60.67 191.18 TF (rans. Areas\051) 0 -270 60.67 212.62 TF (\05020 Circuit Geometric A) 0 -270 71.33 121.3 TF (v) 0 -270 71.33 208.87 TF (erage\051) 0 -270 71.33 213.24 TF 54 72 294.12 720 C 0 0 612 792 C 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.7/DEST FmPD2 0 791.99 0.01 792 C 0 0 612 792 C 91 509/M9.35310.Figure.Figure.79.Speed.of.FPGAs.with.a.mix.of.length.4.buffered.wires.and.passtransistor.wi FmPA 0 791.99 0.01 792 C 0 0 612 792 C 91 509/I1.1010376 FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C 94 237/M9.26892.Figure.Figure.710.Area.of.FPGAs.with.a.mix.of.length.4.buffered.wires.and.passtransistor.wi FmPA 0 791.99 0.01 791.99 C 0 0 612 792 C 94 237/I1.1010388 FmPA 339 475/M9.18737.Heading3.743.Length.8.Buffered.Wires.Plus.PassTransistor.Switched.Wires FmPA 339 475/I1.1001540 FmPA 336 283/M9.27896.Heading2.77.Overall.Architecture.Comparison FmPA 336 283/I1.1004389 FmPA 0 791.99 0.01 792 C 0 0 612 792 C [/Rect[156 310 188 320]/Border[0 0 0]/Page 7/View[/XYZ null 91 509 FmDC exch pop null]/LNK FmPD 0 791.99 0.01 791.99 C 0 0 612 792 C [/Rect[336 587 367 597]/Border[0 0 0]/Page 7/View[/XYZ null 94 237 FmDC exch pop null]/LNK FmPD [/Rect[528 343 537 353]/Border[0 0 0]/Page 10/View[/XYZ null 338 373 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 63 567 729]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "7" 7 %%Page: "8" 8 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 1 9 Q 0 X 0 0 0 1 0 0 0 K 0.18 (and ag) 54 714 P 0.18 (ainst a routing architecture that is similar to that of the pop-) 77.88 714 P 0.61 (ular Xilinx XC4000X series FPGAs [33, 35]. This \3224000X-lik) 54 704 P 0.61 (e\323) 286.13 704 P 1.13 (architecture contains 25% length 1 wires, 12.5% length 2 wires,) 54 694 P 0.19 (37.5% length 4 wires, and 25% \322one-quarter longs\323, whose length) 54 684 P 1.05 (is one-fourth of the chip. The length 1 and 2 wires connect via) 54 674 P 0.84 (pass transistors, while the longer wires connect via tri-state b) 54 664 P 0.84 (uf) 280.85 664 P 0.84 (f-) 288.13 664 P 0.07 (ers. As well, pass transistor switches also allo) 54 654 P 0.07 (w the length 4 wires) 220.84 654 P -0.03 (to connect to the length 1 and 2 wires, and the one-quarter longs to) 54 644 P 0.57 (connect to length 1 wires. While this routing architecture is v) 54 634 P 0.57 (ery) 282.63 634 P 0.31 (similar to that of the Xilinx XC4000X, it simpli\336es a fe) 54 624 P 0.31 (w features) 256.58 624 P ([35].) 54 614 T 0.79 (T) 72 600 P 0.79 (able 3 compares the speed and density of some of the best) 76.78 600 P 54 744/G1004654 FmPA 1.07 (architectures found in each of the preceding sections to those of) 54 590 P 0.5 (this 4000X-lik) 54 580 P 0.5 (e architecture. W) 106.66 580 P 0.5 (e also include the performance of) 171.41 580 P 0.72 (an FPGA composed entirely of length 1 wires connected by pass) 54 570 P 1.35 (transistors, since most prior FPGA research has focused on this) 54 560 P (architecture.) 54 550 T 0.71 (All the architectures in T) 72 536 P 0.71 (able 3 allo) 164.1 536 P 0.71 (w each logic block input) 202.79 536 P 54 680/G1010662 FmPA 1.11 (pin to connect to 0.5) 54 526 P 4 F 1.11 (\327) 132.18 526 P 1 F 1.11 (W routing tracks \050i.e. F) 134.43 526 P 1 7.2 Q 0.89 (c,input) 222.85 523.75 P 1 9 Q 1.11 ( = 0.5) 242.65 526 P 4 F 1.11 (\327) 265.7 526 P 1 F 1.11 (W\051 b) 267.95 526 P 1.11 (ut) 287.12 526 P 0.08 (each logic block output pin can connect to only 0.25) 54 514.35 P 4 F 0.08 (\327) 243.22 514.35 P 1 F 0.08 (W tracks \050i.e.) 245.47 514.35 P 2.1 (F) 54 504.35 P 1 7.2 Q 1.68 (c,output) 59 502.1 P 1 9 Q 2.1 ( = 0.25) 82.4 504.35 P 4 F 2.1 (\327) 111.93 504.35 P 1 F 2.1 (W\051. Setting F) 114.18 504.35 P 1 7.2 Q 1.68 (c,output) 171.48 502.1 P 1 9 Q 2.1 ( to 0.25) 194.88 504.35 P 4 F 2.1 (\327) 226.33 504.35 P 1 F 2.1 (W instead of the) 228.58 504.35 P 0.34 (0.5) 54 492.7 P 4 F 0.34 (\327) 65.25 492.7 P 1 F 0.34 (W we used in the pre) 67.5 492.7 P 0.34 (vious sections reduces the FPGA routing) 145.19 492.7 P -0.14 (area by 2% to 5%, depending on the e) 54 482.7 P -0.14 (xact architecture. Recall that) 189.46 482.7 P 0.37 (the connection block between the routing tracks and a logic block) 54 472.7 P 0.77 (input pin consists of an F) 54 462.7 P 1 7.2 Q 0.62 (c,input) 148.62 460.45 P 1 9 Q 0.77 ( multiple) 168.42 462.7 P 0.77 (x) 201.32 462.7 P 0.77 (er) 205.68 462.7 P 0.77 (, while the connection) 212.31 462.7 P -0.2 (block from a logic block output pin to the routing tracks consists of) 54 451.05 P -0.13 (F) 54 441.05 P 1 7.2 Q -0.11 (c,output) 59 438.8 P 1 9 Q -0.13 ( pass transistors controlled by F) 82.4 441.05 P 1 7.2 Q -0.11 (c,output) 195.99 438.8 P 1 9 Q -0.13 ( SRAM bits. Conse-) 219.39 441.05 P 0.69 (quently) 54 429.4 P 0.69 (, connections to logic block output pins require more area) 80.42 429.4 P 0.23 (than connections to input pins \050see T) 54 419.4 P 0.23 (able 1\051, and it is best to mak) 187.13 419.4 P 0.23 (e) 290.12 419.4 P (F) 54 409.4 T 1 7.2 Q (c,output) 59 407.15 T 1 9 Q ( smaller than F) 82.4 409.4 T 1 7.2 Q (c,input) 136.15 407.15 T 1 9 Q (.) 155.95 409.4 T -0.14 (The architectures are listed \050after the 4000X-lik) 72 393.75 P -0.14 (e architecture\051) 242.54 393.75 P 54 538/G1010448 FmPA 0.33 (in order of increasing comple) 54 383.75 P 0.33 (xity) 161.15 383.75 P 0.33 (. Notice the e) 174.57 383.75 P 0.33 (xtremely poor per-) 225.98 383.75 P 1.52 (formance of an FPGA using only length 1 wires connected via) 54 373.75 P 0.29 (pass transistors \321 150% slo) 54 363.75 P 0.29 (wer \050-60% speedup\051 and 33% percent) 156.95 363.75 P 0.61 (lar) 54 353.75 P 0.61 (ger than the 4000X-lik) 63.33 353.75 P 0.61 (e architecture. The best architecture we) 146.8 353.75 P 2.01 (found using only pass transistors and one length of wire used) 54 343.75 P 1.79 (length 8 wires. This architecture performs much better than a) 317.88 714 P 0.76 (length 1 architecture; it is 5.6% f) 317.88 704 P 0.76 (aster than the 4000X-lik) 440.58 704 P 0.76 (e archi-) 530.01 704 P 1.1 (tecture, at a cost of 16% lar) 317.88 694 P 1.1 (ger area than that of the 4000X-lik) 423.03 694 P 1.1 (e) 554 694 P 0.06 (architecture. Although the speed and area-ef) 317.88 684 P 0.06 (\336cienc) 479.71 684 P 0.06 (y of this length) 503.57 684 P 0.04 (8, all pass-transistor FPGA are reasonably competiti) 317.88 674 P 0.04 (v) 506.14 674 P 0.04 (e on a) 510.5 674 P 0.04 (v) 531.9 674 P 0.04 (erage,) 536.27 674 P -0.15 (we consider FPGA architectures that contain no b) 317.88 664 P -0.15 (uf) 495.89 664 P -0.15 (fers dangerous.) 503.17 664 P -0.14 (As circuit size increases, the longest connections in an FPGA gro) 317.88 654 P -0.14 (w) 551.5 654 P 0.34 (longer) 317.88 644 P 0.34 (, and pass through more series switches. Since the delay of) 340.52 644 P 1.52 (pass-transistor switches gro) 317.88 634 P 1.52 (ws quadratically with the number of) 420.18 634 P 1.26 (switches in series, it is dif) 317.88 624 P 1.26 (\336cult for an architecture that contains) 416.96 624 P -0.11 (only pass transistors to maintain good speed as the size of the logic) 317.88 614 P 0.17 (block array gro) 317.88 604 P 0.17 (ws. As well, lar) 372.98 604 P 0.17 (ger circuits can contain nets with a) 431.99 604 P 0.75 (higher maximum f) 317.88 594 P 0.75 (anout, and purely pass-transistor based routing) 386.28 594 P 0.41 (is inef) 317.88 584 P 0.41 (\336cient for routing high-f) 340.31 584 P 0.41 (anout nets. F) 429.19 584 P 0.41 (or both these reasons,) 478.79 584 P 0.17 (architectures that contain only pass transistors do not scale as well) 317.88 574 P -0.02 (with increasing circuit size as architectures that contain some b) 317.88 564 P -0.02 (uf) 544.73 564 P -0.02 (f-) 552.01 564 P (ers.) 317.88 554 T 0.3 (The best single-wire-type architecture we found, in which all) 335.88 540 P 318 684/G1010572 FmPA 0.3 (wires are length 4 and all switches are b) 317.88 530 P 0.3 (uf) 464.05 530 P 0.3 (fers, is 7.2%) 471.32 530 P 3 F 0.3 (faster) 519.45 530 P 1 F 0.3 ( than) 539.95 530 P -0.05 (the Xilinx 4000X-lik) 317.88 520 P -0.05 (e FPGA. Its area is 30.9% lar) 393.18 520 P -0.05 (ger) 500.37 520 P -0.05 (, ho) 511.51 520 P -0.05 (we) 524.73 520 P -0.05 (v) 535 520 P -0.05 (er) 539.36 520 P -0.05 (. It) 545.86 520 P 0.82 (is interesting that such a simple FPGA architecture is reasonably) 317.88 510 P 0.96 (competiti) 317.88 500 P 0.96 (v) 351.66 500 P 0.96 (e with the comple) 356.02 500 P 0.96 (x routing architecture of the 4000X-) 423 500 P -0.21 (lik) 317.88 490 P -0.21 (e FPGA. Simpler routing architectures mak) 327.29 490 P -0.21 (e it easier to de) 484.7 490 P -0.21 (v) 538.14 490 P -0.21 (elop) 542.5 490 P 0.08 (CAD tools. As well, the) 317.88 480 P 0.08 (y lik) 406.89 480 P 0.08 (ely mak) 423.13 480 P 0.08 (e it easier to implement intel-) 451.86 480 P 0.84 (lectual-property \322cores.) 317.88 470 P 0.84 (\323 These cores are sometimes pro) 403.06 470 P 0.84 (vided as) 527.42 470 P 1.19 (\322hard\323 \050placed-and-routed\051 macros. If there is only one type of) 317.88 460 P 0.65 (routing resource in the FPGA, it is easier to map se) 317.88 450 P 0.65 (v) 508.36 450 P 0.65 (eral of these) 512.72 450 P 0.2 (hard cores into one FPGA and ensure each gets the wires it needs.) 317.88 440 P 0.31 (These f) 317.88 430 P 0.31 (actors may mak) 344.84 430 P 0.31 (e a simple FPGA architecture, in which all) 402.36 430 P 0.17 (the wires are essentially the same, attracti) 317.88 420 P 0.17 (v) 468.38 420 P 0.17 (e despite its suboptimal) 472.74 420 P (speed and area performance.) 317.88 410 T 0.16 (T) 335.88 396 P 0.16 (able 3 also lists four of the best tw) 340.66 396 P 0.16 (o-wire-type architectures.) 465.37 396 P 318 540/G1004294 FmPA 1.64 (Each of these architectures combines some b) 317.88 386 P 1.64 (uf) 488.97 386 P 1.64 (fered wires with) 496.25 386 P 1.31 (some pass-transistor) 317.88 376 P 1.31 (-switched wires. T) 392.25 376 P 1.31 (w) 464.44 376 P 1.31 (o of these architectures) 470.85 376 P 0.02 (use only length 4 wires, while the other tw) 317.88 366 P 0.02 (o use some length 4 and) 471.17 366 P 0.01 (some length 8 wires. Notice that these architectures are all signi\336-) 317.88 356 P 0.2 (cantly \05010.2% to 19%\051 f) 317.88 346 P 0.2 (aster than the 4000X-lik) 405.32 346 P 0.2 (e architecture, b) 493.06 346 P 0.2 (ut) 551 346 P 2 F (T) 192.46 321 T (able 3:) 197.64 321 T 1 F ( Comparison of k) 223.38 321 T (e) 288.29 321 T (y architectures \05020 circuit a) 292.15 321 T (v) 390.44 321 T (erage\051.) 394.81 321 T 53 465/G1010453 FmPA (Se) 80.59 294 T (gmentation of Routing T) 89.45 294 T (racks, and Switch T) 178.39 294 T (ypes Used) 249.16 294 T 53 438/G1010463 FmPA (Delay \050ns\051) 315.98 294 T 314 438/G1010465 FmPA (Speedup vs.) 361.51 304 T 356 448/G1010467 FmPA (4000X-lik) 362.8 294 T (e) 399.71 294 T (FPGA) 371.76 284 T (Routing Area \050Min.) 414.81 304 T 411 448/G1010469 FmPA (W) 420.15 294 T (idth T) 428.29 294 T (ransistor) 449.72 294 T (Areas\051) 438.44 284 T -0.24 (Routing Area vs.) 493.91 304 P 490 448/G1010471 FmPA (4000X-lik) 504.08 294 T (e) 540.98 294 T (FPGA) 513.03 284 T (Xilinx 4000X-lik) 60.18 267 T (e: 25% L1, 12.5% L2, 37.5% L4, 25% one-quarter) 122.35 267 T 53 411/G1010473 FmPA (longs; mix of b) 94.83 257 T (uf) 149.41 257 T (fers and pass transistor switches) 156.68 257 T (48.83) 324.72 263 T 314 407/G1010475 FmPA (\321) 378.76 263 T 356 407/G1010477 FmPA (4425) 441.43 263 T 411 407/G1010479 FmPA (\321) 520.03 263 T 490 407/G1010481 FmPA (100% L1, pass-transistor) 121.22 243 T (-switched) 210.78 243 T 53 387/G1010483 FmPA (120.7) 324.72 243.5 T 314 387/G1010485 FmPA 2 F (-) 373.51 243.5 T 1 F (60%) 376.51 243.5 T 356 387/G1010487 FmPA (5891) 441.43 243.5 T 411 387/G1010489 FmPA (+33.1%) 510.37 243.5 T 490 387/G1010491 FmPA (100% L8, pass-transistor) 121.22 230 T (-switched) 210.78 230 T 53 374/G1010493 FmPA (46.22) 324.72 230 T 314 374/G1010495 FmPA (+5.6%) 371.35 230 T 356 374/G1010497 FmPA (5131) 441.43 230 T 411 374/G1010499 FmPA (+16.0%) 510.37 230 T 490 374/G1010501 FmPA (100% L4, b) 136.43 217 T (uf) 178.49 217 T (fer) 185.76 217 T (-switched) 195.57 217 T 53 361/G1010503 FmPA (45.57) 324.72 217 T 314 361/G1010505 FmPA (+7.2%) 371.35 217 T 356 361/G1010507 FmPA (5792) 441.43 217 T 411 361/G1010509 FmPA (+30.9%) 510.37 217 T 490 361/G1010511 FmPA (67% L4, pass-transistor switched;) 122.5 203 T 53 347/G1010513 FmPA (33% L4, b) 138.68 193 T (uf) 176.24 193 T (fer) 183.51 193 T (-switched) 193.32 193 T (42.91) 324.72 198.5 T 314 342/G1010515 FmPA (+13.8%) 369.1 198.5 T 356 342/G1010517 FmPA (4771) 441.43 198.5 T 411 342/G1010519 FmPA (+7.8%) 512.62 198.5 T 490 342/G1010521 FmPA (83% L4, pass-transistor) 123.47 180 T (-switched) 208.53 180 T 53 324/G1010523 FmPA (17% L4, b) 138.68 170 T (uf) 176.24 170 T (fer) 183.51 170 T (-switched) 193.32 170 T (44.31) 324.72 175 T 314 319/G1010525 FmPA (+10.2%) 369.1 175 T 356 319/G1010527 FmPA (4569) 441.43 175 T 411 319/G1010529 FmPA (+3.3%) 512.62 175 T 490 319/G1010531 FmPA (50% L4, pass-transistor) 123.47 157 T (-switched) 208.53 157 T 53 301/G1010533 FmPA (50% L8, b) 138.68 147 T (uf) 176.24 147 T (fer) 183.51 147 T (-switched) 193.32 147 T (41.04) 324.72 152 T 314 296/G1010535 FmPA (+19.0%) 369.1 152 T 356 296/G1010537 FmPA (5039) 441.43 152 T 411 296/G1010539 FmPA (+13.9%) 510.37 152 T 490 296/G1010541 FmPA (83% L4, pass-transistor) 123.47 134 T (-switched) 208.53 134 T 53 278/G1010543 FmPA (17% L8, b) 138.68 124 T (uf) 176.24 124 T (fer) 183.51 124 T (-switched) 193.32 124 T (43.84) 324.72 129 T 314 273/G1010545 FmPA (+11.4%) 369.1 129 T 356 273/G1010547 FmPA (4539) 441.43 129 T 411 273/G1010549 FmPA (+2.6%) 512.62 129 T 490 273/G1010551 FmPA (50% L4, pass-transistor) 67.15 110 T (-switched; 50% L8, b) 152.21 110 T (uf) 229.52 110 T (fer) 236.79 110 T (-switched with) 246.6 110 T 53 254/G1010553 FmPA (reduced \322switch-block population\323) 120.51 100 T (41.23) 324.72 105.5 T 314 249/G1010555 FmPA (+18.4%) 369.1 105.5 T 356 249/G1010557 FmPA (4708) 441.43 105.5 T 411 249/G1010559 FmPA (+6.4%) 512.62 105.5 T 490 249/G1010561 FmPA (83% L4, pass-transistor) 67.15 87 T (-switched; 17% L8, b) 152.21 87 T (uf) 229.52 87 T (fer) 236.79 87 T (-switched with) 246.6 87 T 53 231/G1010563 FmPA (reduced \322switch-block population\323) 120.51 77 T (44.04) 324.72 82 T 314 226/G1010565 FmPA (+10.9%) 369.1 82 T 356 226/G1010567 FmPA (4426) 441.43 82 T 411 226/G1010569 FmPA (0%) 518.53 82 T 490 226/G1010571 FmPA 53.31 313.75 53.31 72.25 2 L V 0.5 H 0 Z N 313.68 314.25 313.68 71.75 2 L V N 356.01 314.25 356.01 71.75 2 L V N 410.5 314.25 410.5 71.75 2 L V N 490.36 314.25 490.36 71.75 2 L V N 558.69 313.75 558.69 72.25 2 L V N 53.06 314 558.94 314 2 L V N 53.56 278.25 558.44 278.25 2 L V N 53.56 275.75 558.44 275.75 2 L V N 53.06 252 558.94 252 2 L V 2 H N 53.06 238 558.94 238 2 L V 0.5 H N 53.06 225 558.94 225 2 L V N 53.06 212 558.94 212 2 L V 2 H N 53.06 188 558.94 188 2 L V 0.5 H N 53.06 165 558.94 165 2 L V N 53.06 142 558.94 142 2 L V N 53.06 119 558.94 119 2 L V 2 H N 53.06 95 558.94 95 2 L V 0.5 H N 53.06 72 558.94 72 2 L V N 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.8/DEST FmPD2 223 471/M9.39943.TableTitle.Table.77.Comparison.of.key.architectures.20.circuit.average FmPA 223 471/I1.1010452 FmPA [/Rect[159 533 187 543]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD [/Rect[182 416 209 426]/Border[0 0 0]/Page 4/View[/XYZ null 373 409 FmDC exch pop null]/LNK FmPD [/Rect[192 701 201 711]/Border[0 0 0]/Page 10/View[/XYZ null 338 396 FmDC exch pop null]/LNK FmPD [/Rect[206 701 215 711]/Border[0 0 0]/Page 10/View[/XYZ null 338 350 FmDC exch pop null]/LNK FmPD [/Rect[57 611 66 621]/Border[0 0 0]/Page 10/View[/XYZ null 338 350 FmDC exch pop null]/LNK FmPD [/Rect[72 597 99 607]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD [/Rect[336 393 363 403]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 326 567 729]/ARTICLE FmPD2 [/Title(A)/Rect[45 63 567 336]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "8" 8 %%Page: "9" 9 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 1 9 Q 0 X 0 0 0 1 0 0 0 K 1.1 (none of them is as area-ef) 54 512.31 P 1.1 (\336cient. The area penalty for using an) 151.98 512.31 P 0.62 (architecture that is 19% f) 54 502.31 P 0.62 (aster than the 4000X-lik) 146.88 502.31 P 0.62 (e architecture is) 235.9 502.31 P 1.54 (13.9%, while the area penalty for an architecture that is 11.4%) 54 492.31 P 1.63 (f) 54 482.31 P 1.63 (aster than the 4000X-lik) 56.91 482.31 P 1.63 (e architecture is only 2.6%. Both the) 148.95 482.31 P 1.38 (speed and the area of these architectures are signi\336cantly better) 54 472.31 P 0.31 (than the best single-wire-type architecture discussed abo) 54 462.31 P 0.31 (v) 259.18 462.31 P 0.31 (e, sho) 263.54 462.31 P 0.31 (w-) 284.62 462.31 P 1.77 (ing that a mix of pass transistors and b) 54 452.31 P 1.77 (uf) 206.44 452.31 P 1.77 (fers is v) 213.71 452.31 P 1.77 (ery useful in) 245.6 452.31 P (FPGA routing.) 54 442.31 T -0.07 (The last tw) 72 428.31 P -0.07 (o lines in T) 111.77 428.31 P -0.07 (able 3 sho) 151.6 428.31 P -0.07 (w the bene\336ts of reducing the) 187.73 428.31 P 54 572/G1004300 FmPA 3 F 0.01 (switc) 54 418.31 P 0.01 (h-bloc) 72.37 418.31 P 0.01 (k population) 95.18 418.31 P 1 F 0.01 ( [6, 7] of these tw) 140.45 418.31 P 0.01 (o-wire-type architectures) 203.89 418.31 P 0.07 (so that the b) 54 408.31 P 0.07 (uf) 97.78 408.31 P 0.07 (fered wires ha) 105.05 408.31 P 0.07 (v) 155.99 408.31 P 0.07 (e a switch block only once e) 160.35 408.31 P 0.07 (v) 262.53 408.31 P 0.07 (ery tw) 266.9 408.31 P 0.07 (o) 289.62 408.31 P 0.18 (logic blocks.) 54 398.31 P 1 7.2 Q 0.15 (1) 100.18 401.91 P 1 9 Q 0.18 ( As Figure 9 \050a\051 sho) 103.78 398.31 P 0.18 (ws, ordinarily routing wires can) 178.65 398.31 P 0.71 (connect to at least one wire se) 54 388.31 P 0.71 (gment in e) 166.09 388.31 P 0.71 (v) 205.29 388.31 P 0.71 (ery channel the) 209.65 388.31 P 0.71 (y cross.) 265.92 388.31 P 3.06 (W) 54 378.31 P 3.06 (e ha) 61.78 378.31 P 3.06 (v) 79.4 378.31 P 3.06 (e found that the area-ef) 83.76 378.31 P 3.06 (\336cienc) 179.24 378.31 P 3.06 (y of an FPGA can be) 203.09 378.31 P 1.25 (impro) 54 368.31 P 1.25 (v) 75.37 368.31 P 1.25 (ed by remo) 79.73 368.31 P 1.25 (ving some routing switches from some of the) 122.6 368.31 P 0.17 (FPGA wire se) 54 358.31 P 0.17 (gments, ho) 105.19 358.31 P 0.17 (we) 144.64 358.31 P 0.17 (v) 154.91 358.31 P 0.17 (er) 159.27 358.31 P 0.17 (. Figure 9 \050b\051 sho) 165.77 358.31 P 0.17 (ws a routing wire) 230.88 358.31 P 0.62 (which has programmable switches allo) 54 348.31 P 0.62 (wing it to connect to other) 196.25 348.31 P 1.45 (routing wires only in e) 54 338.31 P 1.45 (v) 141.08 338.31 P 1.45 (ery second channel \050or switch block\051 it) 145.44 338.31 P -0.14 (crosses. Reducing the number of programmable switches connect-) 54 328.31 P 1.81 (ing to some of the wires reduces routing \337e) 54 318.31 P 1.81 (xibility) 224.34 318.31 P 1.81 (, and hence) 249.76 318.31 P 0.74 (more tracks per channel are required for successful routing. The) 54 308.31 P 0.98 (area sa) 54 298.31 P 0.98 (v) 79.54 298.31 P 0.98 (ed by reducing the a) 83.9 298.31 P 0.98 (v) 160.63 298.31 P 0.98 (erage number of switches per wire) 165 298.31 P 0.32 (se) 54 288.31 P 0.32 (gment outweighs this cost, ho) 61.36 288.31 P 0.32 (we) 169.66 288.31 P 0.32 (v) 179.93 288.31 P 0.32 (er) 184.29 288.31 P 0.32 (, so the net result is a reduc-) 190.92 288.31 P 0.34 (tion in routing area. As T) 54 278.31 P 0.34 (able 3 sho) 148.57 278.31 P 0.34 (ws, architectures in which the) 185.53 278.31 P 1.54 (b) 54 268.31 P 1.54 (uf) 58.32 268.31 P 1.54 (fered wires can connect to other wires only at e) 65.59 268.31 P 1.54 (v) 249.47 268.31 P 1.54 (ery second) 253.84 268.31 P 0.76 (switch block are from 2.5% to 7% more area-ef) 54 258.31 P 0.76 (\336cient than those) 231.09 258.31 P 1.15 (that used a switch-block population of 100% for all wires. The) 54 248.31 P -0.09 (e) 54 238.31 P -0.09 (xact amount of area impro) 57.86 238.31 P -0.09 (v) 152.34 238.31 P -0.09 (ement depends on the fraction of rout-) 156.7 238.31 P 1.73 (ing wires that use b) 54 228.31 P 1.73 (uf) 130.75 228.31 P 1.73 (fered switches. Notice that one of these) 138.02 228.31 P 0.51 (architectures is 18.4% f) 54 218.31 P 0.51 (aster than the 4000X-lik) 140.43 218.31 P 0.51 (e architecture and) 229.12 218.31 P 0 (only 6.4% lar) 54 208.31 P 0 (ger) 102.59 208.31 P 0 (, and another architecture is 10.9% f) 113.72 208.31 P 0 (aster and uses) 244.12 208.31 P (the same area as the 4000X-lik) 54 198.31 T (e architecture.) 165.13 198.31 T 0.89 (From the results of T) 72 184.31 P 0.89 (able 3 one can see that we ha) 150.84 184.31 P 0.89 (v) 261.62 184.31 P 0.89 (e found) 265.98 184.31 P 54 328/G1004315 FmPA 0.9 (man) 54 174.31 P 0.9 (y architectures with speed superior to that of the 4000X-lik) 69.36 174.31 P 0.9 (e) 290.12 174.31 P -0.2 (architecture, b) 54 164.31 P -0.2 (ut none with superior density) 105.1 164.31 P -0.2 (. W) 208.71 164.31 P -0.2 (e belie) 222.84 164.31 P -0.2 (v) 246.16 164.31 P -0.2 (e the 4000X) 250.53 164.31 P 0.42 (contains too man) 54 154.31 P 0.42 (y short wire se) 116.19 154.31 P 0.42 (gments, and this reduces its speed) 170.05 154.31 P -0.05 (v) 54 144.31 P -0.05 (ersus man) 58.37 144.31 P -0.05 (y of the architectures we ha) 94.43 144.31 P -0.05 (v) 193.24 144.31 P -0.05 (e in) 197.6 144.31 P -0.05 (v) 210.45 144.31 P -0.05 (estig) 214.81 144.31 P -0.05 (ated. The 4000X) 231.77 144.31 P 54 132 294.12 139.5 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 54.5 137.5 207 137.5 2 L 0.5 H 2 Z 0 X 0 0 0 1 0 0 0 K N 0 0 612 792 C 1 9 Q 0 X 0 0 0 1 0 0 0 K (1.) 54 126 T 0.25 (Space limitations preclude a thorough discussion of the) 64.8 126 P 3 F 0.25 (switc) 268.25 126 P 0.25 (h-) 286.62 126 P 54 270/G1008135 FmPA 0.85 (bloc) 64.8 116 P 0.85 (k population) 80.12 116 P 1 F 0.85 ( issue in this paper) 126.22 116 P 0.85 (. F) 196.11 116 P 0.85 (or complete de\336nitions) 209.43 116 P 1.02 (and e) 64.8 106 P 1.02 (xperimental results sho) 84.93 106 P 1.02 (wing wh) 170.25 106 P 1.02 (y it is best to reduce the) 202.48 106 P 0.04 (switch-block population to one switch e) 64.8 96 P 0.04 (v) 208.5 96 P 0.04 (ery tw) 212.87 96 P 0.04 (o potential loca-) 235.55 96 P 1.63 (tions \050rather than one switch e) 64.8 86 P 1.63 (v) 181.48 86 P 1.63 (ery 3 potential locations, for) 185.84 86 P (e) 64.8 76 T (xample\051 see [6, 7].) 68.66 76 T 0.54 (uses a more adv) 317.88 714 P 0.54 (anced switch block than the disjoint switch block) 377 714 P -0.09 (used by all the other architectures in T) 317.88 704 P -0.09 (able 3, ho) 454.78 704 P -0.09 (we) 489.63 704 P -0.09 (v) 499.9 704 P -0.09 (er) 504.27 704 P -0.09 (. The 4000X) 510.76 704 P 0.6 (switch block contains some switches that allo) 317.88 694 P 0.6 (w wires of dif) 485.21 694 P 0.6 (ferent) 537.01 694 P 0.37 (lengths to connect, and that allo) 317.88 684 P 0.37 (w wires in dif) 434.01 684 P 0.37 (ferent tracks to con-) 484.65 684 P 0.4 (nect. These features mak) 317.88 674 P 0.4 (e the 4000X switch block more routable) 411.11 674 P 1.67 (than the disjoint switch block, yet it contains only a fe) 317.88 664 P 1.67 (w more) 529.09 664 P 0.22 (switches than the disjoint switch block. Consequently) 317.88 654 P 0.22 (, this switch) 514.31 654 P 0.04 (block tends to result in FPGAs with superior density) 317.88 644 P 0.04 (. W) 506.62 644 P 0.04 (e consider) 521.22 644 P 1.71 (the in) 317.88 634 P 1.71 (v) 339.48 634 P 1.71 (estig) 343.85 634 P 1.71 (ation of better switch block topologies for use with) 360.8 634 P 0.35 (FPGAs that contain some long wires to be a fertile area for future) 317.88 624 P -0.12 (research. W) 317.88 614 P -0.12 (e e) 362.15 614 P -0.12 (xpect that combining the se) 372.14 614 P -0.12 (gmentation distrib) 470.54 614 P -0.12 (utions) 535.99 614 P 0.62 (of some of the architectures listed in T) 317.88 604 P 0.62 (able 3 with a better switch) 460.19 604 P (block w) 317.88 594 T (ould lead to signi\336cantly impro) 346.54 594 T (v) 459.4 594 T (ed area-ef) 463.77 594 T (\336cienc) 499.27 594 T (y) 523.12 594 T (.) 527.04 594 T 2 12 Q (7) 317.88 570 T (Summary) 335.88 570 T 318 714/G1004341 FmPA 1 9 Q 2.39 (W) 335.88 554 P 2.39 (e ha) 343.66 554 P 2.39 (v) 360.61 554 P 2.39 (e in) 364.98 554 P 2.39 (v) 380.25 554 P 2.39 (estig) 384.62 554 P 2.39 (ated a lar) 401.58 554 P 2.39 (ge number of dif) 439.18 554 P 2.39 (ferent routing) 506.37 554 P 318 698/G1004342 FmPA 0.83 (architecture issues in this w) 317.88 544 P 0.83 (ork. First, we sho) 420.59 544 P 0.83 (wed that it is most) 488.68 544 P 0.72 (important for FPGAs to contain wires of moderate length \0504 to 8) 317.88 534 P 0.36 (logic blocks\051. While most commercial FPGAs contain some v) 317.88 524 P 0.36 (ery) 546.51 524 P 1.05 (short and some v) 317.88 514 P 1.05 (ery long wires, we ha) 382.15 514 P 1.05 (v) 463.42 514 P 1.05 (e found FPGAs that use) 467.79 514 P 0.58 (signi\336cant numbers of these types of wires to be inferior to those) 317.88 504 P (that emplo) 317.88 494 T (y medium-length wires.) 356.04 494 T 0.19 (W) 335.88 480 P 0.19 (e also found that FPGAs that contain a mix of pass-transis-) 343.66 480 P 318 624/G1004344 FmPA 0.11 (tor and tri-state b) 317.88 470 P 0.11 (uf) 379.76 470 P 0.11 (fer routing switches are superior to FPGAs that) 387.03 470 P 0.55 (emplo) 317.88 460 P 0.55 (y only one type of switch. The f) 340.29 460 P 0.55 (astest FPGAs tend to con-) 461.81 460 P 1.32 (tain about 50% pass-transistor switches and 50% tri-state b) 317.88 450 P 1.32 (uf) 540.74 450 P 1.32 (fer) 548.01 450 P 0.45 (switches, while the most area-ef) 317.88 440 P 0.45 (\336cient FPGAs contain about 80%) 435.19 440 P (pass-transistor switches and only 20% tri-state b) 317.88 430 T (uf) 491.68 430 T (fer switches.) 498.95 430 T -0.08 (W) 335.88 416 P -0.08 (e also found that reducing the switch-block internal popula-) 343.66 416 P 318 560/G1004349 FmPA 1.26 (tion of routing wires that interconnect with tri-state b) 317.88 406 P 1.26 (uf) 518.74 406 P 1.26 (fers pro-) 526.01 406 P 0.37 (duces an area g) 317.88 396 P 0.37 (ain of 2.5% to 7.5% for typical architectures. The) 374.18 396 P 0.98 (switch-block population of these b) 317.88 386 P 0.98 (uf) 446.1 386 P 0.98 (fered wires should be set so) 453.38 386 P 0.75 (that each wire connects to orthogonal wires at only e) 317.88 376 P 0.75 (v) 514.15 376 P 0.75 (ery second) 518.51 376 P (channel it crosses.) 317.88 366 T 1.54 (Finally) 335.88 352 P 1.54 (, we sho) 360.8 352 P 1.54 (wed that the best architectures e) 393.41 352 P 1.54 (xamined in) 516.21 352 P 318 496/G1007522 FmPA 1.02 (this paper ha) 317.88 342 P 1.02 (v) 365.73 342 P 1.02 (e signi\336cantly superior speed to a \050slightly simpli-) 370.1 342 P 0.13 (\336ed\051 Xilinx XC4000X routing architecture; some architectures are) 317.88 332 P 0.54 (19% f) 317.88 322 P 0.54 (aster than the 4000X architecture. This 4000X-lik) 340.07 322 P 0.54 (e routing) 525.22 322 P 0.12 (architecture has better area-ef) 317.88 312 P 0.12 (\336cienc) 424.72 312 P 0.12 (y than all b) 448.58 312 P 0.12 (ut one of the archi-) 489.02 312 P 1.96 (tectures we e) 317.88 302 P 1.96 (xamined, ho) 368.64 302 P 1.96 (we) 414.88 302 P 1.96 (v) 425.14 302 P 1.96 (er) 429.51 302 P 1.96 (. The best architectures in this) 436.01 302 P 0.6 (paper ha) 317.88 292 P 0.6 (v) 349.03 292 P 0.6 (e a better area-delay product than the 4000X-lik) 353.39 292 P 0.6 (e archi-) 530.17 292 P 0.85 (tecture, indicating that the) 317.88 282 P 0.85 (y ha) 414.29 282 P 0.85 (v) 430.21 282 P 0.85 (e g) 434.58 282 P 0.85 (ained more in speed than the) 446.13 282 P 0.85 (y) 553.5 282 P 2.3 (ha) 317.88 272 P 2.3 (v) 326.2 272 P 2.3 (e sacri\336ced in area. The) 330.56 272 P 2.3 (y are also less comple) 429.88 272 P 2.3 (x than the) 517.91 272 P 1.22 (4000X. This is a useful feature, as it simpli\336es both CAD tool) 317.88 262 P 0.4 (design and the implementation of pre-placed and pre-routed intel-) 317.88 252 P (lectual property cores.) 317.88 242 T 1.15 (While prior researchers and this w) 335.88 228 P 1.15 (ork ha) 465.27 228 P 1.15 (v) 488.99 228 P 1.15 (e answered man) 493.35 228 P 1.15 (y) 553.5 228 P 318 372/G1008156 FmPA 3.98 (important questions about FPGA routing architecture, much) 317.88 218 P 0.79 (remains to be done. W) 317.88 208 P 0.79 (e belie) 404.59 208 P 0.79 (v) 428.9 208 P 0.79 (e one of the most fertile areas for) 433.26 208 P 0.46 (future research concerns \336nding good switch block topologies for) 317.88 198 P 1.42 (use with FPGAs that contain wires longer than length 1. Prior) 317.88 188 P 0.81 (research into this area has focused on switch blocks for use with) 317.88 178 P -0.18 (FPGAs that contain only length 1 wires, b) 317.88 168 P -0.18 (ut we ha) 467.96 168 P -0.18 (v) 497.92 168 P -0.18 (e found that the) 502.29 168 P -0.2 (best switch block for an architecture with only length 1 wires is not) 317.88 158 P 0.01 (necessarily the best switch block for an FPGA that contains longer) 317.88 148 P (wires.) 317.88 138 T 2 12 Q (Ackno) 391 120 T (wledgments) 424.22 120 T 318 264/G1007553 FmPA 1 9 Q 0.31 (The authors are indebted to Jordan Sw) 335.88 104 P 0.31 (artz, who modi\336ed the) 476.09 104 P 318 248/G1007554 FmPA 1.01 (FPGA \322architecture generator\323 within VPR to allo) 317.88 94 P 1.01 (w tar) 505.66 94 P 1.01 (geting of) 524.75 94 P 1.23 (the 4000X-lik) 317.88 84 P 1.23 (e architecture. W) 369.26 84 P 1.23 (e w) 436.19 84 P 1.23 (ould also lik) 450.07 84 P 1.23 (e to thank Ste) 496.94 84 P 1.23 (v) 549.64 84 P 1.23 (e) 554 84 P 54 72 294.12 720 C 54 518.31 293.76 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 71.41 682.25 89.19 700.04 R 7 X 0 0 0 1 0 0 0 K V 0.5 H 0 Z 0 X N 108.17 682.25 125.95 700.04 R 7 X V 0 X N 144.93 682.25 162.71 700.04 R 7 X V 0 X N 181.69 682.25 199.48 700.04 R 7 X V 0 X N 218.45 682.25 236.24 700.04 R 7 X V 0 X N 255.21 682.25 273 700.04 R 7 X V 0 X N 71.41 649.94 89.19 667.73 R 7 X V 0 X N 108.17 649.94 125.95 667.73 R 7 X V 0 X N 144.93 649.94 162.71 667.73 R 7 X V 0 X N 181.69 649.94 199.48 667.73 R 7 X V 0 X N 218.45 649.94 236.24 667.73 R 7 X V 0 X N 255.21 649.94 273 667.73 R 7 X V 0 X N 97.35 646.98 97.35 667.28 2 L 2 H N 97.35 683.29 97.35 701.83 2 L N 245.43 646.24 245.43 667.28 2 L N 245.43 681.96 245.43 704.64 2 L N 88.9 675.29 61.77 675.29 2 L N 107.13 675.29 236.09 675.29 2 L N 255.65 675.29 279.67 675.29 2 L N J 97.79 683.74 107.13 674.84 2 L J 97.79 683.74 98.51 683.05 2 L 0.5 H N [2.179 4.358] 2.179 I 98.51 683.05 106.4 675.53 2 L N J 106.4 675.53 107.13 674.84 2 L N J 107.13 675.29 97.79 666.84 2 L J 107.13 675.29 106.39 674.62 2 L N [2.119 4.237] 2.119 I 106.39 674.62 98.53 667.51 2 L N J 98.53 667.51 97.79 666.84 2 L N J 235.64 675.73 245.43 668.62 2 L J 235.64 675.73 236.45 675.14 2 L N [2.019 4.039] 2.019 I 236.45 675.14 244.62 669.21 2 L N J 244.62 669.21 245.43 668.62 2 L N J 245.43 682.85 235.64 676.18 2 L J 245.43 682.85 244.6 682.28 2 L N [1.968 3.936] 1.968 I 244.6 682.28 236.47 676.74 2 L N J 236.47 676.74 235.64 676.18 2 L N J 89.79 675.29 106.24 675.29 2 L J 89.79 675.29 90.79 675.29 2 L N [1.807 3.613] 1.807 I 90.79 675.29 105.24 675.29 2 L N J 105.24 675.29 106.24 675.29 2 L N J 236.09 675.29 256.1 675.29 2 L J 236.09 675.29 237.09 675.29 2 L N [1.637 3.275] 1.637 I 237.09 675.29 255.1 675.29 2 L N J 255.1 675.29 256.1 675.29 2 L N J 139.15 645.5 139.15 701.09 2 L 2 H N 175.16 647.28 175.16 702.86 2 L N 211.18 646.84 211.18 702.42 2 L N J 128.62 676.77 139.1 685.22 2 L J 128.62 676.77 129.4 677.4 2 L 0.5 H N [2.292 4.584] 2.292 I 129.4 677.4 138.32 684.59 2 L N J 138.32 684.59 139.1 685.22 2 L N J 164.64 676.33 175.12 684.77 2 L J 164.64 676.33 165.42 676.95 2 L N [2.292 4.584] 2.292 I 165.42 676.95 174.34 684.15 2 L N J 174.34 684.15 175.12 684.77 2 L N J 199.92 676.62 210.4 685.07 2 L J 199.92 676.62 200.7 677.25 2 L N [2.292 4.584] 2.292 I 200.7 677.25 209.62 684.44 2 L N J 209.62 684.44 210.4 685.07 2 L N J 67.83 713.08 97 713.08 2 L 2 H 2 Z N 1 9 Q (Routing wire) 105.33 711.33 T J 181.17 713.08 212 713.08 2 L J 181.17 713.08 182.92 713.08 2 L 0.5 H N [3.357 4.316] 3.357 I 182.92 713.08 210.25 713.08 2 L N J 210.25 713.08 212 713.08 2 L N (Routing switch) 217.83 711.33 T J 73.14 598.25 90.92 616.04 R 7 X V 0 Z 0 X N 109.9 598.25 127.68 616.04 R 7 X V 0 X N 146.66 598.25 164.44 616.04 R 7 X V 0 X N 183.42 598.25 201.2 616.04 R 7 X V 0 X N 220.18 598.25 237.96 616.04 R 7 X V 0 X N 256.94 598.25 274.72 616.04 R 7 X V 0 X N 73.14 565.94 90.92 583.73 R 7 X V 0 X N 109.9 565.94 127.68 583.73 R 7 X V 0 X N 146.66 565.94 164.44 583.73 R 7 X V 0 X N 183.42 565.94 201.2 583.73 R 7 X V 0 X N 220.18 565.94 237.96 583.73 R 7 X V 0 X N 256.94 565.94 274.72 583.73 R 7 X V 0 X N 99.07 562.98 99.07 583.28 2 L 2 H N 99.07 599.29 99.07 617.83 2 L N 247.15 562.24 247.15 583.28 2 L N 247.15 597.96 247.15 620.64 2 L N 90.63 591.29 63.5 591.29 2 L N 108.86 591.29 237.82 591.29 2 L N 257.38 591.29 281.39 591.29 2 L N J 99.52 599.74 108.86 590.84 2 L J 99.52 599.74 100.24 599.05 2 L 0.5 H N [2.179 4.358] 2.179 I 100.24 599.05 108.13 591.53 2 L N J 108.13 591.53 108.86 590.84 2 L N J 108.86 591.29 99.52 582.84 2 L J 108.86 591.29 108.12 590.62 2 L N [2.119 4.237] 2.119 I 108.12 590.62 100.26 583.51 2 L N J 100.26 583.51 99.52 582.84 2 L N J 237.37 591.73 247.15 584.62 2 L J 237.37 591.73 238.18 591.14 2 L N [2.019 4.039] 2.019 I 238.18 591.14 246.35 585.21 2 L N J 246.35 585.21 247.15 584.62 2 L N J 247.15 598.85 237.37 592.18 2 L J 247.15 598.85 246.33 598.28 2 L N [1.968 3.936] 1.968 I 246.33 598.28 238.2 592.74 2 L N J 238.2 592.74 237.37 592.18 2 L N J 91.52 591.29 107.97 591.29 2 L J 91.52 591.29 92.52 591.29 2 L N [1.807 3.613] 1.807 I 92.52 591.29 106.97 591.29 2 L N J 106.97 591.29 107.97 591.29 2 L N J 237.82 591.29 257.83 591.29 2 L J 237.82 591.29 238.82 591.29 2 L N [1.637 3.275] 1.637 I 238.82 591.29 256.83 591.29 2 L N J 256.83 591.29 257.83 591.29 2 L N J 140.88 561.5 140.88 617.09 2 L 2 H N 176.9 563.28 176.9 618.86 2 L N 212.91 562.84 212.91 618.42 2 L N J 166.37 592.33 176.85 600.77 2 L J 166.37 592.33 167.15 592.95 2 L 0.5 H N [2.292 4.584] 2.292 I 167.15 592.95 176.07 600.15 2 L N J 176.07 600.15 176.85 600.77 2 L N 0 0 0 1 0 0 0 K J 0 0 0 1 0 0 0 K 2 F (Figur) 57.2 535.17 T (e 9:) 78.54 535.17 T 1 F ( Examples of dif) 92.28 535.17 T (ferent switch-block population v) 154.05 535.17 T (alues.) 271.06 535.17 T 55 679/G1008083 FmPA (\050a\051 Full switch-block population \0505/5 or 100%\051) 81 634.3 T (\050b\051 Reduced switch-block population \0503/5 or 60%\051) 76.5 550.46 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 54 72 294.12 720 C 0 0 612 792 C 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.9/DEST FmPD2 0 792 0.01 792 C 0 0 612 792 C 92 685/M9.16150.Figure.Figure.9.Examples.of.different.switchblock.population.values FmPA 0 792 0.01 792 C 0 0 612 792 C 92 685/I1.1008082 FmPA [/Rect[146 415 150 425]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[144 275 171 285]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[121 395 152 407]/Border[0 0 0]/Page 9/View[/XYZ null 92 685 FmDC exch pop null]/LNK FmPD 0 792 0.01 792 C 0 0 612 792 C [/Rect[173 355 203 365]/Border[0 0 0]/Page 9/View[/XYZ null 92 685 FmDC exch pop null]/LNK FmPD [/Rect[117 73 122 83]/Border[0 0 0]/Page 10/View[/XYZ null 74 653 FmDC exch pop null]/LNK FmPD [/Rect[155 415 159 425]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[126 73 131 83]/Border[0 0 0]/Page 10/View[/XYZ null 74 620 FmDC exch pop null]/LNK FmPD [/Rect[147 425 173 435]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD [/Rect[146 181 173 191]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD [/Rect[450 701 476 711]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD [/Rect[455 601 483 611]/Border[0 0 0]/Page 8/View[/XYZ null 223 471 FmDC exch pop null]/LNK FmPD [/Title(A)/Rect[45 63 567 729]/ARTICLE FmPD2 FMENDPAGE %%EndPage: "9" 9 %%Page: "10" 10 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 1 9 Q 0 X 0 0 0 1 0 0 0 K 0.25 (Y) 52.67 710.67 P 0.25 (oung and Ste) 58.17 710.67 P 0.25 (v) 105.45 710.67 P 0.25 (e T) 109.81 710.67 P 0.25 (rimber) 121.49 710.67 P 0.25 (ger of Xilinx, and Frank Heile of Altera,) 145.32 710.67 P 0.17 (for helpful discussions on the circuit-le) 52.67 700.67 P 0.17 (v) 194.05 700.67 P 0.17 (el design of FPGAs. This) 198.41 700.67 P -0.19 (w) 52.67 690.67 P -0.19 (ork w) 59.08 690.67 P -0.19 (as supported by the Information T) 79.54 690.67 P -0.19 (echnology Research Cen-) 200.69 690.67 P 0.12 (tre of Ontario, the W) 52.67 680.67 P 0.12 (alter C. Sumner F) 127.67 680.67 P 0.12 (oundation, an NSERC 1967) 191.91 680.67 P 1 (Scholarship, a V) 52.67 670.67 P 1 (. L. Henderson Research Fello) 113.26 670.67 P 1 (wship and Xilinx.) 226.53 670.67 P 0.05 (W) 52.67 660.67 P 0.05 (e are also grateful to the Canadian Microelectronics Corporation) 60.44 660.67 P (and TSMC for pro) 52.67 650.67 T (viding 0.35) 119.28 650.67 T 4 F (m) 162.53 650.67 T 1 F (m process information.) 167.71 650.67 T 2 12 Q (Refer) 144.85 632.67 T (ences) 173.28 632.67 T 53 777/G1005576 FmPA 1 9 Q ([1]) 52.67 617.67 T 1.23 (S. Bro) 74.27 617.67 P 1.23 (wn, R. Francis, J. Rose and Z. Vranesic,) 98.28 617.67 P 3 F 1.23 (F) 255.1 617.67 P 1.23 (ield-Pr) 260.2 617.67 P 1.23 (o-) 285.29 617.67 P 53 762/G1008981 FmPA 3.81 (gr) 74.27 607.67 P 3.81 (ammable Gate Arr) 82.13 607.67 P 3.81 (ays) 157.12 607.67 P 1 F 3.81 (, Kluwer Academic Publishers,) 169.11 607.67 P (1992.) 74.27 597.67 T ([2]) 52.67 584.67 T 2.38 (J. Rose and D. Hill, \322) 74.27 584.67 P 2.38 (Architectural and Ph) 162.46 584.67 P 2.38 (ysical Design) 241.66 584.67 P 53 729/G1005876 FmPA -0.2 (Challenges for One-Million Gate FPGAs and Be) 74.27 574.67 P -0.2 (yond,) 248.4 574.67 P -0.2 (\323) 268.02 574.67 P 3 F -0.2 (A) 274.06 574.67 P -0.2 (CM) 279.29 574.67 P (Int. Symp. on FPGAs) 74.27 564.67 T 1 F (, 1997, pp. 129 - 132.) 150.51 564.67 T ([3]) 52.67 551.67 T (Xilinx Inc., The Programmable Logic Data Book, 1994.) 74.27 551.67 T 53 696/G1005608 FmPA ([4]) 52.67 538.67 T (Lucent T) 74.27 538.67 T (echnologies, FPGA Data Book, 1998.) 106.38 538.67 T 53 683/G1005613 FmPA ([5]) 52.67 525.67 T 0.38 (V) 74.27 525.67 P 0.38 (antis Corporation, \322VF1 Field Programmable Gate Array) 79.77 525.67 P 0.38 (,) 287.17 525.67 P 0.38 (\323) 288.79 525.67 P 53 670/G1007765 FmPA 3 F (Pr) 74.27 515.67 T (eliminary Data Sheet) 82.93 515.67 T 1 F (, 1998.) 159.43 515.67 T ([6]) 52.67 502.67 T 0.02 (V) 74.27 502.67 P 0.02 (. Betz, \322) 79.6 502.67 P 0.02 (Architecture and CAD for Speed and Area Optimi-) 108.42 502.67 P 53 647/G1005903 FmPA 1.77 (zation of FPGAs\323,) 74.27 492.67 P 3 F 1.77 (Ph.D. Dissertation) 148.56 492.67 P 1 F 1.77 (, Uni) 218.08 492.67 P 1.77 (v) 237.62 492.67 P 1.77 (ersity of T) 241.99 492.67 P 1.77 (or-) 282.29 492.67 P (onto, 1998.) 74.27 482.67 T ([7]) 52.67 469.67 T -0.22 (V) 74.27 469.67 P -0.22 (. Betz, J. Rose and A. Marquardt,) 79.6 469.67 P 3 F -0.22 (Ar) 200.52 469.67 P -0.22 (c) 209.18 469.67 P -0.22 (hitectur) 213.04 469.67 P -0.22 (e and CAD for) 240.71 469.67 P 53 614/G1010717 FmPA 1.09 (Deep-Submicr) 74.27 459.67 P 1.09 (on FPGAs) 125.85 459.67 P 1 F 1.09 (, Kluwer Academic Publishers, T) 164.68 459.67 P 1.09 (o) 288.29 459.67 P (appear in 1999.) 74.27 449.67 T ([8]) 52.67 436.67 T 0.33 (J. Rose and S. Bro) 74.27 436.67 P 0.33 (wn, \322Fle) 141.87 436.67 P 0.33 (xibility of Interconnection Struc-) 173.06 436.67 P 53 581/G1005893 FmPA 1.78 (tures for Field-Programmable Gate Arrays,) 74.27 426.67 P 1.78 (\323) 235.99 426.67 P 3 F 1.78 (JSSC) 244.01 426.67 P 1 F 1.78 (, March) 263.01 426.67 P (1991, pp. 277 - 282.) 74.27 416.67 T ([9]) 52.67 403.67 T 1.03 (B. Tseng, J. Rose and S. Bro) 74.27 403.67 P 1.03 (wn, \322Using Architectural and) 183.72 403.67 P 53 548/G1005894 FmPA 0.03 (CAD Interactions to Impro) 74.27 393.67 P 0.03 (v) 171.47 393.67 P 0.03 (e FPGA Routing Architectures,) 175.83 393.67 P 0.03 (\323) 288.79 393.67 P 3 F (A) 74.27 383.67 T (CM W) 79.5 383.67 T (orkshop on FPGAs) 101.92 383.67 T 1 F (, 1992, pp. 3 - 8.) 170.91 383.67 T ([10]) 52.67 370.67 T 0.67 (Y) 74.27 370.67 P 0.67 (. Chang, D. F) 79.6 370.67 P 0.67 (. W) 129.4 370.67 P 0.67 (ong, and C. K. W) 142.35 370.67 P 0.67 (ong, \322Uni) 207.56 370.67 P 0.67 (v) 243.51 370.67 P 0.67 (ersal Switch) 247.87 370.67 P 53 515/G1005895 FmPA 1.09 (Modules for FPGA Design,) 74.27 360.67 P 1.09 (\323) 176.41 360.67 P 3 F 1.09 (A) 183.75 360.67 P 1.09 (CM T) 188.98 360.67 P 1.09 (r) 210.33 360.67 P 1.09 (ans. on Design A) 213.69 360.67 P 1.09 (uto-) 278.29 360.67 P (mation of Electr) 74.27 350.67 T (onic Systems) 132.36 350.67 T 1 F (, Jan. 1996, pp. 80 - 101.) 178.6 350.67 T ([11]) 52.67 337.67 T -0.14 (S. W) 74.27 337.67 P -0.14 (ilton, \322) 91.76 337.67 P -0.14 (Architectures and Algorithms for Field-Program-) 115.9 337.67 P 53 482/G1005902 FmPA 0.88 (mable Gate Arrays with Embedded Memories,) 74.27 327.67 P 0.88 (\323) 246.03 327.67 P 3 F 0.88 (Ph.D. Dis-) 253.16 327.67 P 3.57 (sertation) 74.27 317.67 P 1 F 3.57 (, Uni) 106.27 317.67 P 3.57 (v) 127.62 317.67 P 3.57 (ersity of T) 131.98 317.67 P 3.57 (oronto, 1997. \050A) 175.9 317.67 P 3.57 (v) 248.2 317.67 P 3.57 (ailable for) 252.48 317.67 P 10.66 (do) 74.27 307.67 P 10.66 (wnload from http://www) 83.04 307.67 P 10.66 (.ee.ubc.ca/~ste) 193.28 307.67 P 10.66 (v) 246.16 307.67 P 10.66 (e) 250.52 307.67 P 10.66 (w/publica-) 254.29 307.67 P (tions.html\051.) 74.27 297.67 T ([12]) 52.67 284.67 T 2.89 (J. Greene, V) 74.27 284.67 P 2.89 (. Ro) 123.87 284.67 P 2.89 (ycho) 141.67 284.67 P 2.89 (wdhury) 158.94 284.67 P 2.89 (, S. Kaptanoglu and A. El) 185.85 284.67 P 53 429/G1005930 FmPA 0.48 (Gamal, \322Se) 74.27 274.67 P 0.48 (gmented Channel Routing,) 116.11 274.67 P 0.48 (\323) 213.19 274.67 P 3 F 0.48 (D) 219.92 274.67 P 0.48 (A) 226.1 274.67 P 0.48 (C) 231.33 274.67 P 1 F 0.48 (, 1990, pp. 567) 237.34 274.67 P (- 572.) 74.27 264.67 T ([13]) 52.67 251.67 T 0.75 (K. Ro) 74.27 251.67 P 0.75 (y and M. Mehendale, \322Optimization of Channel Se) 96.43 251.67 P 0.75 (g-) 285.29 251.67 P 53 396/G1005927 FmPA 3.88 (mentation for Channelled Architecture FPGAs,) 74.27 241.67 P 3.88 (\323) 259.4 241.67 P 3 F 3.88 (CICC) 269.53 241.67 P 1 F 3.88 (,) 290.54 241.67 P (1992, pp. 4.4.1 - 4.4.4.) 74.27 231.67 T ([14]) 52.67 218.67 T 2.04 (K. Zhu and D. F) 74.27 218.67 P 2.04 (. W) 140.71 218.67 P 2.04 (ong, \322On Channel Se) 155.02 218.67 P 2.04 (gmentation for) 237.5 218.67 P 53 363/G1005924 FmPA (Ro) 74.27 208.67 T (w-Based FPGAs,) 84.54 208.67 T (\323) 146.41 208.67 T 3 F (ICCAD) 152.66 208.67 T 1 F (, 1992, pp. 26 - 29.) 179.66 208.67 T ([15]) 52.67 195.67 T 2.37 (M. Pedram, B. Nobande) 74.27 195.67 P 2.37 (g) 168.74 195.67 P 2.37 (ani and B. Preas, \322Design and) 173.19 195.67 P 53 340/G1005931 FmPA 1.9 (Analysis of Se) 74.27 185.67 P 1.9 (gmented Routing Channels for Ro) 130.43 185.67 P 1.9 (w-Based) 261.3 185.67 P (FPGAs,) 74.27 175.67 T (\323) 102.39 175.67 T 3 F (IEEE T) 108.64 175.67 T (r) 134.89 175.67 T (ans. on CAD) 138.26 175.67 T 1 F (, Dec. 1994, pp. 1470 - 1479.) 184.51 175.67 T ([16]) 52.67 162.67 T -0.11 (S. Bro) 74.27 162.67 P -0.11 (wn, M. Khellah and G. Lemieux, \322Se) 96.94 162.67 P -0.11 (gmented Routing) 230.64 162.67 P 53 307/G1005955 FmPA 1.96 (for Speed-Performance and Routability in Field-Program-) 74.27 152.67 P 0.51 (mable Gate Arrays,) 74.27 142.67 P 0.51 (\323) 144.88 142.67 P 3 F 0.51 (J) 151.63 142.67 P 0.51 (ournal of VLSI Design) 155.4 142.67 P 1 F 0.51 (, V) 238.17 142.67 P 0.51 (ol. 4, No. 4,) 248.52 142.67 P (1996, pp. 275 - 291.) 74.27 132.67 T ([17]) 52.67 119.67 T 0.44 (S. Bro) 74.27 119.67 P 0.44 (wn, M. Khellah and Z. Vranesic, \322Minimizing FPGA) 97.48 119.67 P 53 264/G1005951 FmPA -0.18 (Interconnect Delays,) 74.27 109.67 P -0.18 (\323) 147.93 109.67 P 3 F -0.18 (IEEE Design and T) 153.99 109.67 P -0.18 (est Ma) 222.86 109.67 P -0.18 (gazine) 246.84 109.67 P 1 F -0.18 (, W) 270.33 109.67 P -0.18 (in-) 282.79 109.67 P (ter 1996, pp. 16 - 23.) 74.27 99.67 T ([18]) 52.67 86.67 T -0.02 (P) 74.27 86.67 P -0.02 (. Cho) 78.27 86.67 P -0.02 (w) 97.53 86.67 P -0.02 (, S. Seo, J. Rose, K. Chung, G. P) 103.44 86.67 P -0.02 (aez and I. Rahardja,) 221.13 86.67 P 53 231/G1005952 FmPA 0.59 (\322The Design of an SRAM-Based Field-Programmable Gate) 74.27 76.67 P 1.06 (Array) 338.15 710.67 P 1.06 (, P) 358.55 710.67 P 1.06 (art I: Architecture,) 368.98 710.67 P 1.06 (\323) 440.51 710.67 P 3 F 1.06 (T) 447.82 710.67 P 1.06 (o appear in IEEE T) 451.99 710.67 P 1.06 (r) 526.24 710.67 P 1.06 (ans. on) 529.6 710.67 P (VLSI) 338.15 700.67 T 1 F (.) 356.15 700.67 T ([19]) 316.55 687.67 T 1.4 (V) 338.15 687.67 P 1.4 (. Betz and J. Rose, \322Ho) 343.48 687.67 P 1.4 (w Much Logic Should Go in an) 434.26 687.67 P 317 832/G1006044 FmPA 2.48 (FPGA Logic Block?,) 338.15 677.67 P 2.48 (\323) 418.72 677.67 P 3 F 2.48 (IEEE Design and T) 427.44 677.67 P 2.48 (est Ma) 504.29 677.67 P 2.48 (gazine) 530.92 677.67 P 1 F 2.48 (,) 554.42 677.67 P (Spring 1998, pp. 10 - 15.) 338.15 667.67 T ([20]) 316.55 654.67 T 1.56 (V) 338.15 654.67 P 1.56 (. Betz and J. Rose, \322Ef) 343.48 654.67 P 1.56 (fect of the Pref) 432.55 654.67 P 1.56 (abricated Routing) 490.86 654.67 P 317 799/G1006045 FmPA 0.79 (T) 338.15 644.67 P 0.79 (rack Distrib) 343.33 644.67 P 0.79 (ution on FPGA Area-Ef) 386.68 644.67 P 0.79 (\336cienc) 475.07 644.67 P 0.79 (y) 498.93 644.67 P 0.79 (,) 502.85 644.67 P 0.79 (\323) 504.47 644.67 P 3 F 0.79 (IEEE T) 511.51 644.67 P 0.79 (r) 538.55 644.67 P 0.79 (ans.) 541.91 644.67 P (on VLSI) 338.15 634.67 T 1 F (, Sept. 1998, pp. 445 - 456.) 367.4 634.67 T ([21]) 316.55 621.67 T (Altera Inc., Data Book, 1998.) 338.15 621.67 T 317 766/G1006056 FmPA ([22]) 316.55 608.67 T 3.55 (H. Hseih, et al, \322Third-Generation Architecture Boosts) 338.15 608.67 P 317 753/G1006075 FmPA 2.16 (Speed and Density of Field-Programmable Gate Arrays,) 338.15 598.67 P 2.16 (\323) 552.67 598.67 P 3 F (CICC) 338.15 588.67 T 1 F (, 1990, pp. 31.2.1 - 31.27.) 359.15 588.67 T ([23]) 316.55 575.67 T 1.29 (Canadian Microelectronics Corporation, \3220.35 mm Mix) 338.15 575.67 P 1.29 (ed-) 545.17 575.67 P 317 720/G1006143 FmPA 3.71 (Mode Polycide HSPICE Models,) 338.15 565.67 P 3.71 (\323) 468.15 565.67 P 3 F 3.71 (Con\336dential Pr) 478.11 565.67 P 3.71 (ocess) 537.17 565.67 P (Documentation) 338.15 555.67 T 1 F (, 1997.) 393.64 555.67 T ([24]) 316.55 542.67 T 1.61 (S. Y) 338.15 542.67 P 1.61 (ang, \322Logic Synthesis and Optimization Benchmarks,) 354.86 542.67 P 317 687/G1007725 FmPA -0.09 (V) 338.15 532.67 P -0.09 (ersion 3.0,) 343.65 532.67 P -0.09 (\323) 380.68 532.67 P 3 F -0.09 (T) 386.84 532.67 P -0.09 (ec) 391.01 532.67 P -0.09 (h. Report) 398.87 532.67 P 1 F -0.09 (, Microelectronics Center of North) 432.28 532.67 P (Carolina, 1991.) 338.15 522.67 T ([25]) 316.55 509.67 T 0.09 (E. M. Sento) 338.15 509.67 P 0.09 (vich et al, \322SIS: A System for Sequential Circuit) 381.2 509.67 P 317 654/G1006276 FmPA 1.25 (Analysis,) 338.15 499.67 P 1.25 (\323) 371.27 499.67 P 3 F 1.25 (T) 378.76 499.67 P 1.25 (ec) 382.93 499.67 P 1.25 (h. Report No. UCB/ERL M92/41) 390.79 499.67 P 1 F 1.25 (, Uni) 513.28 499.67 P 1.25 (v) 532.3 499.67 P 1.25 (ersity) 536.67 499.67 P (of California, Berk) 338.15 489.67 T (ele) 406.3 489.67 T (y) 416.65 489.67 T (, 1992.) 420.57 489.67 T ([26]) 316.55 476.67 T 0.89 (J. Cong and Y) 338.15 476.67 P 0.89 (. Ding, \322Flo) 391.17 476.67 P 0.89 (wMap: An Optimal T) 435.73 476.67 P 0.89 (echnology) 519.17 476.67 P 317 621/G1006281 FmPA 2.92 (Mapping Algorithm for Delay Optimization in Lookup-) 338.15 466.67 P 1.94 (T) 338.15 456.67 P 1.94 (able Based FPGA Designs,) 342.93 456.67 P 1.94 (\323) 446.11 456.67 P 3 F 1.94 (IEEE T) 454.29 456.67 P 1.94 (r) 482.48 456.67 P 1.94 (ans. on CAD) 485.85 456.67 P 1 F 1.94 (, Jan.) 535.98 456.67 P (1994, pp. 1 - 12.) 338.15 446.67 T ([27]) 316.55 433.67 T 3.27 (V) 338.15 433.67 P 3.27 (. Betz and J. Rose, \322Cluster) 343.48 433.67 P 3.27 (-Based Logic Blocks for) 458.63 433.67 P 317 578/G1006290 FmPA 0.29 (FPGAs: Area-Ef) 338.15 423.67 P 0.29 (\336cienc) 398.45 423.67 P 0.29 (y vs. Input Sharing and Size,) 422.31 423.67 P 0.29 (\323) 526.87 423.67 P 3 F 0.29 (CICC) 533.41 423.67 P 1 F 0.29 (,) 554.42 423.67 P (1997, pp. 551 - 554.) 338.15 413.67 T ([28]) 316.55 400.67 T 0.17 (V) 338.15 400.67 P 0.17 (. Betz and J. Rose, \322VPR: A Ne) 343.48 400.67 P 0.17 (w P) 461.32 400.67 P 0.17 (acking, Placement and) 475.1 400.67 P 317 545/G1006295 FmPA 0.58 (Routing T) 338.15 390.67 P 0.58 (ool for FPGA Research,) 374.76 390.67 P 0.58 (\323) 462.85 390.67 P 3 F 0.58 (Int. W) 469.67 390.67 P 0.58 (orkshop on F) 491.42 390.67 P 0.58 (ield-) 540.17 390.67 P (Pr) 338.15 380.67 T (o) 346.74 380.67 T (gr) 351.15 380.67 T (ammable Lo) 359.02 380.67 T (gic and Applications) 403.68 380.67 T 1 F (, 1997, pp. 213 - 222.) 478.18 380.67 T ([29]) 316.55 367.67 T 2.64 (C. Ebeling, L. McMurchie, S. A. Hauck and S. Burns,) 338.15 367.67 P 317 512/G1006370 FmPA 2.67 (\322Placement and Routing T) 338.15 357.67 P 2.67 (ools for the T) 441.18 357.67 P 2.67 (riptych FPGA,) 497.63 357.67 P 2.67 (\323) 552.67 357.67 P 3 F (IEEE T) 338.15 347.67 T (r) 364.4 347.67 T (ans. on VLSI) 367.77 347.67 T 1 F (, Dec. 1995, pp. 473 - 482.) 414.02 347.67 T ([30]) 316.55 334.67 T -0.22 (W) 338.15 334.67 P -0.22 (. Elmore, \322The T) 345.82 334.67 P -0.22 (ransient Response of Damped Linear Net-) 406.07 334.67 P 317 479/G1006371 FmPA 3.12 (w) 338.15 324.67 P 3.12 (orks with P) 344.55 324.67 P 3.12 (articular Re) 391.65 324.67 P 3.12 (g) 436.87 324.67 P 3.12 (ard to W) 441.33 324.67 P 3.12 (ideband Ampli\336ers,) 478.69 324.67 P 3.12 (\323) 552.67 324.67 P (J) 338.15 314.67 T 3 F (ournal of Applied Physics) 341.42 314.67 T 1 F (, Jan. 1948, pp. 55 - 63.) 434.67 314.67 T ([31]) 316.55 301.67 T 1.25 (S. T) 338.15 301.67 P 1.25 (rimber) 354.09 301.67 P 1.25 (ger) 377.92 301.67 P 1.25 (, Ed.,) 389.05 301.67 P 3 F 1.25 (F) 412.81 301.67 P 1.25 (ield-Pr) 417.9 301.67 P 1.25 (o) 443 301.67 P 1.25 (gr) 447.41 301.67 P 1.25 (ammable Gate Arr) 455.27 301.67 P 1.25 (ay T) 525.14 301.67 P 1.25 (ec) 541.31 301.67 P 1.25 (h-) 549.17 301.67 P 317 446/G1008995 FmPA (nolo) 338.15 291.67 T (gy) 354.06 291.67 T 1 F (, Kluwer Academic Publishers, 1994.) 361.97 291.67 T ([32]) 316.55 278.67 T 0.43 (R. Hitchcock, G. Smith and D. Cheng, \322T) 338.15 278.67 P 0.43 (iming Analysis of) 491.31 278.67 P 317 423/G1006456 FmPA 0.68 (Computer) 338.15 268.67 P 0.68 (-Hardw) 373.97 268.67 P 0.68 (are,) 401.36 268.67 P 0.68 (\323) 413.97 268.67 P 3 F 0.68 (IBM J) 420.89 268.67 P 0.68 (ournal of Resear) 443.58 268.67 P 0.68 (c) 505.1 268.67 P 0.68 (h and De) 508.96 268.67 P 0.68 (vel-) 543.18 268.67 P (opment) 338.15 258.67 T 1 F (, Jan. 1983, pp. 100 - 105.) 364.64 258.67 T ([33]) 316.55 245.67 T 2.84 (Xilinx Inc., \322XC4000E and XC4000X Series Field-Pro-) 338.15 245.67 P 317 390/G1006873 FmPA (grammable Gate Arrays,) 338.15 235.67 T (\323) 426.24 235.67 T 3 F (Data Sheet) 432.48 235.67 T 1 F (, 1997.) 472.23 235.67 T ([34]) 316.55 222.67 T 2.7 (P) 338.15 222.67 P 2.7 (. Clark) 342.15 222.67 P 2.7 (e, \322Dynachip Claims Speed Breakthrough in its) 369.26 222.67 P 317 367/G1006902 FmPA (FPGAs,) 338.15 212.67 T (\323) 366.27 212.67 T 3 F (Electr) 372.52 212.67 T (onic Engineering T) 394.11 212.67 T (imes) 463.11 212.67 T 1 F (, June 9, 1997, p. 10.) 479.61 212.67 T ([35]) 316.55 199.67 T 5.35 (J. Sw) 338.15 199.67 P 5.35 (artz, \322) 362.91 199.67 P 5.35 (A High-Speed T) 389.53 199.67 P 5.35 (iming-A) 459.4 199.67 P 5.35 (w) 489.08 199.67 P 5.35 (are Router for) 495.48 199.67 P 317 344/G1007480 FmPA (FPGAs,) 338.15 189.67 T (\323) 366.27 189.67 T 3 F (M.A.Sc. Thesis,) 372.52 189.67 T 1 F (Uni) 430.51 189.67 T (v) 443.79 189.67 T (ersity of T) 448.15 189.67 T (oronto, 1998.) 484.93 189.67 T 0 0 0 1 0 0 0 K [/CropBox[0 0 FmDC 612 792 FmDC FmBx]/PAGE FmPD [/Dest/P.10/DEST FmPD2 338 429/M9.18308.Reference.28.R.Hitchcock.G.Smith.and.D.Cheng.Timing.Analysis.of.ComputerHardware.IBM FmPA 338 429/I1.1006459 FmPA 338 396/M9.18606.Reference.29.Xilinx.Inc.XC4000E.and.XC4000X.Series.FieldProgrammable.Gate.Arrays.Data FmPA 338 396/I1.1006884 FmPA 338 373/M9.10834.Reference.30.P.Clarke.Dynachip.Claims.Speed.Breakthrough.in.its.FPGAs.Electronic.Engineerin FmPA 338 373/I1.1006909 FmPA 338 350/M9.16129.Reference.31.J.Swartz.A.HighSpeed.TimingAware.Router.for.FPGAs.MASc.Thesis.University.of FmPA 338 350/I1.1007483 FmPA 338 693/M9.18313.Reference.22.S.Yang.Logic.Synthesis.and.Optimization.Benchmarks.Version.30.Tech.Report FmPA 338 693/I1.1007728 FmPA 74 676/M9.12343.Reference.5.Vantis.Corporation.VF1.Field.Programmable.Gate.Array.Preliminary.Data.Sheet.199 FmPA 74 676/I1.1007766 FmPA 338 452/M9.30421.Reference.30.S.Trimberger.Ed.FieldProgrammable.Gate.Array.Technology.Kluwer.Academic.Publis FmPA 338 452/I1.1009009 FmPA 74 620/M9.29926.Reference.7.V.Betz.J.Rose.and.A.Marquardt.Architecture.and.CAD.for FmPA 74 620/I1.1010718 FmPA 74 768/M9.34205.Reference.1.S.Brown.R.Francis.J.Rose.and.Z.Vranesic.FieldProgrammable.Gate.Arrays.Kluwer FmPA 74 768/I1.1005580 FmPA 74 702/M9.17723.Reference.2.Xilinx.Inc.The.Programmable.Logic.Data.Book.1994 FmPA 74 702/I1.1005616 FmPA 74 689/M9.38790.Reference.3.Lucent.Technologies.FPGA.Data.Book.1998 FmPA 74 689/I1.1005620 FmPA 74 735/M9.26086.Reference.2.J.Rose.and.D.Hill.Architectural.and.Physical.Design.Challenges.for.OneMillion.G FmPA 74 735/I1.1005885 FmPA 74 653/M9.32183.Reference.5.V.Betz.Architecture.and.CAD.for.Speed.and.Area.Optimization.of.FPGAs.PhD.Dis FmPA 74 653/I1.1005904 FmPA 74 587/M9.26398.Reference.6.J.Rose.and.S.Brown.Flexibility.of.Interconnection.Structures.for.FieldProgramma FmPA 74 587/I1.1005908 FmPA 74 554/M9.32675.Reference.7.B.Tseng.J.Rose.and.S.Brown.Using.Architectural.and.CAD.Interactions.to.Improve FmPA 74 554/I1.1005912 FmPA 74 521/M9.39923.Reference.8.Y.Chang.D.F.Wong.and.C.K.Wong.Universal.Switch.Modules.for.FPGA.Design FmPA 74 521/I1.1005916 FmPA 74 488/M9.42645.Reference.9.S.Wilton.Architectures.and.Algorithms.for.FieldProgrammable.Gate.Arrays.with FmPA 74 488/I1.1005920 FmPA 74 435/M9.24113.Reference.10.J.Greene.V.Roychowdhury.S.Kaptanoglu.and.A.El.Gamal.Segmented.Channel.Rout FmPA 74 435/I1.1005932 FmPA 74 402/M9.15776.Reference.11.K.Roy.and.M.Mehendale.Optimization.of.Channel.Segmentation.for.Channelled.Arch FmPA 74 402/I1.1005936 FmPA 74 369/M9.33687.Reference.12.K.Zhu.and.D.F.Wong.On.Channel.Segmentation.for.RowBased.FPGAs.ICCAD FmPA 74 369/I1.1005940 FmPA 74 346/M9.15781.Reference.13.M.Pedram.B.Nobandegani.and.B.Preas.Design.and.Analysis.of.Segmented.Routing FmPA 74 346/I1.1005944 FmPA 74 313/M9.30544.Reference.14.S.Brown.M.Khellah.and.G.Lemieux.Segmented.Routing.for.SpeedPerformance.and FmPA 74 313/I1.1005958 FmPA 74 270/M9.12073.Reference.15.S.Brown.M.Khellah.and.Z.Vranesic.Minimizing.FPGA.Interconnect.Delays.IEEE FmPA 74 270/I1.1005962 FmPA 74 237/M9.31529.Reference.16.P.Chow.S.Seo.J.Rose.K.Chung.G.Paez.and.I.Rahardja.The.Design.of.an.SRAM FmPA 74 237/I1.1005966 FmPA 338 838/M9.34683.Reference.17.V.Betz.and.J.Rose.How.Much.Logic.Should.Go.in.an.FPGA.Logic.Block.IEEE.Design. FmPA 338 838/I1.1006029 FmPA 338 805/M9.11528.Reference.18.V.Betz.and.J.Rose.Effect.of.the.Prefabricated.Routing.Track.Distribution.on.FP FmPA 338 805/I1.1006048 FmPA 338 772/M9.36814.Reference.19.Altera.Inc.Data.Book.1998 FmPA 338 772/I1.1006059 FmPA 338 759/M9.39074.Reference.20.H.Hseih.et.al.ThirdGeneration.Architecture.Boosts.Speed.and.Density.of.FieldPr FmPA 338 759/I1.1006078 FmPA 338 726/M9.16114.Reference.21.Canadian.Microelectronics.Corporation.035.mm.MixedMode.Polycide.HSPICE.Mod FmPA 338 726/I1.1006144 FmPA 338 660/M9.39337.Reference.22.E.M.Sentovich.et.al.SIS.A.System.for.Sequential.Circuit.Analysis.Tech.Report.N FmPA 338 660/I1.1006305 FmPA 338 627/M9.10977.Reference.23.J.Cong.and.Y.Ding.FlowMap.An.Optimal.Technology.Mapping.Algorithm.for.Delay FmPA 338 627/I1.1006306 FmPA 338 584/M9.38864.Reference.24.V.Betz.and.J.Rose.ClusterBased.Logic.Blocks.for.FPGAs.AreaEfficiency.vs.Input FmPA 338 584/I1.1006309 FmPA 338 551/M9.15909.Reference.25.V.Betz.and.J.Rose.VPR.A.New.Packing.Placement.and.Routing.Tool.for.FPGA FmPA 338 551/I1.1006315 FmPA 338 518/M9.24141.Reference.26.C.Ebeling.L.McMurchie.S.A.Hauck.and.S.Burns.Placement.and.Routing.Tools.for FmPA 338 518/I1.1006375 FmPA 338 485/M9.35384.Reference.27.W.Elmore.The.Transient.Response.of.Damped.Linear.Networks.with.Particular.Rega FmPA 338 485/I1.1006390 FmPA [/Title(A)/Rect[44 63 566 726]/ARTICLE FmPD2 [/Page 1/View[/XYZ null 71 556 FmDC exch pop null]/Title(1 Introduction)/OUT FmPD [/Page 2/View[/XYZ null 72 324 FmDC exch pop null]/Title(2 FPGA Architecture and Circuit Design Parameters ...)/OUT FmPD [/Page 3/View[/XYZ null 72 462 FmDC exch pop null]/Title(3 Experimental Methodology)/Count 3/OUT FmPD [/Page 3/View[/XYZ null 76 353 FmDC exch pop null]/Title(3.1 CAD Flow)/Count 1/OUT FmPD [/Page 3/View[/XYZ null 340 491 FmDC exch pop null]/Title(3.1.1 Overview of Timing-Driven Routing Algorithm)/OUT FmPD [/Page 4/View[/XYZ null 76 699 FmDC exch pop null]/Title(3.2 Delay Model)/OUT FmPD [/Page 4/View[/XYZ null 76 355 FmDC exch pop null]/Title(3.3 Area Model)/OUT FmPD [/Page 4/View[/XYZ null 336 292 FmDC exch pop null]/Title(4 Experimental Results: Single Wire Segment Length...)/Count 1/OUT FmPD [/Page 5/View[/XYZ null 338 631 FmDC exch pop null]/Title(4.1 Area Model Revisited)/OUT FmPD [/Page 6/View[/XYZ null 72 864 FmDC exch pop null]/Title(5 Experimental Results: Two Types of Wire Segment ...)/Count 3/OUT FmPD [/Page 6/View[/XYZ null 76 771 FmDC exch pop null]/Title(5.1 Tri-State Buffer Routing Switches Only)/OUT FmPD [/Page 6/View[/XYZ null 339 864 FmDC exch pop null]/Title(5.2 Length 4 Buffered Wires Plus Pass- Transistor-...)/OUT FmPD [/Page 7/View[/XYZ null 339 475 FmDC exch pop null]/Title(5.3 Length 8 Buffered Wires Plus Pass- Transistor-...)/OUT FmPD [/Page 7/View[/XYZ null 336 283 FmDC exch pop null]/Title(6 Overall Architecture Comparison)/OUT FmPD [/Page 9/View[/XYZ null 336 722 FmDC exch pop null]/Title(7 Summary)/OUT FmPD [/Page 9/View[/XYZ null 391 272 FmDC exch pop null]/Title(Acknowledgments)/OUT FmPD [/Page 10/View[/XYZ null 145 785 FmDC exch pop null]/Title(References)/OUT FmPD FMENDPAGE %%EndPage: "10" 10 %%Trailer %%BoundingBox: 0 0 612 792 %%PageOrder: Ascend %%Pages: 10 %%DocumentFonts: Helvetica-Bold %%+ Times-Roman %%+ Times-Bold %%+ Times-Italic %%+ Symbol %%+ ZapfDingbats %%EOF