One way to reduce the delay and area of FPGAs is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnections. In this paper we empirically evaluate FPGA architectures with logic clusters ranging in size from 1 to 20, and show that compared to architectures with size 1 clusters, architectures with size 8 clusters have 23% less delay (30% faster clock speed), and require 14% less area. We also show that FPGA architectures with large cluster sizes can significantly reduce design compile time -- an increasingly important concern as the logic capacity of FPGAs rises. For example, an architecture that uses size 20 clusters requires 7 times less compile time than an architecture with size 1 clusters.