Publications

Patents

Books and Book Chapters

	Architecture and CAD for Deep-Submicron FPGAs, V. Betz, J. Rose, and A. Marquardt, Kluwer Academic Publishers, February 1999. 264 pages. ISBN 0-7923-8460-1 Book description (from the back cover). Amazon review
	V. Betz, "Placement for General Purpose FPGAs," Chapter 14, in Reconfigurable Computing, A. DeHon and S. Hauck, Eds., Morgan Kauffman, 2007.
	M. Hutton and V. Betz, "FPGA Synthesis and Physical Design," Volume 1, Chapter 13, in Electronic Design Automation for Integrated Circuits Handbook, L. Scheffer, L. Lavagno, and G. Martin, Eds., Taylor and Francis CRC Press, 2006, pp. 13-1 to 13-32.

Conference Keynotes

• "FPGAs at 28 nm: Meeting the Challenge of Modern Systems-on-a-Chip," IEEE International Conference on Field Programmable Logic and Applications, Milan, Italy, 2010. [Abstract] [PDF]

• "FPGA Challenges and Opportunities at 40 nm and Beyond,". IEEE International Conference on Field Programmable Logic and Applications, Prague, Czech Republic, 2009. [Abstract] [PDF]

Conference Panel & Workshop Presentations

• "FPGAs in 2032: Challenges and Opportunities for the Next 20 Years," ACM/SIGDA International Symposium on FPGAs,, Monterey, CA, 2012. Workshop co-chair. Slides and video.

• "Grand Challenges in FPGA Research," ACM/SIGDA International Symposium on FPGAs,, Monterey, CA, 2007. [PDF]

• "Will Power Kill FPGAs?," ACM/SIGDA International Symposium on FPGAs, Monterey, CA, 2006. [PDF]

Journal and Conference Papers and Articles:

• J. Cassidy, L. Lilge and V. Betz, "FullMonte: a Framework for High-Performance Monte Carlo Simulation of Light through Turbid Media with Complex Geometry, To appear in SPIE Photonics West, Feb. 2013.

• M. Abdelfattah and V. Betz, "Design Tradeoffs for Hard and Soft FPGA-based Networks-on-Chip," IEEE Int. Conf. on Field-Programmable Technology, 2012, pp. 95 - 103. [PDF]

• W. Zhang, V. Betz and J. Rose, "Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver," ACM Trans. on Reconfigurable Technology and Systems, March 2012, pp. 6:1 - 6:26. [PDF]

• V. Betz, "FPGAs, Programming Models and Kit Cars," The Last Byte article, IEEE Design and Test of Computers, July/August 2011, p. 112. [Computing Now Link] [PDF]

• A. Ludwin and V. Betz, "Efficient and Deterministic Parallel Placement for FPGAs," ACM Trans. on Design Automation of Electronic Systems, Vol. 16, No. 3, June 2011, pp. 22:1 - 22:23. [PDF]

• H. Wong, J. Rose and V. Betz, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture," ACM Int. Symp.on FPGAs, 2011, pp. 5 - 14. [PDF]

• S. Brown and V. Betz, "Recent FPGA Advances and Challenges," 10th Int. Conf. on Engineering of Reconfigurable Systems and Algorithms, 2010. [Abstract] [PDF]

• D. Chen, D. Singh, J. Chromczak, D. Lewis, R. Fung, D. Neto and V. Betz, "A Comprehensive Approach to Modeling, Characterizing and Optimizing for Metastability in FPGAs," ACM Int. Symp. on Field Programmable Gate Arrays, 2010, pp. 167 - 176. [Abstract] [PDF]

• W. Zhang, V. Betz and J. Rose, "Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver," IEEE Int. Conf. on Field-Programmable Technology, 2008, pp. 17 - 24. [Abstract] [PDF]

• R. Fung, V. Betz, and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations," IEEE Trans. on Computer-Aided Design of Circuits and Systems, April 2008, pp. 686 - 697. [Abstract] [PDF]

• A. Ludwin, V. Betz and K. Padalia, "High-Quality, Deterministic Parallel Placement for FPGAs on Commodity Hardware," ACM / Sigda Int. Symp. on FPGAs, 2008, pp. 14 - 23. [Abstract] [PDF]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• R. Tessier, V. Betz, D. Neto, A. Egier and T. Gopalsamy, "Power-efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks," IEEE Trans. on Computer-Aided Design of Circuits and Systems, Feb. 2007, pp. 278 - 290. [Abstract] [PDF]

• R. Tessier, V. Betz, D. Neto and T. Gopalsamy, "Power-Aware RAM Mapping for FPGA Embedded Memory Blocks," ACM/Sigda International Symposium on Field Programmable Gate Arrays, 2006, pp. 189 - 198. [Abstract] [PDF]

• D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff and J. Rose, "The Stratix II Logic and Routing Architecture," ACM/Sigda International Symposium on Field Programmable Gate Arrays, 2005, pp. 14 - 20. [Abstract] [PDF]

• R. Fung, V. Betz and W. Chow, "Simultaneous Short-Path and Long-Path Timing Optimization for FPGAs," IEEE International Conference on Computer-Aided Design, November 2004, 838 - 845. [Abstract] [PDF]

• D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, S. Marquardt, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff and J. Rose, ``The Stratix Routing and Logic Architecture,'' ACM/Sigda International Symposium on Field-Programmable Gate Arrays, February 2003, pp. 12 - 20. [Abstract] [PDF]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• A. Marquardt, V. Betz and J. Rose, ``Speed and Area Tradeoffs in Cluster-Based FPGA Architectures,'' IEEE Transactions on VLSI Systems, February 2000, pp. 84 - 93. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``Automatic Generation of FPGA Routing Architectures from High-Level Descriptions,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 175 - 184. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• A. Marquardt, V. Betz and J. Rose, ``Timing-Driven Placement for FPGAs,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 203 - 213. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• V. Betz and J. Rose, ``Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect,'' IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1999, pp. 171 - 174. [Abstract] [PDF] [Gzipped PostScript]

• V. Betz and J. Rose, ``FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density,''ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 59 - 68. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• A. Marquardt, V. Betz and J. Rose, ``Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 37 - 46. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• V. Betz and J. Rose, ``Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency,'' IEEE Transactions on VLSI Systems, September 1998, pp. 445 - 456. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``How Much Logic Should Go in an FPGA Logic Block?,'' IEEE Design and Test Magazine, Spring 1998, pp. 10 - 15. [Abstract] [PDF] [Gzipped Postscript]

• J. Swartz, V. Betz and J. Rose, ``A Fast Routability-Driven Router for FPGAs,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, 1998, pp. 140 - 149. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``VPR: A New Packing, Placement and Routing Tool for FPGA Research,'' Seventh International Workshop on Field-Programmable Logic and Applications, London, UK, 1997, pp. 213 - 222. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size,'' IEEE Custom Integrated Circuits Conference, Santa Clara, CA, 1997, pp. 551 - 554. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,'' IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 1996, pp. 652 - 659. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``Using Architectural Families to Increase FPGA Speed and Density,'' ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, 1995, pp. 10 - 16. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and R. Mittra, ``A Boundary Condition to Absorb Both Propagating and Evanescent Waves in a Finite-Difference Time-Domain Simulation,'' IEEE Microwave and Guided Wave Letters, June 1993, pp. 182 - 184.

• V. Betz and R. Mittra, ``Comparison and Evaluation of Boundary Conditions for the Absorption of Guided Waves in an FDTD Simulation,'' IEEE Microwave and Guided Wave Letters, Dec. 1992, pp. 499 - 501.

• V. Betz, N. P. East and A. Sebak, ``Applications of Planar Near-Field Measurements to Electromagnetic Radiation and Interference Problems,'' Canadian Conference on Electrical and Computer Engineering, Montreal, PQ, 1991, pp. 72.1.1 - 72.1.4.

Tutorials

• V. Betz and S. Verma, "Manage Performance and Power Using 40 nm FPGAs," Internet Seminar, July 2008. [PDF] [video]

• V. Betz and S. Rajput, "Learn to Design with Stratix III FPGAs Programmable Power Technology and Selectable Core Voltage," Internet Seminar, March 2007. [PDF] [video]

• V. Betz, "Using Stratix III FPGAs to Achieve Higher Performance Systems with Lower Power", Internet Seminar, Dec. 2006.

• V. Betz and S. Rajput, "Reduce FPGA Power With Automatic Optimization & Power-Efficient Design", Internet Seminar, Nov. 2005. [PDF]

• V. Betz and P. Ekas, "Power Solutions for Leading-Edge FPGAs", Internet Seminar, March 2005. [PDF]

Theses and Technical Reports:

• V. Betz and J. Rose, ``Architecture and CAD for the Speed and Area Optimization of FPGAs,'' Ph.D. Dissertation University of Toronto, 1998.

• V. Betz and J. Rose, ``On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs,'' CSRI Technical Report #358, Department of Electrical and Computer Engineering, University of Toronto, 1996. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and R. Mittra, ``Absorbing Boundary Conditions for the Finite-Difference Time-Domain Analysis of Guided-Wave Structures,'' M.S. Thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1993.

• V. Betz, N. P. East, and A. Sebak, ``Calculation of Far-Field Radiation Pattern from Near-Field Antenna Measurements,'' B.Sc. Thesis, Department of Electrical and Computer Engineering, University of Manitoba, 1991.