FPGA CAD Tools
- The latest version of VPR , a placement and routing tool for FPGA research, is available from as part of the VTR (Verilog to Routing) source archive.
- VPR and T-VPack version 4.30; this is the version used in Architecture and CAD for Deep-Submicron FPGAs.
New! COFFE: Circuit Optimization for FPGA Exploration. COFFE can automatically optimize low-level FPGA circuitry, and produce area and delay estimates that can be fed into VPR for architecture exploration. COFFE uses enhanced area and delay modeling vs. prior approaches, and VPR (post 7.0) has been upgraded to also use these enhanced models to be compatible with COFFE.
New! Hetris: Heterogeneous Floorplanning for FPGAs (coming soon).
FPGA Benchmarks, Architectures, and CAD flows
Other uses of and contests for FPGA CAD programs
VPR is part of the
suite of computer benchmarks
(the standard benchmarks used to determine the speed of various workstations).
I have found it to be a good predictor of the speed of commercial FPGA CAD tools on various computer hardware as well. Results are
The FPGA Place-and-Route Challenge: a contest for the FPGA community - compare your routing area against the best achieved so far
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