Current Graduate Students

Henry Wong, PhD
Research higher performance soft core processors for FPGAs, and build an x86 compatible soft core processor.

Mohamed Abdelfattah, PhD
Investigating how networks on a chip (NoCs) can best be integrated with FPGA logic to form a new hybrid device.

Jeff Cassidy, MASc
Developing a 3D simulation of photon absorption within arbitrary inhomogeneous material, for use in planning photodynamic cancer therapy. The computational requriements are high, so the simulator will then be hardware accelerated using FPGAs.

Charles Chiasson, MASc
Investigating novel electrical and architectural enhancements to FPGA interconnect in very advanced process technology.

Tim Liu, MASc
Investigating high-quality and scalable placement algorithms for very large circuits.

Kevin Murray, MASc
Investigating new physical CAD tools, including placement and floorplanning, to allow efficient latency-insensitive design of large systems.

Former Graduate Students

Wei Zhang
Developed a portable and scalable LU decomposition engine for FPGAs; this design easily adapts to and benefits from larger and faster FPGAs in the future.
Now a design engineer at Maxeler, London, UK, working on FPGA-based compute acceleration.

Former Undergraduate Student Researchers

Scott Whitty, BASc, summer researcher
Develop a CAD flow to allow large benchmark circuits to be analyzed and synthesized to basic components by an industrial tool flow, and then translate these intermediate results into circuits suitable for academic research flows.

Suya Liu, BASc, summer researcher
Worked to enable large and realistic benchmark designs to pass into academic flows, so academics can work on state-of-the-art problems. This involved three parts: modeling the Stratix IV architecture within VPR, obtaining large benchmark circuits, and upgrading the vqm2blif CAD flow that converts these circuits to an academic format.

Thien Yu, BASc, summer researcher
Upgraded VPR's placement engine to be more efficient by using "incremental" update techniques. Added support for carry chains to VPR, starting with a flexible description of these chains, through to upgrading the placement engine to respect the constraints imposed by such chains.

Michael Wainberg, BASc, summer researcher
Added multi-clock timing analysis to VPR, which is crucial in today's large, complex circuits. Investigated how best to optimize circuits with multiple timing constraints, and upgraded all optimization in VPR to be multi-clock aware.

Undergraduate Design Projects

Ke Deng, Saiquan Zhang, and Zimo Li
Develop a high-definition video-effects engine on an FPGA.

Kiril Pashin and Hoi-Ki Tong
Investigate FPGA routing algorithms to improve performance, and resolve hold time violations.

Jack Wu, Qian Sun, and Shi Zhang
Develop a voice controlled browser that reads out web pages for an Android phone.

Brian Pelingon and Venneti Prasanna
Develop a cell-phone based client server system to find and record available parking.

Former Undergraduate Design Projects

Ehsan Nasiri, Rafat Rashid and Saurabh Verma
Develop an LU decomposition engine in OpenCL, and port it to GPUs, multi-core CPUs and FPGAs. Compare performance, and evalute how significant the code changes are to achieve high performance on each platform (performance portability).

Fredrich Ombico and Hani Abdo
Develop a multiplayer online game on Android mobile devices.

Canna Wen, Rafal Dittwald and Clifford Lau
Develop an online version of the Diplomacy multiplayer strategy game to be played on mobile devices.

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