Jeff Cassidy, PhD
Developing a 3D simulation of photon absorption within arbitrary inhomogeneous material, for use in planning photodynamic cancer therapy. The computational requriements are high, so the simulator will then be hardware accelerated using FPGAs.
Kevin Murray, PhD
Investigating new physical CAD tools, including placement and floorplanning, to allow efficient latency-insensitive design of large systems.
Matthew An, MASc
Researching new parallel placement algorithms, and investigating how the transactional memory parallel processing paradigm can be applied to FPGA CAD.
Ibrahim Ahmed, PhD
Developing a robust dynamic voltage scaling system for FPGAs to save power.
Sadegh Yazdanshenas, PhD
Novel circuits (MTJ, BRAM) for FPGAs and efficient shells for datacenter FPGAs.
Lawrence Park, MASc
Safe context switching for FPGAs, particularly for datacenter applications.
Abed Yassine, PhD
Automatic optimization of patient-specific treatment plans for photodynamic therapy (light-activated chemotherapy to treat cancer).
Yasmin Afsharnezhad, MASc
Hardware acceleration of biophotonic calculations, to enable efficient treatment planning for photodynamic therapy.
Andrew Boutros, MASc
More efficient FPGA architectures.
Mustafa Abbas, MASc
Improved CAD tools for FPGAs.
Andrew Bitar, MASc
Researched new applications for FPGAs with embedded hard NoCs, and a CAD system for such FPGAs. Now at Intel Corporation's Programmable Solutions Group.
Oleg Petelin, MASc
Investigating new switch fabrics and switch evaluation tools for FPGAs.
Ehsan Nasiri, MEng
Evaluated new switch fabrics for interposer-based FPGAs. Now at Google, Waterloo.
Javeed Shaikh, MEng
Investigated "partition-then-place" CAD flows for interposer-based FPGAs. Now at Google, Mountain View, CA.
Rafat Rashid, MASc
Developed the hardware and compiler for an efficient FPGA overlay based on an application customized multi-threaded VLIW processor. Achieves 40% to 80% of the efficiency of OpenCL-based HLS, with 100x reduced recompilation time. Now at Index Exchange.
Charles Chiasson, MASc
Investigated novel electrical and architectural enhancements to FPGA interconnect in very advanced process technology. Now at Intel's Programmable Solutions Group.
Tim Liu, MASc
Investigated high-quality and scalable placement algorithms for very large circuits.
, MASc Developed a portable and scalable LU decomposition engine for FPGAs; this design easily adapts to and benefits from larger and faster FPGAs in the future.
Now at Xilinx.
Ange Yaghi, BASc, summer researcher, 2013
Embedding NoCs in FPGAs: Modeling and Simulation
Longyu Wang, BASc, summer researcher, 2013
Visualizing FPGA architectures
Jerry She, BASc, summer researcher, 2013
Improving CAD timing optimization for designs with complex timing.
Suya Liu, BASc, summer researcher, 2012
Worked to enable large and realistic benchmark designs to pass into academic flows, so academics can work on state-of-the-art problems. This involved three parts: modeling the Stratix IV architecture within VPR, obtaining large benchmark circuits, and upgrading the vqm2blif CAD flow that converts these circuits to an academic format.
Thien Yu, BASc, summer researcher, 2012
Upgraded VPR's placement engine to be more efficient by using "incremental" update techniques. Added support for carry chains to VPR, starting with a flexible description of these chains, through to upgrading the placement engine to respect the constraints imposed by such chains.
Michael Wainberg, BASc, summer researcher, 2012
Added multi-clock timing analysis to VPR, which is crucial in today's large, complex circuits. Investigated how best to optimize circuits with multiple timing constraints, and upgraded all optimization in VPR to be multi-clock aware.
Scott Whitty, BASc, summer researcher, 2011
Develop a CAD flow to allow large benchmark circuits to be analyzed and synthesized to basic components by an industrial tool flow, and then translate these intermediate results into circuits suitable for academic research flows.
Mark Sutherland, Security at What Price: Investigating the Hardware Cost of Physical Layer Security in MIMO Systems, 2013 - 2014.
Naif Tarafdar and Jordan Zannier, 2013 - 2014
High-performance Monte Carlo photon simulations in OpenCL on CPUs, GPUs and FPGAs
Zohair Massoud and Bilal Afzar, 2013 - 2014
A Portable Piano Tutor on a Cell Phone
Ke Deng, Saiquan Zhang, and Zimo Li, 2012 - 2013
Develop a high-definition video-effects engine on an FPGA.
Kiril Pashin and Hoi-Ki Tong , 2012 - 2013
Investigate FPGA routing algorithms to improve performance, and resolve hold time violations.
Jack Wu, Qian Sun, and Shi Zhang , 2012 - 2013
Develop a voice controlled browser that reads out web pages for an Android phone.
Brian Pelingon and Venneti Prasanna , 2012 - 2013
Develop a cell-phone based client server system to find and record available parking.
Ehsan Nasiri, Rafat Rashid and Saurabh Verma, 2011 - 2012
Develop an LU decomposition engine in OpenCL, and port it to GPUs, multi-core CPUs and FPGAs. Compare performance, and evalute how significant the code changes are to achieve high performance on each platform (performance portability).
Fredrich Ombico and Hani Abdo, 2011 - 2012
Develop a multiplayer online game on Android mobile devices.
Canna Wen, Rafal Dittwald and Clifford Lau
Develop an online version of the Diplomacy multiplayer strategy game to be played on mobile devices.