Student duties involve the theoretical study of the problem and the development of a CAD tool. If you like topics such as VLSI design (logic synthesis, testing), algorithms and programming, then there is good confidence you will like this work. It is common for our students to intern at leading industrial facilities. If you are already admitted to UofT and you are interested, email for an appointment. Otherwise, you first need to apply for admission to our graduate program.

We kindly acknowledge the contribution of various Canadian and Provincials agencies ( NSERC, CFI, CITO, Micronet ) as well as our domestic and international industrial partners (Motorola/Freescale-Austin, Motorola/Freescale-Markham , Intel Corporation-Portland, ATI, Infineon Technologies - Munich, Altera-San Jose ) that aid materialize our work. We are also thankful to all our graduate and undergraduate students (past and present) for their contributions, dedication and ethics.

Design Error and Fault Diagnosis

With the increase in the complexity of digital VLSI circuits, multiple design errors or/and manufacture defects can occur in a gate-level implementation or in a manufactured chip. In addition, due to recent advances in boolean satisfiability solvers, they have become a popular in VLSI CAD applications. The focus of this work is to develop efficient techniques for multiple fault/design error diagnosis using boolean satifiability solvers, as well as to optimize the satisfiability solver for this specific application. We intend to use this work for fault diagnosis of different physical faults such as bridges, stuck-at faults and opens. We are also interested in more traditional design error and dault diagnosis thechniques as well as automatic fault repair techniques of memory structures. 

Functional verification is a hard problem with crucial time-to-market and financial consequences. It has been reported that the VLSI engineer dedicates at least 50% of his/her time to perform various verification related tasks. In this work we develop diagnosis-based verification techniques for designs with a degree of structural similarity. We use various formal equivalence engines (BDDs, ATPG, SAT-solvers etc) and we intend to apply our techniques to build efficient logic-to-logic verification tools.

Logic optimization is the step of the VLSI design cycle where a netlist is modified to reduce area, power consumption, switching noise or to improve the testability of the final circuit. We are interested in techniques that perform a sequence of simple logic transformations (design rewiring) until the desired constraints (usually defined at the logic and physical level) are satisfied. We intend to apply these techniques in a variety of different optimization and synthesis problems such as routing, synthesis for testability, low-power and delay.

In a typical VLSI synthesis process specifications may change when the designer has already invested a significant amount of effort to get a design. Engineering changes to the original specification (RTL, HDL etc) may require large changes in the existing gate-level implementation if a conventional CAD tool is used. This is undesirable as it can jeopardize the engineering effort invested in the design. In this project we are interested for simulation/symbolic-based tools that can perform engineering changes efficiently.