University of Toronto ň Computer Engineering Research Group (EECG)

Selected Conference Papers

  1. B.Le, D.Sengupta and A.Veneris, ``Reviving Erroneous Stability-based Clock Gating using Partial Max-SAT,'', in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2013 (PDF)
  2. B.Keng and A.Veneris, ``Automated Debugging of Missing Input Constraints in a Formal Verification Environment,'' in Formal Methods in CAD (FMCAD), 2012 (PDF)
  3. B.Keng and A.Veneris, ``Path Directed Abstraction and Refinement in SAT-based Design Debugging,'' in IEEE/ACM Design Automation Conference (DAC), 2012 (PDF)
  4. D.Sengupta, F.M.de Paula, A.J.Hu, A.Veneris and A. Ivanov, ``Lazy Suspect-Set Computation: Fault Diagnosis for Deep Electrical Bugs,'' in IEEE Great Lakes VLSI Symposium, 2012 (PDF)
  5. B.Le, H.Mangassarian and A.Veneris, ``Non-Solution Implications using Reverse Domination in a Modern SAT-based Debugging Environent,'' in IEEE/ACM Design and Test in Europe (DATE) 2012, (PDF)
  6. Z.Poulos, Y-S Yang, J. Anderson and A.Veneris, ``Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug,'' in IEEE/ACM Design and Test in Europe (DATE) 2012, (PDF)
  7. B.Le, H.Mangassarian, B.Keng, and A.Veneris, ``Propelling SAT-based Debugging Using Reverse Domination,'' in IEEE Int'l Workshop on Constraints in Formal Verification, 2011 (PDF)
  8. H.Mangassarian, H.Yoshida, A.Veneris, S.Yamashita and M.Fujita, ``On Error Tolerance and Engineering Change with Partially Programmable Circuits,'' in IEEE/ACM Asian-South Pacific DAC 2012 (ASPDAC), (PDF)
  9. Y.S.Yang, A.Veneris, N.Nicolici and M.Fujita, ``Automated Data Analysis Techniques for a Modern Silicon Debug Environment,'' in IEEE/ACM Asian-South Pacific DAC 2012 (ASPDAC, invited paper), (PDF)
  10. B.Keng, D.E.Smith and A.Veneris, ``Efficient Debugging of Multiple Design Errors,'' in IEEE Microprocessor Test and Verification Workshop, 2011 (PDF)
  11. H.Mangassarian, A.Veneris, D.E.Smith, and S.Safarpour ``Debugging with Dominance: On-the-fly Debug Solution Implications,'' in IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), 2011 (PDF)
  12. D.Sengupta, A.Veneris, S.Wilton, A.Ivanov, R.Saleh, ``Sequence Pair Based Voltage Island Floorplanning,'' in IEEE International Green Computing Conference, 2011 (PDF)
  13. A.Veneris, B.Keng and S.Safarpour, ``From RTL to Silicon: The Case for Automated Debug,'' in IEEE/ACM Asian-South Pacific Design Automation Conference, 2011 (PDF) (invited paper)
  14. B.Keng, S.Safarpour and A.Veneris ``Automated Debugging of SystemVerilog Assertions,'' in IEEE/ACM Design and Test in Europe, 2011 (PDF)
  15. B.Keng and A.Veneris, ``Managing Complexity in Design Debugging with Sequential Abstraction and Refinement,'' in IEEE/ACM Asian-South Pacific Design Automation Conference, 2011 (PDF)
  16. Y.-S.Yang, B. Keng, A.Veneris, N. Nicolici and H. Mangassarian, ``Software Solutions to Automating Data Analysis and Acquisition Setup in Silicon Debug,'' in IEEE Silicon Debug and Diagnosis Workshop, 2010
  17. B.Keng, S.Safarpour and A.Veneris, ``An Automated Framework for Correction and Debug of PSL Assertions,'' in IEEE Microprocessor Verification and Test Workshop, 2010 (PDF)
  18. H. Mangassarian, B.Le, A.Goultiaeva, A.Veneris and F.Bacchus, ``Leveraging Dominators for Preprocessing QBF,'' in IEEE/ACM Design and Test in Europe (DATE), 2010 (PDF)
  19. Y.-S.Yang, B.Keng, N.Nicolici, A.Veneris and S.Safarpour, ``Automated Silicon Debug Data Analysis Techniques for a Hardware Data Acquisition Environment,'' in IEEE Int'l Symposium on Quality of Electronic Design, 2010.
  20. S.Safarpour, A.Veneris and F.Najm, ``Managing Verification Error Traces with Bounded Model Debugging,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2010 (PDF)
  21. S.Safarpour and A.Veneris, ``Automated Debugging with High Level Abstraction and Refinement,'' in IEEE High Level Design Validation and Test Workshop, 2009
  22. B.Keng and A.Veneris, ``Scaling VLSI Design Debugging with Interpolation,'' in Formal Methods in CAD (FMCAD), 2009 (PDF)
  23. Y.Chen, S.Safarpour and A.Veneris, ``Optimal Trace Compaction with Property Preservation,'' in IEEE Midwest Symposium on Circuits and Systems, 2009 (PDF)
  24. A.Veneris and S. Safarpour, ``The Day Sherlock Holmes Decided to do EDA,'' invited talk in IEEE/ACM Design Automation Conference (DAC), 2009 (PDF)
  25. E.Safi, A.Moshovos and A.Veneris, ``A Physical-Level Study of the Compacted Matrix Instruction Scheduler for Duynamically Scheduled Superscalar Processors,'' in IEEE Int'l Symposium on Systems, Architectures, Modeling and Simulation, (PDF)
  26. Y.Chen, S.Safarpour, A.Veneris and J.M.Silva, ``Spatial and Temporal Design Debug using Partial MaxSAT,'' in IEEE Great Lakes VLSI Symposium, 2009 (PDF)
  27. Y.S.Yang, S.Sinha, A.Veneris, R.K.Brayton and D.Smith, ``Sequential Logic Rectifications with Approximate SPFDs,'' in IEEE/ACM Design and Test in Europe (DATE), 2009 (PDF)
  28. Y.S.Yang, N.Nicolici, and A.Veneris ``Automated Data Analysis Solutions to Silicon Debug,'' in IEEE/ACM Design and Test in Europe (DATE), 2009 (PDF)
  29. B.Keng, H.Mangassarian and A.Veneris, ``A Succint Memory Model for Automated Design Debugging,'' in IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), 2008 (PDF)
  30. S.Almukhaizim, Y.Makris, Y.-S.Yang and A.Veneris, ``On the Minimization of Potential Transient Errors and SET in Logic Circuits using SPFD,'' in IEEE Int'l On Line Test Symposium, 2008 (PDF)
  31. S.Safarpour, M.Liffton, H.Mangassarian, A.Veneris and K.A.Sakallah, ``Improved Design Debugging Using Maximum Satisfiability,'' in Formal Methods in CAD (FMCAD) 2007, (PDF)
  32. H.Mangassarian, A.Veneris, S.Safarpour, M.Benedetti and D.Smith, ``A Performance-Driven QBF-Based Iterative Logic Array Representation with Applications to Verification, Debug and Test,'' in Int'l Conference on Computer-Aided Design (ICCAD), 2007, (PDF)
  33. E.Safi, P.Akl, A.Moshovos, A.Veneris and A.Arapoyianni, ``On the Latency, Energy and Area of Checkpointed, Supescalar Register Alias Tables,'' in IEEE Int'l Symposium on Low Power Electronic Devices, 2007 (PDF)
  34. H.Mangassarian, A.Veneris and M.Benedetti, ``Fault Diagnosis Using Quantified Boolean Formulas,'' in IEEE Silicon Debug and Diagnosis Workshop (SDD), Freiburg, May 2007, (PDF)
  35. H.Mangassarian, A.Veneris, S.Safarpour, F.N.Najm and M.S.Abadir, ``Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability,'' in IEEE/ACM Design and Test in Europe Conference (DATE), 2007 (PDF)
  36. S.Safarpour and A.Veneris, ``Abstraction and Refinement Techniques in Automated Design Debugging,'' in IEEE/ACM Design and Test in Europe Conference (DATE), 2007 (PDF)
  37. Y.-S.Yang, S.Sinha, A.Veneris and R.K.Brayton, ``Automating Logic Rectification by Approximate SPFDs,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2007 (PDF)
  38. S.Safarpour, A.Veneris and Hratch Mangassarian, ``Trace Compaction using SAT-based Reachability Analysis,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2007 (PDF)
  39. E.Safi, A.Moshovos and A.Veneris, ``L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture,'' in IEEE Int'l Symposium on Low Power Electronic Devices, 2006 (PDF)
  40. S.Almukhaizim, Y.Makris, Y.-S.Yang and A.Veneris, ``Seamless Integration of SER in Rewiring-Based Design Space Exploration,'' in IEEE Int'l Test Conference (ITC), 2006 (PDF)
  41. S.Safarpour, A.Veneris, G.Baeckler and R.Yuan, ``Efficient SAT-based Boolean Matching for FPGA Technology Mapping,'' in IEEE/ACM Design Automation Conference (DAC), 2006 (PDF)
  42. S.Safarpour, A.Veneris and R.Dreschler, ``Integrating Observability Don't Cares in All-Solution SAT Solvers,'' in IEEE Int'l Symposium on Circuits and Systems, 2006 (PDF)
  43. G.Fey, S.Safarpour, A.Veneris and R.Drechsler, ``On the Relation Between Simulation-based and SAT-based Diagnosis,'' in IEEE/ACM Design and Test in Europe (DATE) Conference, 2006 (PDF)
  44. M.F.Ali, S.Safarpour, A.Veneris, M.S.Abadir and R.Drechsler, ``Post-Verification Debugging of Hierarchical Designs,'' in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2005 (PDF)
  45. J.B.Liu, M.S.Abadir, A.Veneris and S.Safarpour,``Diagnosing Multiple Transition Faults in the Absense of Timing Information,'' in IEEE Great Lakes VLSI Symposium, 2005 (PDF)
  46. S.Safarpour, G.Fey, A.Veneris and R.Drechsler, ``Utilizing Don't Care States in SAT-based Bounded Sequential Problems,'' in IEEE Great Lakes VLSI Symposium, 2005 (PDF)
  47. Y-S.Yang, A.Veneris, P.Thadikaran and S.Venkataraman, ``Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs,'' in IEEE Design and Test in Europe, 2005 (PDF)
  48. M.Fahim Ali, A.Veneris, S.Safarpour, R.Drechsler, A.Smith and M.S.Abadir, ``Debugging Sequential Circuits Using Boolean Satisfiability,'' in IEEE Int'l Conference of Computer-Aided Design, 2004 (PDF) (PS)
  49. J.B.Liu, M.S.Abadir, R.Chang, A.Veneris, ``Monarch: A Platform for Logic Optimization using ATPG/Diagnosis-based Design Rewiring,'' in IEEE Latin-American Test Workshop 2004 (PDF) (PS)
  50. A.Veneris, R.Chang, M.S.Abadir and M.Amiri, ``Fault Equivalence and Diagnostic Test Generation Using ATPG,'' in IEEE Int'l Symposium on Circuits and Systems, 2004 (PDF)
  51. S.Safarpour, A.Veneris, R.Drechsler and J.Lee, ``Managing Don't Cares in Boolean Satisfiability,'' in IEEE Design Automation and Test in Europe (DATE) Conference, 2004 (PDF)
  52. A.Smith, A.Veneris and A.Viglas, ``Design Diagnosis Using Boolean Satisfiability,'' in IEEE Asian-South Pacific Design Automation Conference 2004 (PDF)
  53. Y.S.Yang, J.B.Liu, P.Thadikaran and A.Veneris, ``Extraction Error Diagnosis and Correction in High-Performance Designs,'' in IEEE International Test Conference 2003 (PDF)
  54. A.Veneris, ``Fault Diagnosis and Logic Debugging Using Boolean Satisfiability,'' in IEEE Microprocessor Test and Verification Workshop, 2003 (PDF)
  55. R.Chang, S.Seyedi, A.Veneris and M.S.Abadir, ``Exact Functional Fault Collapsing in Combinational Logic Circuits,'' in IEEE Latin American Test Workshop 2003, (PDF)
  56. A.Veneris, A.Smith and M.S.Abadir, ``Logic Verification based on Diagnosis Techniques,'' in IEEE Asian-South-Pacific (ASP) Design Automation Conference 2003, (PDF)
  57. J.B.Liu, A.Veneris and H.Takahashi, ``Incremental Diagnosis of Multiple Open Interconnects,'' in IEEE Int'l Test Conference 2002 (PDF)
  58. A.Veneris, M.Abadir and M.Amiri, ``Design Rewiring Using ATPG,'' in IEEE Int'l Test Conference 2002 (PDF)
  59. A.Veneris, M.Amiri and I.Ting, ``Design Rewiring for Power Minimization,'' in ISCAS 2002 (PS)
  60. B.Liu, A.Veneris and M.S.Abadir, ``Efficient and Exact Diagnosis of Multiple Stuck-at Faults,'' 3rd IEEE Latin-American Test Workshop 2002 (PS)
  61. A.Veneris, B.Liu, M.Amiri and M.S.Abadir, ``Incremental Diagnosis and Debugging of Multiple Faults and Errors,'' IEEE Design, Automation and Test in Europe (DATE) Conference, 2002 (PDF)
  62. I.Ting, A.Veneris, and M.S.Abadir, ``ATPG Driven Logic Synthesis for Area and Power Minimization'', 2nd IEEE Latin-American Test Workshop 2001 (postcript)
  63. A.Veneris, M.S.Abadir, and I.Ting, `` Design Rewiring based on Diagnosis Techniques'', IEEE Asian-South-Pacific (ASP) Design Automation Conference, pp 479-481, 2001. Recipient of ASP-DAC 2001's best paper award. (postcript)
  64. A.Veneris, M.S.Abadir, and I.N.Hajj, `` Design Optimization based on Diagnosis Techniques'', 1st IEEE Latin-American Test Workshop 2000 (postcript)
  65. A. Veneris, S. Venkataraman, I. N. Hajj, and W. K. Fuchs,``Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits'', in Proceedings of IEEE VLSI Test Symposium, pp. 58ˇ63, 1999. (posctript)
  66. A. Veneris and I. N. Hajj, ``A Hybrid Approach to Design Error Detection and Correction'', in Proceedings of International Conference on Electronics, Circuits and Systems, 1999. (postcript)
  67. A. Veneris and I. N. Hajj, ``Correcting Multiple Design Errors in Digital VLSI Circuits'', in Proceedings of IEEE International Symposium on Circuits and Systems, 1999. (postcript)
  68. A. Veneris and I. N. Hajj, ``A Fast Algorithm for Locating and Correcting Simple Design Errors'' in Proceedings of 7th IEEE Great Lakes Symposium on VLSI, pp. 45--50, 1997. (postcript)
  69. A. Veneris and I. N. Hajj, ``Error Diagnosis and Correction in VLSI Digital Circuits'', in Proceedings of IEEE Midwest Symposium on Circuits and Systems, pp. 1005--1008, 1997. (postcript)
  70. L. M. Kirousis and A. Veneris, ``Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations'', in 7th International Workshop of Distributed Algorithms, Lecture Notes in Computer Science 725, Springer-Verlag, pp. 54--68, 1993. (postcript)
  71. L. M. Kirousis, P. Tsigas and A. Veneris, ``An Atomicity Criterion for Composite Registers'', in Proceedings of IMACS/IFAC International Symposium on Parallel and Distributed Computing in Engineering Systems (NorthˇHolland), pp. 31ˇ34, 1991. (postcript)

Refereed Journal Papers

  1. H.Mangassarian, A.Veneris and F.N.Najm, ``Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability,'' in IEEE Trans. on TCAD (accepted) (PDF)
  2. Y.S.Yang, A.Veneris and N.Nicolici, ``Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment,'' in IEEE Trans. on VLSI (accepted) (PDF)
  3. Y.S.Yang, S.Sinha, A.Veneris and R.K.Brayton, ``Automating Logic Transformations with Approximate SPFDs,'' in IEEE Trans. on Computer-Aided Design (accepted) (PDF)
  4. E.Safi, A.Moshovos and A.Veneris, ``Two-stage Pipelined Register Renaming,'' in IEEE Trans. on VLSI (accepted July 2010) (PDF)
  5. B.Keng, S.Safarpour and A.Veneris, ``Bounded Model Debugging,'' in IEEE Trans. on CAD (accepted) (PDF)
  6. Y.Chen, S.Safarpour, J.M.Silva and A.Veneris, ``Automated Design Debugging with Maximum Satisfiability,'' in IEEE Trans. on CAD (accepted) (PDF)
  7. H.Mangassarian, A.Veneris and M.Benedetti, ``Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug and Test,'' in IEEE Trans. on Computers (accepted) (PDF)
  8. S.Safarpour and A.Veneris, ``Automated Design Debugging with Abstraction and Refinement,'' in IEEE Trans. on CAD, Oct. 2009 (PDF)
  9. E.Safi, A.Moshovos and A.Veneris, ``On the Latency and Energy of Checkpointed, Superscalar Register Alias Tables,'' in IEEE Trans. on VLSI (PDF)
  10. S.Safarpour, A.Veneris, and R.Drechsler, ``Improved SAT-based Reachability Analysis with Observability Don't Cares,'' in Journal on Satisfiability, Boolean Modeling and Computation, Volume 5 (2008), pages 1-25 (PDF)
  11. E.Safi, A.Moshovos and A.Veneris, ``L-CBF: A Low-Power Fast Counting Bloom Filter Architecture,'' in IEEE Trans. on VLSI (PDF)
  12. Y.-S.Yang, A.Veneris, P.Thadikaran and S.Venkataraman, ``Extraction Error Modeling and Automated Model Debugging in High-Performance Custom Designs,'' in IEEE Trans. on VLSI, July 2006 (PDF)
  13. A.Smith, A.Veneris, M.F.Ali and A.Viglas, ``Fault Diagnosis and Logic Debugging Using Boolean Satisfiability,'' in IEEE Transactions in Computer-Aided Design (PDF)
  14. J.B.Liu and A.Veneris, ``Incremental Fault Diagnosis,'' in IEEE Transactions in Computer-Aided Design (PDF)
  15. A.Veneris and J.B.Liu, ``Incremental Design Debugging in a Logic Synthesis Environment,'' in Springer-Verlag Journal of Electronic Testing: Theory and Applications, vo.21, no.5, pp.485-494, Oct 2005 (PDF)
  16. A.Veneris, ``Logic Rewiring for Delay and Power Minimization,'' in Journal of Information Science and Engineering (PDF)
  17. A.Veneris, R.Chang, M.S.Abadir and S.Seyedi, ``Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG,'' in Journal of Electronic Testing: Theory and Applications (Kluwer), vo.21, no.5, pp.495-502, Oct 2005 (PDF)
  18. A.Veneris and M.S.Abadir, ``Design Rewiring Using ATPG'', IEEE Transactions on Computer-Aided Design, vol. 21, no. 12, pp. 1469-1479, December 2002 (PDF)
  19. A. Veneris and I. N. Hajj, ``Design Error Diagnosis and Correction Via Test Vector Simulation'', in IEEE Transactions on ComputerˇAided Design, vol.18, no.12, pp.1803-1816, December 1999. (PDF)
  20. L. M. Kirousis and A. Veneris, ``Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations'', in Acta Informatica (Springer-Verlag) 32, pp. 155ˇ170, 1995. (postcript)

Books, Book Chapters and Patents

  1. Y.S.Yang, S.Sinha, A.Veneris and R.K.Brayton, ``Advanced Techniques in Logic Synthesis, Optimizations and Applications'' Springer 2010 (Ed: Sunil P. Khatri and Kanupriya Gulati) (PDF)
  2. S.Safarpour, D.Smith, A.Veneris and A.Baker, ``A Methodology for Automated Debugging with Quantified Satisfiability,'' US/Canadian Patent filed, November 2007
  3. A.Veneris, S.Safarpour, M.F.Ali and H.Mangassarian, ``Method, System and Computer Program for Automated Hardware Design Debugging,'' US/Canadian patent filed, October 2006.
  4. M.S.Abadir and A.Veneris, ``Method and system of data processor design by sensitizing logical difference,'' US Patent 7,003,743, Febr 21, 2006
  5. A. Veneris, and D. Kalles, ``Fortran 77'' (in Greek), Voulgaris Editions,1987 (1st ed.), 1989 (2nd ed.).

  University of Toronto ň Computer Engineering Research Group (EECG)