HDL Specifications

Device

Part	Logic	Block RAM
XC5VLX110	17,280 V5 slices	128 x 36Kb block RAM (4,608 Kb)
XC2VP30-6ff896	27,392 logic cells	136 x 18Kb block RAM (2,448 Kb)

35 [1]	34 [1]	33 [1]	32..23 [10]	22..15 [8]	14..5 [10]	4..0 [5]
Head?	Tail?	Measure?	Timestamp	Destination	Source/Injection	Ununsed

13..11 [3]	10 [1]	9..0 [10]
Port	VC	Timestamp

All resource utilizaton numbers shown here are post-synthesis and are based on the XC2VP30 device.

Name	Description	Slices	FF	Slice LUTs	BRAMs	Notes
muxNto1	4-bit 8-to-1	8	0	16		Encoded select
muxNto1_decoded	4-bit 8-to-1
decoder_N	8-to-1 one hot	4	0	8
encoder_N	8-to-1 one hot	2	0	3
LFSR3_9	6-element LFSR (full cycle)	3	6	2		Requires decoding (N-1) signals. Will not scale.
LFSR3_9	6-element LFSR (basic)	3	6	1
RAMFIFO_ctrl_lfsr	36 bit x 64 FIFO control	9	13	17		2 6-bit LFSRs(f) & simple logic.
RAMFIFO_ctrl_lfs_dc	36 bit x 64 FIFO control (2 cycle latency)	14	13	25
RAMFIFO_ctrl_counter	36 bit x 64 FIFO control	16	13	32		2 6-bit counters
RAMFIFO	36 bit x 64 x 8 contexts (18Kb) FIFO	289	417	526	1	Individual dout reg per context (necessary?)
		304	417	526	1	Post PAR. 5.993ns (167 MHz)
flit_out_inf	10-bit timestamp	6	0	11
srl_fifo	11 bit x 16 SRL FIFO	13	5	23
FQCtrl	State-less FQ bandwidth controller	75	34	72
		69	34	72		Post PAR. Fmax ~140MHz (6.769ns)
FlitQueue	FQ with 2 VCs	194	143	306	1	RAMFIFO (2 contexts), FQCtrl, 1 encoder, 3 flit_out_inf, 1 srl_fifo (14bitx32)
TGBernoulli	State-less version of Bernoulli injection process	36	20	69
TGBernoulliFSM	FSM version of Bernoulli injection process	33	22	62
		32	22	53		Post PAR. Fmax 200MHz (4.977ns)
RNG	32-bit taus88 RNG	74	96	129
TrafficGen	Single context TG (no FQ)	142	198	245		RNG, TGBernoulliFSM with config and stats

hdl.txt · Last modified: 2009/11/17 20:43 by danyao

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