Weekly Status

Next week:

Raised issue: How detailed should these be modeled in functional simulation?

Next week:

Next week:

Are cache coherence protocols a 'soft' layer on top of underlying interconnects?

Next week:

Find out more about packet-switched networks, especially in NoC applications

What are the tradeoffs in NoC system design?

Next week:

No meeting due to reading week

Natalie joined the meeting today

Most appropriate canonical router model seems to be a 5-stage VC router

Mesh and 2D torus are the most commonly used topologies

Next week:

Elias presented slides on chapter 16 (router architecture) from Dally

Next:

No meeting. Andreas was away.

Elias presented slides on chapter 17 (router datapath components) from Dally

Next:

Danyao presented an overview on the network simulator project [ PDF ]

Next:

Next:

NoCem: interconnect simulator on FPGA

Netmaker: synthesizable VC router

Next:

Got SimFlex running

No meeting (due to exams)

No meeting

Bochs project presentation

We want to simulate up to 256 nodes on a single chip

No meeting

Brainstormed on project details: The Plan

Playing with SimFlex to get aggregated bandwidth numbers between the processors and the interconnect

Simulator and SVN up

Added RouterIdeal class to model an unpipelined router (1 cycle routing delay).

We still need PQs to model the Router input buffers

To-Do

Unsuccessful attempt at implementing credits in PQs instead of Routers

Functional unpipelined mesh element with credits

To-do:

Implemented a mesh element with credits

Timestamp problem fixed (credit stalls and bandwidth limits are correctly accounted for)

How to properly warm up the network?

Next

On-chip network paper survey (see Research Survey)

Added dedicated credit channels in the FlitQueues so that credits can be potentially handled in a separate interconnect parallel to the flit network

Merged output buffers of the Router into a single one and added a dedicated credit channel. This avoids credit flits with earlier timestamps be blocked by data flits with later timestamps.

Implemented time-multiplexed Router that emulates simultaneous switching of multiple ports by switching one port each clock cycle

Removed credits between the local node and the router (assuming the local node can always consume incoming flits)

Next

Separated the output interfaces for credits and flits at the Routers. Performance improved from 5.9 clks/ts to 3.47 clks/ts (Rev. 45)

Added wormhole routing to RouterMesh (Rev. 52)

Added VC support in FlitQueue and RouterMesh (Rev. 55, see Flit Queue for a description)

Make simulator model register stages and RAM latencies that will be in the hardware model

Working on Verilog modules to estimate hardware utilization

1 RouterMesh = 1 Router + 5 FlitQueues ~= 1830 LUTs + 1921 FFs + 16 Kb blockRAMs

Small FIFO implementation

Scripts to run sweeps on simulator parameters

Sweep on Interconnect and Router models over various traffic load: interconnect

Investigating performance bottlenecks

On vacation this week

Bubble-avoidance in ideal IC/mesh-ideal router brings sim steps/clock to 1.

Bubbles in dual-crossbar and regular mesh Router are caused by the Router::can_increment() function. By allowing a Router to increment if only 1 available port is uninspected, sim steps/clock is improved from 0.31 to 0.44 at 50% load and from 0.23 to 0.31 at 100% load.

The Router with the most ready ports in a given time step determines the least number of clock cycles required to simulate this step. The average for this metric in our simulation is about 2.9 over 100 steps, which is consistent with the measured values of sim steps/clock.

Partitioned Crossbar: the grouping of FQs/TGs into destination partitions in the 16-node torus benchmark reduces simulator performance by 2.5x (2x from grouping 2 RTs per source partition, and probably some inefficiencies in crossbar allocation)

Added 16-node mesh network benchmark. Need more.

Changed input port arbitration scheme from rotating priority (based on CLK) to static priority because the iport.inspected flag prevents head-of-line blocking, which the rotating priority scheme was introduced to address. The static priority results in deterministic results irrespective of the global interconnect model used.

Project positioning

Writing an abstract and a summary of related work

Trying to run SICOSYS and booksim and use them as a baseline for correctness and software simulator performance

Next:

booksim vs. sim:

writing/introduction

Need to process flits in their arrival order (so a flit stalled from the previous cycle should get priority over new flits that just arrived)

Model the fact that body/tail flits by-pass the routing stage. No effect now because routing delay is 1 for both head and other flits

Latency discrepancy

Verify:

Implemented RAMFIFO. Compared LFSR based and counter based implementation. In ISE, LFSR-based is 50% cheaper for 36 bit x 64 deep FIFO based on block RAM (6-bit head/tail pointers)

Trying to get Timing Analyzer to work (need to update Debian to get libmotif3)

Read a few papers on on-chip network and trace-based simulation (see realistic_traffic)

Let TG injection lag behind global clock if output queue is full. This approach is used in booksim. No performance hit. (Rev. 124)

Working on verilog (see hdl for progress)

Weird problem: FF counter decreases significantly after MAP (something must be wrong… @@). Only occurs for V2P, not V5.

TGBernoulliFSM/TGBernoulli, FQCtrl module (hdl)

RAMFIFO: 2-cycle dequeue latency when switching contexts

FlitQueue. TrafficGen.

Working on FlitQueue testbench