Danyao's Wall Notes

Summary of the network-related files in Flexus:

• components/Nic/NicXImpl.hpp
• components/Common/Transports/NetworkTransport.hpp
• components/Common/Slices/NetworkMessage.hpp
  • src, dest, vc, size, src_port, dst_port
• components/ProtocolEngine/he_exec_engine.hpp/cpp
  • Home engine (in ProtocolEngine), translates memory transport to network transport
• components/ProtocolEngine/ServiceFlexus.hpp
  • translateMemoryTransport (trans): create a tPacket (protocol packet) from a memory transport
  • send (…): creates the protocol packet and NetworkMessage for the requested
  • NetworkMessage payload size: 64 or 0 bytes
• components/NetShim: interconnection network
  • Translates NetworkMessage to MessageStage (network packet) upon receiving the network message
  • allocMessageState ()
  • transmit latency = transport[NetworkMessageTag]→size: i.e. flit size = 1 byte (when flexusInFastMode; this is the default setting)
  • If not in fast mode (netcontainer.cpp): latency = channelLatencyData (32) or channelLatencyControl (1)
  • Actual channel busy time = transmit latency / localLatencyDivider (8)
    • i.e. data packet occupies the channel for 4 cycles, control packets 1
• components/NetShim/netcommon.hpp: defines MessageState

• Realizable ethernet throughput:
  • http://www.codinghorror.com/blog/archives/000339.html

• Working on simulator
  • Using SimFlex topology configuration file (specifies connectivity (from node/port → to node/port)
  • Assuming infinite switching bandwidth for now

• navigation

Paper survey stuff moved to the Research Survey section.

• NUCA Non-uniform cache architecture
• If a link has multi-cycle latency (say N), does that mean we can only send one flit every N cycles? (probably not. The link acts as a pipeline)

Things to try:

• crossbar resource utilization (variable sizes and data widths)
• router arbitration resource util. (Schelle claims this is one of the major reasons why VC routers are not suitable for FPGAs)
• time-decompose the crossbar into multi-cycle arbitrations (done)
• allow TGs to drift behind to minimize injection queue size (see booksim) (done)
• compact flits at FQ (since flits arrive in streams)

• The Processor Memory bottleneck: http://www.acm.org/crossroads/xrds5-3/pmgap.html
• FPGA-Optim http://www.conekt.net/fpgaoptim.html: A tool to analyze Xilinx Map NCD files and show a resource utilization breakdown