http://www.eecg.toronto.edu/~wangda/fame/wiki/ 2010-03-15T00:47:41-04:00 http://www.eecg.toronto.edu/~wangda/fame/wiki/ http://www.eecg.toronto.edu/~wangda/fame/wiki/lib/images/favicon.ico text/html 2010-03-11T17:21:45-04:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=hdl&rev=1268346105&do=diff Device Part Logic Block RAM XC5VLX110 17,280 V5 slices 128 x 36Kb block RAM (4,608 Kb) XC2VP30-6ff896 27,392 logic cells 136 x 18Kb block RAM (2,448 Kb) * V5 slice = 4 LUTs + 4 FFs * logic cell ~= 1 LUT + 1 FF + carry logic Flit Descriptor Format Data Flit 35 [1] 34 [1] 33 [1] 32..23 [10] 22..15 [8] 14..5 [10] 4..2 [3] 1..0 [2] Head? Tail? Measure? Timestamp Destination Source/Injection oport oport VC * Only the head flit need… text/html 2010-03-11T13:35:38-04:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=meeting_minutes&rev=1268332538&do=diff -> Older status [ 2009 ] WW2, Jan. 4, 2010 * CAD tool * Interconnect HDL * Merging the flit and credit channel selection criterion actually doesn't save hardware * Additional level of N 2-to-1 select_earliest to choose the earlier of the flit and credit channel to represent this node. This alone wipes out the benefit of using 2 copies of simple N-to-1 select_earliest components * More delay with the additional layer as well text/html 2010-03-04T18:03:18-04:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=navigation&rev=1267743798&do=diff * Main * Weekly Status * Research Survey * Project Plan * Simulator * CAD * On-Chip Interconnect * HDL * Wall * Foxcove-4 text/html 2010-02-24T17:01:30-04:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=cad&rev=1267048890&do=diff The CAD tool takes a user network and maps it onto the on-chip simulator framework. Suppoted Systems * Visual C++ 2008 * Linux-like systems The CAD tool is located in the main SVN under cad/. Command bamboo -u <user file> -a <arch file> -o <output byte file> [Options] text/html 2010-02-24T17:00:14-04:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=simulator&rev=1267048814&do=diff <- Index Supported Systems * Visual C++ 2008 * Linux-like systems The simulator is located at sim/. Command sim <config_file> <ready_delta> <sim_time_steps> [Option] Note that sim_time_steps here indicates the duration in which measurement flits will be generated. If a warmup phase is specified, a certain number of warmup cycles will be run before we start counting the measurement cycles.