http://www.eecg.toronto.edu/~wangda/fame/wiki/ 2010-09-28T23:11:23-04:00 http://www.eecg.toronto.edu/~wangda/fame/wiki/ http://www.eecg.toronto.edu/~wangda/fame/wiki/lib/images/favicon.ico text/html 2010-09-08T22:10:26-04:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=hdl&rev=1283998226&do=diff Device Part Logic Block RAM XC5VLX110 17,280 V5 slices 128 x 36Kb block RAM (4,608 Kb) XC2VP30-6ff896 27,392 logic cells 136 x 18Kb block RAM (2,448 Kb) * V5 slice = 4 LUTs + 4 FFs * logic cell ~= 1 LUT + 1 FF + carry logic Control Unit The Control Unit receives 16-bit double words from the UART that encode the command and data required to control the DART simulator. text/html 2010-07-23T13:59:40-04:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=meeting_minutes&rev=1279907980&do=diff -> Older status [ 2009 ] Week Date Task Status 1 Jul. 19 - Jul. 25 Thesis: architecture, implementation done 2 Jul. 26 - Aug. 1 Thesis: case study & experiments 3 Aug. 2 - Aug. 8 Thesis: case study & experiments 4 Aug. 9 - Aug. 15 Thesis: wrap-up 5 Aug. 16 - Aug. 22 More revision 6 Aug. 23 - Aug. 24 RAM packing experiment 7 Aug. 30 - Sep. 5 Must submit thesis here 8 Sep. 6 - Sep. 12 Presentation slides 9 Sep. 13 …