http://www.eecg.toronto.edu/~wangda/fame/wiki/ 2009-11-23T07:12:11-05:00 http://www.eecg.toronto.edu/~wangda/fame/wiki/ http://www.eecg.toronto.edu/~wangda/fame/wiki/lib/images/favicon.ico text/html 2009-11-20T13:19:27-05:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=wall&rev=1258741167&do=diff Jun. 9, 2009 Summary of the network-related files in Flexus: * components/Nic/NicXImpl.hpp * components/Common/Transports/NetworkTransport.hpp * components/Common/Slices/NetworkMessage.hpp * src, dest, vc, size, src_port, dst_port * components/ProtocolEngine/he_exec_engine.hpp/cpp * Home engine (in ProtocolEngine), translates memory transport to network transport text/html 2009-11-18T19:03:23-05:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=meeting_minutes&rev=1258589003&do=diff WW3, Jan. 13, 2009 * Next week: * Elias: summary on the FAST project * Danyao: summary on the ProtoFlex project WW4, Jan. 20, 2009 * Raised issue: How detailed should these be modeled in functional simulation? * wrong-path execution * out-of-order execution text/html 2009-11-17T20:43:23-05:00 Danyao Wang http://www.eecg.toronto.edu/~wangda/fame/wiki/doku.php?id=hdl&rev=1258508603&do=diff Device Part Logic Block RAM XC5VLX110 17,280 V5 slices 128 x 36Kb block RAM (4,608 Kb) XC2VP30-6ff896 27,392 logic cells 136 x 18Kb block RAM (2,448 Kb) * V5 slice = 4 LUTs + 4 FFs * logic cell ~= 1 LUT + 1 FF + carry logic Flit Descriptor Format Data Flit 35 [1] 34 [1] 33 [1] 32..23 [10] 22..15 [8] 14..5 [10] 4..0 [5] Head? Tail? Measure? Timestamp Destination Source/Injection Ununsed * Only the head flit need to carry source inf…