FPGA-Aided Microarchitecture Exploration

hdl

2009-11-17T20:43:23-05:00

Device Part Logic Block RAM XC5VLX110 17,280 V5 slices 128 x 36Kb block RAM (4,608 Kb) XC2VP30-6ff896 27,392 logic cells 136 x 18Kb block RAM (2,448 Kb) * V5 slice = 4 LUTs + 4 FFs * logic cell ~= 1 LUT + 1 FF + carry logic Flit Descriptor Format Data Flit 35 [1] 34 [1] 33 [1] 32..23 [10] 22..15 [8] 14..5 [10] 4..0 [5] Head? Tail? Measure? Timestamp Destination Source/Injection Ununsed * Only the head flit need to carry source inf…

interconnect

2009-08-31T03:35:36-05:00

The global on-chip interconnect is used to facilitate communication among the simulator nodes (Traffic Generators, Flit Queues and Routers). The preferred interconnect architecture should be simple, and provide high throughput and low latency. Conceptually, the on-chip interconnect is a black box, that delivers flits from source nodes to destination nodes in the order of their timestamps. The flit stream for each source-destination pair must be strictly in order of increasing timestamp values to…

meeting_minutes

2009-11-18T19:03:23-05:00

WW3, Jan. 13, 2009 * Next week: * Elias: summary on the FAST project * Danyao: summary on the ProtoFlex project WW4, Jan. 20, 2009 * Raised issue: How detailed should these be modeled in functional simulation? * wrong-path execution * out-of-order execution

navigation

2009-08-06T14:01:14-05:00

* Main * Weekly Status * Research Survey * Project Plan * Simulator * On-Chip Interconnect * HDL * Wall

notes

2009-07-30T16:11:13-05:00

The core of the project is the interconnection network as described on the start page. On top of that, we propose to build a cache simulator that allows the study of things such as cache coherence protocols for large CMPs. This calls for a three-tiered system:

requirement

2009-03-31T03:59:00-05:00

Interfaces Some type of interface is necessary to interact with external components such as CPU simulators or memory system simulators. This may include a driver to translate software API calls to a hardware protocole, and the hardware protocol itself.

research_survey

2009-10-22T17:21:51-05:00

This page contains a summary of on-going research projects that use FPGAs to accelerate computer architecture simulation. Network-on-Chip * Micro's special edition on on-chip interconnects * On-chip interconnects at SoCCentral Router Microarchitecture and Flow Control * Virtual-channel flow control. Dally. Parallel and Distributed Systems, March 1992. * Express virtual channels: towards the ideal interconnection fabric. Kumar, Peh et al. ISCA 2007.

simulator

2009-10-20T11:57:04-05:00

<- Index Supported Systems * Visual C++ 2008 * Linux-like systems The simulator is located at sim/. Command sim [Option] Note that sim_time_steps here indicates the duration in which measurement flits will be generated. If a warmup phase is specified, a certain number of warmup cycles will be run before we start counting the measurement cycles.

start

2009-08-06T14:00:53-05:00

Increasing number of modern digital systems now use interconnection networks as the communication fabric. Simulation is an essential tool to evaluate the performance of interconnection networks, but detailed simulation in software is often slow. Since a network has few global states, and most nodes in the network are quasi-independent from one another, there is opportunity for hardware acceleration.

wall

2009-11-20T13:19:27-05:00

Jun. 9, 2009 Summary of the network-related files in Flexus: * components/Nic/NicXImpl.hpp * components/Common/Transports/NetworkTransport.hpp * components/Common/Slices/NetworkMessage.hpp * src, dest, vc, size, src_port, dst_port * components/ProtocolEngine/he_exec_engine.hpp/cpp * Home engine (in ProtocolEngine), translates memory transport to network transport