Peter Yiannacouras

PhD Candidate

Computer Group
Department of Electrical and Computer Engineering
Faculty of Engineering
University of Toronto

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Contact

Edward S Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto
10 King's College Road
Toronto, Ontario
Canada M5S 3G4

email:

Tel: (416) 978-1652
Office: LP392 (Pratt Building - PT on the map)

Brief Bio

I received my BASc from the University of Toronto's Engineering Science program in the Computer Option in 2003. I have completed my MASc from the University of Toronto's ECE department in September of 2005 and am now pursuing a PhD at the same university. And in 2006, I worked at Intel Microarchitecture Research Labs.

Research

My research interests are in architecture, systems design, and reconfigurable devices. My graduate work has been in FPGA-based soft processors and their customization. We've developed an infrastructure for rapidly generating efficient RTL descriptions of a processor from an input description. We've dubbed the system SPREE (Soft Processor Rapid Exploration Environment) and more can be found about it by going to The SPREE Home Page. We've migrated SPREE to real hardware connected to DDR SDRAM and found that our embedded benchmarks are generally compute bound. Recently we've investigated adding vector extensions to soft processors as a means of increasing their compute power in a scalable and user-selectable way.

Supervisors

Journal Publications

Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow, A Desktop Computer with a Reconfigurable Pentium, ACM Transactions on Reconfigurable Technology and Systems, Vol. 1, No. 1, pp. 5:1-5:15 March 2008 (pdf)
Martin Labrecque, Peter Yiannacouras, and J. Gregory Steffan, Custom Code Generation for Soft Processors, SIGARCH Computer Architecture News, Vol. 35, No. 3, pp. 9-19, June 2007.
Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Exploration and Customization of FPGA-Based Soft Processors, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 26, No. 2, pp. 266-277, February 2007 (pdf)

Refereed Conference Publications

Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, VESPA: Portable, Scalable, and Flexible FPGA-Based Vector Processors, International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2008, Atlanta, GA. (pdf ppt)
Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan, Scaling Soft Processor Systems, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Palo Alto, CA, April, 2008 (pdf - Acceptance Rate 25%)
Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow, An FPGA-Based Pentium(R) in a Complete Desktop System, ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2007, Monterey, CA. (pdf - Acceptance Rate 24%)
Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Application-Specific Customization of Soft Processor Microarchitecture, ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2006, Monterey, CA. (pdf ppt - Acceptance Rate 22%)
Peter Yiannacouras, Jonathan Rose, and J. Gregory Steffan, The Microarchitecture of FPGA-Based Soft Processors, International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), September 2005, San Francisco, CA. (pdf ppt - Acceptance Rate 31%)

Workshops

Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Improving Memory Systems for Soft Vector Processors, Workshop on Soft Processor Systems (WoSPS - in conjunction with PACT), October 2008, Toronto, ON.(pdf ppt)
Martin Labrecque, Peter Yiannacouras, and J. Gregory Steffan, Custom Code Generation for Soft Processors, Reconfigurable and Adaptive Architecture Workshop (RAAW - in conjunction with MICRO), December 2006, Orlando, FA.(pdf)

Posters

Peter Yiannacouras, Jonathan Rose, and J. Gregory Steffan, SPREE: Microarchitectural Exploration on FPGAs, Workshop on Architecture Research using FPGA Platforms (WARFP - in conjunction with HPCA), February 2005, San Francisco, CA. (pdf ppt)
Peter Yiannacouras and Jonathan Rose, A Parameterized Automatic Cache Generator for FPGAs, Field Programmable Technologies (FPT 2003), December 2003, Tokyo, Japan.

Theses

Peter Yiannacouras, The Microarchitecture of FPGA-Based Soft Processors, MASc Thesis, University of Toronto, 2005. (pdf)
Peter Yiannacouras, An Automatic Cache Generator for Stratix FPGAs, BASc Thesis, University of Toronto, 2003. (pdf)

Courses

PPIT - Prospective Professors in Training

MIE3002 Engineering Teaching and Learning

PhD

ECE1718 Reconfigurable Computing
ECE1387 CAD for Digital Circuit Synthesis and Layout
ECE1762 Data Structures and Algorithms
CSC2227 Design and Implementation of Operating Systems
ECE1772 Motion Analysis in Computer Vision

MASc

ECE1718 Modern and Emerging Architectures
ECE1769 Behavioural Synthesis
ECE1724 Runtime Program Optimization
ECE1746 Distributed Systems
ECE1768 Reliability of Integrated Circuits

4th Year Undergrad technical courses

ECE552 Computer Architecture
CSC444 Software Engineering
ECE460 Computer Networks
ECE431 Digital Signal Processing
ECE435 Digital Electronics
ECE532 Digital Hardware
ECE451 VLSI Systems
ECE540 Optimizing Compilers

TAing

ECE385F - Microprocessor Systems, 2008 Fall
ECE243S - Computer Organization, 2008 Spring
ECE385F - Microprocessor Systems, 2007 Fall
ECE243S - Computer Organization, 2007 Spring
ECE241F - Digital Systems, 2006 Fall
ECE243S - Computer Organization, 2006 Spring
ECE241F - Digital Systems, 2005 Fall
ECE243S - Computer Organization, 2005 Spring
ECE241F - Digital Systems, 2004 Fall
ECE241S - Digital Systems, 2004 Spring
ECE352F - Computer Organization, 2003 (My ECE352 stuff)
ECE352F - Computer Organization, 2002
CSC190S - Data Structures and Algorithms, 2002

Personal

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Last Updated January 2, 2008; visitors since March 20, 2006 (stats)