Architectural Description

The input to SPREE is a textual description in the form of C++ code. The description provides:

  1. List of Components
  2. Components are implemented in Verilog by the user and are imported into the SPREE Component Library. This allows for FPGA-specific implementations of the components in order to ensure efficient synthesis. When building a processor, the user specifies which components from the library are desired.

  3. The Datapath Wiring
  4. The processor is defined primarily by its datapath. Users can control the flow of data through the components and insert pipe registers where desired. The number of stages (pipelined) or number of cycles per instruction (unpipelined) is inferred by the amount of cycle latency in the described datapath.

  5. Hazard Detection and Forwarding (Pipelined)
  6. These are implemented by the user as part of the datapath, this must be done (currently) manually to ensure proper execution.

An excerpt from a simple example is shown below. The format of the input is currently C++ code, however, we plan to develop a text parser for the system.

/****************** Component List *******************/
RTLComponent *addersub=new RTLComponent("addersub");
RTLComponent *logic_unit=new RTLComponent("logic_unit");
RTLComponent *shifter=new RTLComponent("shifter","barrel");
RTLComponent *mul=new RTLComponent("mul");
RTLComponent *reg_file=new RTLComponent("reg_file");
RTLComponent *ifetch=new RTLComponent("ifetch");
RTLComponent *branchresolve=new RTLComponent("branchresolve");

/*************** Datapath Wiring ****************/ // RS Fanout addConnection(reg_file,"a_readdata",addersub,"opA"); addConnection(reg_file,"a_readdata",logic_unit,"opA"); addConnection(reg_file,"a_readdata",shifter,"sa"); addConnection(reg_file,"a_readdata",mul,"opA"); addConnection(reg_file,"a_readdata",branchresolve,"rs"); ... /*********************** Hazard detection *******************/ HazardDetector *rs_haz=newHazardDetector(rs_reg,"q",dst1,"q"); HazardDetector *rt_haz=newHazardDetector(rt_reg,"q",dst1,"q"); stallOnHazard(rs_haz,1); stallOnHazard(rt_haz,1);