RTL Generation

The SPREE RTL Generator performs a number of operations needed to turn the architecture description input into synthesizable Verilog. These are listed below:

  1. Datapath vs ISA verification
  2. The datapath is checked to make sure it has all the functionality required to execute the ISA (currently fixed to be a subset of MIPS I), and also that the wiring between components is consistent with the flow of data implied by each instruction.

  3. Removal of unused connections/components
  4. After verification, any connections/components that were not used by any instruction is removed. This allows for ISA subsetting, where one can reduce the processor by restricting what fraction of the ISA is used.

  5. Datapath Analysis (timing)
  6. The datapath is examined and the generator determines the stages of each component. Further checks are made for structural hazards and other illegal configurations.

  7. Control Generation
  8. Either pipelined or unpipelined control is generated which ensures components are enabled only when their data is ready, and allows for stalled components.