RTL Generation
The SPREE RTL Generator performs a number of operations needed to turn the architecture description input into synthesizable Verilog. These are listed below:
- Datapath vs ISA verification
The datapath is checked to make sure it has all the functionality required to execute the ISA (currently fixed to be a subset of MIPS I), and also that the wiring between components is consistent with the flow of data implied by each instruction.
- Removal of unused connections/components
After verification, any connections/components that were not used by any instruction is removed. This allows for ISA subsetting, where one can reduce the processor by restricting what fraction of the ISA is used.
- Datapath Analysis (timing)
The datapath is examined and the generator determines the stages of each component. Further checks are made for structural hazards and other illegal configurations.
- Control Generation
Either pipelined or unpipelined control is generated which ensures components are enabled only when their data is ready, and allows for stalled components.