library altera; use altera.maxplus2.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity wrapper is port ( --in your designs the following pins should be kept as inputs --or bidirectionals unless you intend to use them as outputs address: in std_logic_vector(23 downto 1); data : in std_logic_vector (15 downto 0); codata : in std_logic_vector (31 downto 0); srama : in std_logic_vector (17 downto 0); sramdl : in std_logic_vector (15 downto 0); sramdh : in std_logic_vector (15 downto 0); codsync : in std_logic; codread : in std_logic; codwrite : in std_logic; sram1en : in std_logic; sram2en : in std_logic; sram1oe : in std_logic; sram2oe : in std_logic; sram1we : in std_logic; sram2we : in std_logic; sram1ud : in std_logic; sram2ud : in std_logic; sram1ld : in std_logic; sram2ld : in std_logic; br_sfpga : in std_logic; bg_sfpga : in std_logic; bgack_sfpga : in std_logic; clk : in std_logic; fc : in std_logic_vector ( 2 downto 0); berr : in std_logic; as : in std_logic; halt : in std_logic; reset : in std_logic; dtack : in std_logic; lds : in std_logic; uds : in std_logic; rw : in std_logic; irqsf: in std_logic; iacksf : in std_logic; hex0 : in std_logic_vector(7 downto 0); hex1 : in std_logic_vector(7 downto 0); hex2 : in std_logic_vector(7 downto 0); hex3 : in std_logic_vector(7 downto 0); sfpga_digital : in std_logic_vector(33 downto 0); sfpga_con40 : in std_logic_vector(31 downto 0); sfpga_logic : in std_logic_vector(17 downto 0); sfpga_con60 : in std_logic_vector(51 downto 0); pclk : in std_logic; led : out std_logic_vector(15 downto 0) ); end wrapper; architecture temp_sfpga of wrapper is --in your designs replace this component declaration with a --component declaration of your top-level entity --signal declarations for internal signals signal myClk,myreset,preset,Cin: std_logic; signal fibout : std_logic_vector (15 downto 0); signal Cout :std_logic; --signal myhex0,myhex1,myhex2,myhex3 : std_logic_vector (3 downto 0); component fibo PORT (Clk,reset,preset,Cin :IN STD_LOGIC; fibout :OUT STD_LOGIC_VECTOR(15 downto 0); Cout :OUT STD_LOGIC); end component; component seg7 IS PORT( Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END component; begin --------------- Your code here ---------------- end temp_sfpga;