DART: An FPGA-Based Network-on-Chip Simulation Acceleration Engine

The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms---hence the study of new NoC designs can be very time-intensive. To address this challenge we propose DART, a fast and flexible FPGA-based NoC simulation architecture. Rather than laying the NoC out in hardware on the FPGA like previous approaches, our design virtualizes the NoC by mapping its components to a generic NoC simulation engine, composed of a fully-connected collection of fundamental components (e.g., routers and flit queues). This approach has two main advantages: (i) since FPGA implementation is decoupled it can simulate any NoC; and (ii) any NoC can be mapped to the engine without resynthesizing it, which can take time for a large FPGA design. We demonstrate that an implementation of DART on a Virtex II Pro FPGA can achieve over 100x speedup relative to a cycle-based software simulator, while maintaining the same level of simulation accuracy.

Papers and Talks:

DART: A Programmable Architecture for NoC Simulation on FPGAs, Danyao Wang, Charles Lo, Jasmina Vasiljevic, Natalie Enright Jerger, and J. Gregory Steffan, to appear in IEEE Transactions on Computers, 2012.

DART: Fast and Flexible NoC Simulation using FPGAs, (pdf, ppt) Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan, in International Symposium on Networks-on-Chip, Pittsburgh, PA, May, 2011.

DART: Fast and Flexible FPGA-Based NoC Simulation, (pdf) Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan, Workshop on Architectural Research Prototyping, Saint Malo, France, June, 2010.

An FPGA-based Accelerator Platform for Network-on-Chip Simulation, (pdf) Danyao Wang, M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2010.


DART source files are available for download here.