VPR and T-VPack 5.0.2

Full CAD Flow for Heterogeneous FPGAs

*NEW* VPR 6.0 Full Release! Download here

This website is deprecated, please use google code repository for future updates on VPR
Prior stable version:
5.0.2 -- last updated March 24, 2009.

VPR is a FPGA placement and routing tool that was designed to enable FPGA architecture exploration. Placement and routing of user circuits can be performed on a wide range of architectures. Since its initial release over 10 years ago, FPGAs have evolved considerably and now contain many new architectural features. This website describes a new version of VPR that is delivers four significant new features:

Supporting heterogeneous FPGA requires an entire CAD flow above the packing placement and routing supplied by VPACK and VPR. Accompanying this release of VPR is a full set of CAD tools offering a full Verilog-to-routing flow. This flow starts with ODIN, that provides elaboration of Verilog. Logic synthesis is performed using a specific version of the ABC tool from UC Berkeley. Packing is performed with an updated version of TVPack that can pass heterogenous blocks through untouched. Finally, placement and routing is performed with the latest version of VPR. There are limitations in this flow that are detailed in this presentation. In particular, the front end synthesis tool, ODIN, only identifies multipliers as hard blocks. Other blocks may be added by modifying the program to find other hard structures. Any hard blocks that are found are treated as block boxes for all the tools except VPR. This means inputs to the blocks are treated as Primary Outputs and outputs are treated as Primary Inputs and, as a result, timing-driven optimization of paths containing blocks is not possible.

Architecture Files

The area and performance of a FPGA is affected by its architecture and the implementation of the architecture. Accordingly, when using VPR, area and delay measurements must be provided to enable VPR to produce accurate area and delay measurements of the target FPGA. It is often difficult and time-consuming to obtain these delays independently and, therefore, to simplify the use of VPR, a large collection of compatible architecture files (containing accurate area and delay measurements) are provided at this site. The site includes files for different architectures and also different designs of these architectures. The different designs of a given architecture are created by varying process technologies and the optimization objectives used during the transistor sizing of each architecture. Full details on how these designs were created are available on the site.

More Information


To download the latest source code for VPR and the supporting CAD tools click here

If you have questions regarding VPR or the CAD tool flow please e-mail vpr@eecg.utoronto.ca