Technology Mapping for Large CPLDs
Abstract
In this paper we present a new technology
mapping algorithm for use with complex PLDs
(CPLDs), which consist of a large number of
PLA-style logic blocks. Although the
traditional synthesis approach for such devices
uses two-level minimization, the complexity of
recently-produced CPLDs has resulted in a
trend toward multi-level synthesis. We describe
an approach that allows existing multi-level
synthesis techniques [13] to be adapted to
produce circuits that are well-suited for
implementation in CPLDs. Our algorithm
produces circuits that require up to 90% fewer
logic blocks than the circuits produced by a
recently-published algorithm.
Reference
Jason Anderson and Stephen D. Brown, "Technology Mapping for Large CPLDs," IEEE Design Automation Conference, San Francisco, June 1998, pp. 698-703.
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