Difficulty of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow
Abstract
This paper studies the difficulty of predicting interconnect delay in
an industrial setting. Fifty industrial circuits, Altera's Quartus II
CAD software, and Altera's Stratix and Stratix II FPGA architectures
were used in the study. We show that there is a large amount of inherent
randomness in a state-of-the-art FPGA placement algorithm. Thus, it
is impossible to predict interconnect delay with a high degree of
accuracy. Futhermore, we show that a simple timing model can be used to
predict some aspects of interconnect timing with just as much accuracy
as predictions obtained by running the placement tool itself. Finally,
we examine the benefits of using the simple timing model in a timing
driven physical synthesis flow, and attempt to establish an upper bound
on these possible gains, given the difficulty of interconnect delay
prediction.
Reference
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, and Stephen D. Brown, "Difficulty of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow", In Proceedings of the Workshop on System Level Interconnect Prediction, Munich, Germany, March 2006, pp. 3-8.
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