Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices
Abstract
Circuits implemented in FPGAs have delays that are dominated by its
programmable interconnect. This interconnect provides the ability to
implement arbitrary connections. However, it contains both highly
capacitive and resistive elements. The delay encountered by any
connection depends strongly on the number of interconnect elements
used to route the connection. These delays are only completely known
after the place and route phase of the CAD flow. We propose to produce
timing-directed placement constraints for designs using a concept
referred to as critically connect components (CCCs). These placement
constraints are created after an initial unconstrained run of the
QuartusII place and route tool. In this manner, the placement tool can
create constraints that guide subsequent passes away from any mistakes
made on the initial pass. Experiments conducted on Altera's APEX20K
family using this methodology along with LogicLock placement constraints
indicate an average performance gain of approximately 6% on a varied
suite of industrial circuits.
Reference
Deshanand Singh, Terry Borer, Stephen D. Brown, "Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices," International Conference on VLSI, Las Vegas, NV, February 2003.
(Download Full Paper)