Notes

Outline

EVE: A CAD Tool Providing Placement and Pipelining Assistance for High-Speed FPGA Circuit Designs William Chow Supervisor : Prof. Jonathan Rose M.A.Sc. Thesis Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto September 28, 2001

Motivation Context: High-speed circuit designs, how? Push-button design flow Automatic: design -> circuit 0.18 mm, struggling to achieve 150MHz+ Von Herzen’s paper [VonH97] 250MHz FPGA, 0.6mm in 1997! Useful “Event Horizon” concept (later) EVE: EVent horizon Editor

Event Horizon

Context Von Herzen’s approach Set speed goal Build by construction using Event Horizon concept EVE Start with placed and routed design Increase speed by manual editing small designs

Goals Construct a manual editor focussing on packing/placement/pipelining level of the Event Horizon design methodology to allow a designer to increase speed easier Gain insights to better placement and routing techniques through extensive manual circuit editing experience

Design Objectives of EVE Target real FPGA architecture : Xilinx Virtex-E Give full low-level control Give instant performance feedback Assist pipelining (3&4) not supported by Xilinx Tools

EVE: two operating modes Timing Exact Microscopic Placement (TEMP) Mode Change placement and packing of circuit components Instant timing feedback Invoke horizon : suggest good placement positions Pipelining Mode Maintain correct functionality during flip-flop insertion and flip-flop motion Instant feedback of new circuit speed estimation Flip-flop placement optimizations

Horizon From “Event Horizon” Gradient of colours Horizon Radius Where to evaluate Limit computation Display timing -ve : speed improves +ve : speed degrades

Timing Exact Microscopic Placement (TEMP) Mode Placement Packing Timing Feedback Horizon More info Better answer

Implementation of TEMP mode Instant feedback Internal Timing Analysis Accurate timing Database of real delays Compression by 100x (100MB->1MB) High Interactivity Integrate tightly with Xilinx backend (FPGA Editor) for quick incremental P&R,timing

Partial Incremental Timing Analysis Full Timing Analysis (TA) O(n) Forward &Backward Sweep as in [HSC83] Faster: Only rebuild modified portion of circuit

Delay Database Delay Extraction RC Models: Elmore, Penfield Rubinstein Not possible in EVE Extracting Logic Delays Extracting Routing Delays Delay Database Compression

Routing Delay Compression

Backend Integration Existing tools are insufficient Lack ease for incremental flow Full CAD flow is slow Solution: Interface with Xilinx manual editor - FPGA Editor Full set of commands for circuit editing Use named pipes on WIN NT platform

Event Horizon: Pipelining Pipeline to extend Event Horizon

Pipelining Mode

Baseline Circuits Generation (Push-button flow baseline) Input is VHDL or Verilog Synthesize using Synplify Pro 6.2, freq = s Place and route using Xilinx backend tools Obtain frequency from reports repeat step (2) to (4), increasing s 10% until done Using frequency in (5), do Multi-Pass Place&Route (MPPR) for 10 runs, pick the best design  [+10%]

Results: Using TEMP mode only

Example : Vision

Vision: Before

Vision: After

Results: Using both TEMP and pipelining modes

Observations (1) Pack and unpack slices during placement and routing is good

Observations (2)

Observations (3)

Observations (4)

Live Demo

Conclusion Proposed a high-speed manual circuit design methodology Created a manual editor Targets real designs: Xilinx Virtex-E Focus on pipelining, placement, packing Full low-level control Instant exact timing feedback Results: speed increased up to +19%, avg +12.7% for 8 ccts

Future Work Synthesis in Event Horizon framework Extend EVE to support Virtex-II, etc. Automate manual optimizations in EVE Make pipelining mode more useful