EVE: A CAD Tool Providing Placement and Pipelining Assistance for High-Speed FPGA Circuit Designs

Event Horizon

src CLB

250MHz à budget = 4ns

0.8

0.4

1.2

0.8

1.2

0.4

Max clock skew = 0.1ns, clock-to-output delay = 1.3ns,

LUT delay+FF setup time = 1.5ns

•Choose placement of target CLB

•

•Set target speed

•Know chip spec

•Calculate Event Horizon

Max routing delay = 4.0-0.1-1.3-1.5 = 1.1ns