20
Baseline Circuits Generation
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(Push-button flow baseline)
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Input is VHDL or Verilog
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Synthesize using Synplify Pro 6.2, freq = s
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Place and route using Xilinx backend tools
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Obtain frequency from reports
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repeat step (2) to (4), increasing s
10%
until done
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Using frequency in (5), do Multi-Pass Place&Route (MPPR) for 10 runs, pick the best design
[+10%]
(skip!)
