<LI><A NAME="tex2html2" HREF="node2.html#54">FPGA with Embedded Memory</A>
<LI><A NAME="tex2html3" HREF="node2.html#71">Memory/Logic Routing Structures</A>
<LI><A NAME="tex2html4" HREF="node4.html#95">Example Generated Circuit</A>
<LI><A NAME="tex2html6" HREF="node6.html#183">Effects of  <IMG WIDTH=26 HEIGHT=27 ALIGN=MIDDLE ALT="tex2html_wrap_inline363" SRC="img1.gif"  >  on routability and delay</A>
