Memory/Logic Interconnect Flexibility in FPGAs with
Large Embedded Memory Arrays

Steven J.E. Wilton, Jonathan Rose and Zvonko G. Vranesic
Department of Electrical and Computer Engineering
University of Toronto
Toronto, Ontario, Canada M5S 1A4
wilton@eecg.toronto.edu

Abstract:

As the capacities of field-programmable gate arrays (FPGAs) grow, it becomes desirable to create FPGAs with embedded memory arrays. This paper examines the flexibility of the interconnect structure that joins memory and logic. For architectures with only a few memory arrays, we find that both the routability and the delay of circuits are insensitive to the memory/logic interconnect flexibility, which implies that this interconnection can be made very inflexible. This is in contrast to the logic connection block flexibility, which has been shown to require high flexibility [1]. For architectures with more arrays, the memory/logic interconnect flexibility requirements increase and approach those of logic interconnect.

• Introduction
• Architectural Framework
• Architecture Evaluation Method
  • Benchmark Circuit Generation
  • Circuit Implementation Procedure
• Experimental Results
  • Effect of Fm on Routability
  • Effect of Fc on choice of Fm>
  • Circuit Delay
• Conclusions
• References
• About this document ...