Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision		 Previous revision
wiki:aca2017:assignments [2018/03/26 21:29] – Andreas Moshovoswiki:aca2017:assignments [2018/04/22 19:30] (current) – Andreas Moshovos
Line 1: Line 1:
 +====== Assignment #5 ======
 +Please read the following publication: {{ :wiki:aca2017:selfoptimizingmemcntrl.pdf | Self-Optimizing Memory Controllers: A Reinforcement Learning Approach, Ipek et al., ISCA 2008. }}
 +
 +Then answer the following questions:
 +
 +  * A DRAM chip is contains several independent banks. At a high-level what is the sequence of operations that need to be issued to a bank to read and write data? Briefly explain what a row is and what purpose it serves.
 +  * Briefly explain what the FR-FCFS policy is?
 +  * What is a Markov Decision Process? Please formally define it.
 +  * Why is a discounted cumulative reward function more appropriate for infinite horizon problems?
 +  * Explain what are Q-values.
 +  * What is  epsilon-greedy action selection? Why is it needed?
 +  * What is CMAC and why is it used here? What goal does it serve?
 +  * In FIg. 6(a) why are there two parallel vertical pipes?
 +
 +
 ====== Assignment #4 ====== ====== Assignment #4 ======
 You are asked to think about the on and off-chip memory system for our DaDianNao like accelerator. Let's restrict attention to CNNs, where the layers are convolutions, pooling and fully-connected. You are asked to think about the on and off-chip memory system for our DaDianNao like accelerator. Let's restrict attention to CNNs, where the layers are convolutions, pooling and fully-connected.
Line 14: Line 29:
  
 For all options calculate the bandwidth that would be needed from off-chip. That would be the number of bytes that are needed to read the activatios and weights, plus the number of bytes that are needed to write the output weights, and the sum of these divided by the number of cycles the accelerator takes to do the computation. Can you compare and contract diffferent on-chip memory allocation policies between weights and activations with regards to the overall off-chip bandwidth? For all options calculate the bandwidth that would be needed from off-chip. That would be the number of bytes that are needed to read the activatios and weights, plus the number of bytes that are needed to write the output weights, and the sum of these divided by the number of cycles the accelerator takes to do the computation. Can you compare and contract diffferent on-chip memory allocation policies between weights and activations with regards to the overall off-chip bandwidth?
 +
 +[[wiki:aca2017:assignment4|Find the input data and further information here. Thank you to Kevin Siu for preparing these.]]
  
 ====== Assignment #3 ====== ====== Assignment #3 ======