Due Thursday, March 8, before class. Submission link will be provided in due time. Do not e-mail.

Description

Due Thursday, February 15, before class. Submission link will be provided in due time. Do not e-mail.

Repeat Assignment #1 but use Intel's PIN tool.

Due Thursday, February 1, before class. Submission link will be provided in due time. Do not e-mail.

Getting to know the Simplescalar Simulator Read the lab0 and lab4 handouts from ECE552. These will introduce you to the Simplescalar simulator. Our goal here is to modify the cache simulation module to implement a different replacement policy. The cache module is implemented in cache.c. The simplest simulator that uses it is sim-cache.c.

Part A: Modify cache.c to add a “not MRU” replacement policy. You will have to modify the cache_access() function and potentially others. For example, check whether you need to change cache_probe() too. Not MRU replaces one cache block a random except for the MRU. Sim-cache for the go and gcc traces first with LRU replacement and then with your notMRU.

Part B: Read the following paper: Adaptive Insertion Policies for High-Performance Caching, M. K. Qureshi et al, IEEE/ACM Intl’ Symposium on Computer Architecture, .

Modify cache.c to implement DIP. No need to implement set dueling.