https://www.eecg.toronto.edu/~moshovos/000/ 2026-04-29T21:04:47+00:00 https://www.eecg.toronto.edu/~moshovos/000/ https://www.eecg.toronto.edu/~moshovos/000/lib/tpl/bootstrap3/images/favicon.ico text/html 2018-03-23T17:58:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.eecg.toronto.edu/~moshovos/000/doku.php?id=wiki:aca2017:assign3&rev=1521827904&do=diff Warning:) I have not written a simulator for the accelerator in question. So, I do not have strong opinions on what needs to be done and how. Moreover, I do not have the experience with potential problems that may arise for this specific case. However, I have experience with processor simulators which I will happily share as needed. So approach this more as a text/html 2018-03-28T19:31:34+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.eecg.toronto.edu/~moshovos/000/doku.php?id=wiki:aca2017:assignment4&rev=1522265494&do=diff Below are two CSV files (packaged into a single .zip file). One for the activations and one for the weights of MobileNet. The columns of the weight file are: * Layer: Name of the layer * In: Name of the layer that is input to this layer (i.e. read the corresponding line in activation csv file to get input activation size) text/html 2018-04-22T23:30:51+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.eecg.toronto.edu/~moshovos/000/doku.php?id=wiki:aca2017:assignments&rev=1524439851&do=diff Assignment #5 Please read the following publication: [ Self-Optimizing Memory Controllers: A Reinforcement Learning Approach, Ipek et al., ISCA 2008. ] Then answer the following questions: * A DRAM chip is contains several independent banks. At a high-level what is the sequence of operations that need to be issued to a bank to read and write data? Briefly explain what a row is and what purpose it serves. text/html 2018-03-27T15:12:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.eecg.toronto.edu/~moshovos/000/doku.php?id=wiki:aca2017:lectures&rev=1522163535&do=diff Lecture Material and Schedule Alternate Execution Models and Architectures Jan. Tue 9: Meltdown, Virtual Memory and Caches We discussed the Meltdown vunerability. Please refer to the following: "Meltdown Attack". Virtual Memory and Interaction with the Memory Hierarchy: Cache Indexing: