CMP-MSI: Workshop on Chip Multiprocessor Memory Systems and Interconnects


In conjunction with the

13th Annual International Conference on High-Performance Architecture

Sunday, Feb 11, 2007

Phoenix, Arizona


Chip multiprocessors (CMPs) are emerging as the architecture of choice for future high performance processors. CMPs integrate several high -performance processing cores onto the same chip. A high performance  interconnect and memory system are necessary to satisfy the data supply  needs of all these cores especially given the ever increasing speed gap  between processors and main memory systems. At the same time, power, complexity and reliability are additional constraints that must be met by any design.

The fact that now these components will be tightly integrated onto the same die presents opportunities and challenges that are very different than those that existed in previous multi-processor systems. This workshop aims to become a forum for academia and industry to discuss and present ideas and recent  developments in the design and evaluation of on-chip multiprocessor memory systems and interconnects.


The workshop had 46 attendees. The presentation foils are now posted.




Session #1


Performance, Area and Bandwidth Implications on Large-Scale CMP Cache Design  * Presentation *


Li Zhao, Ravi Iyer, Srihari Makineni, Jaideep Moses, Ramesh Illikkal, Donald Newell


System Technology Lab, Intel Corporation


Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors  * Presentation *


Carmelo Acosta †, Francisco J. Cazorla ?, Alex Ramirez †?, Mateo Valero


† Universitat Politecnica de Catalunya ? Barcelona Supercomputing Center


Quantifying and Comparing the Impact of Wrong-Path Memory References in Multiple-CMP Systems  * Presentation *


Ayse Yilmazer1, Resit Sendag1, Joshua J. Yi2


1 University of Rhode Island 2 Freescale Semiconductor, Inc.


Coffee Break





Position Paper Session


Providing QoS with Virtual Private Machines  * Presentation *


Kyle J. Nesbit, James Laudon*, and James E. Smith


University of Wisconsin – Madison, Sun Microsystems*


Better than the Two: Exceeding Private and Shared Caches via Two-Dimensional Page Coloring  * Presentation *


Lei Jin Sangyeun Cho


University of Pittsburgh

Session #3


A Reusability-Aware Cache Memory Sharing Technique for High Performance CMPs with Private L2 Caches  * Presentation *


Sungjune Youn, Hyunhee Kim and Jihong Kim


Seoul National University


Analyzing Performance Vulnerability due to Resource Denial­ of ­Service Attack on Chip Multiprocessors  * Presentation *


Dong Hyuk Woo Hsien­Hsin S. Lee


Georgia Institute of Technology


Formal Verification of a Novel Snooping Cache Coherence Protocol for CMP  * Presentation *


Xuemei Zhao, Karl Sammut, and Fangpo He


Flinders University




Erik Altman, IBM

Amirali Baniasadi, Victoria

Angelos Bilas, Crete

Babak Falsafi, CMU

Leonidas Kontothanassis, Google
Christos Kozyrakis, Stanford

Andreas Moshovos, Toronto, Organizer

Vijaykrishnan Narayanan, PennState

Yannis Schoinas, Intel

Greg Steffan, Toronto

Per Stenström, Chalmers