Roman Genov

The Edward S. Rogers Sr.
Department of Electrical and Computer Engineering
10 King's College Road
Toronto, Ontario M5S 3G4 Canada	Phone: (416) 946-8666
Fax: (416) 971-2286
Email: roman@eecg.toronto.edu 
URL: http://eecg.toronto.edu/~roman	
RESEARCH INTERESTS 	
	Analog and digital VLSI circuits, systems and algorithms for parallel signal processing and high-performance adaptive computing with application to pattern recognition, focal-plane imaging, communications, autonomous system design, and low-power instrumentation.	
EDUCATION 	
	The Johns Hopkins University, Ph.D., Electrical and Computer Engineering, Baltimore, MD, 08/2002.
Dissertation: Massively Parallel Mixed-Signal VLSI Kernel Machines.
Advisor: Gert Cauwenberghs
Massachusetts Institute of Technology, Visiting Student, AI Lab/CBCL, Cambridge, MA, 1/99-8/99. 
The Johns Hopkins University, M.S.E., Electrical and Computer Engineering, Baltimore, MD, 1998.
GPA 4.00/4.00
Rochester Institute of Technology, B.S., Electrical Engineering, Rochester, NY, 1996.
GPA 4.00/4.00, Highest Honors, Rank in class – 1/316	
PROFESSIONAL EXPERIENCE 	
	University of Toronto, Toronto, ON, 9/2002-Present
Assistant Professor, Electronics Group, Department of Electrical and Computer Engineering. 
The Johns Hopkins University, Baltimore, MD, 9/96-8/2002
Research Assistant, Adaptive Microsystems Lab, Electrical and Computer Engineering Department. 
Designed low-power massively parallel mixed-signal array processor chips providing 1,000 GOPS/Watt (first Support Vector Machine in silicon).
Developed multi-chip PCI parallel processing card achieving ultra-fast real-time performance in data classification (sound) and pattern recognition (image, video) tasks. 
Designed and tested novel high-performance algorithmic A/D converters (with Northrop Grumman Corporation), low-power charge-mode flash converters, and parallel delta-sigma converters. 
Supervised B.S. and M.S. level students in algorithm development and microchip design.
Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, 6/98-7/98.
Visiting Researcher, Autonomous Systems Lab. 
Developed learning algorithms and VLSI architectures for mobile mini-robot navigation. Investigated sensor-processor interfaces.
Xerox Corporation, Webster, NY, 3/96-8/96.    
Design Engineer CO-OP, Advanced Development Team in the Color Imaging Systems Division. Developed and designed electrical and computer systems for new generation color copiers. Responsible for hardware-software co-design with Verilog and Xilinx FPGA tools.
Atmel Corporation, Columbia, MD, 6/95-12/95. 
Design Engineer Intern, Chesapeake Design Center.
Designed, simulated and laid out digital VLSI cells. Developed a Perl extraction tool to automate creation of Verilog ASIC models from HSPICE output.	
CURRENT RESEARCH 	
	High-performance parallel computation: developed mixed-signal VLSI parallel array processors for high-dimensional vector-matrix multiplication; investigated stochastic coding algorithms for achieving full digital resolution of computation. 
Real-time data classification: developed multi-processor engine for kernel-based pattern recognition (Kerneltron); implemented the first Support Vector Machine in silicon.
Low-power A/D conversion: designed parallel charge-mode flash A/D converters, parallel delta-sigma and algorithmic converters for system-on-chip applications.
High-speed, high-resolution A/D conversion: developed a digitally calibrated pipelined A/D converter. 
High-performance instrumentation: designed a single-chip system for multi-channel wide dynamic range track-and-hold mixed-mode signal acquisition for low-power applications.
Autonomous learning systems: investigated reinforcement learning algorithms and VLSI architectures for autonomous agents; extended Q-learning to sensor fusion using self-organizing maps. 	
AWARDS AND HONORS 	
	American Councils for International Education Fellowship, 1994-95.
Rochester Institute of Technology Presidential Fellowship, 1995-96.
Best Student Paper Award, 3rd place, IEEE Midwest Symposium on Circuits and Systems (MWSCAS'2000), 2000. 
Best Presentation Award, IEEE International Joint Conference on Neural Networks (IJCNN'99), 1999. 
Best Student Paper Contest Finalist, IEEE International Symposium on Circuits and Systems (ISCAS'99), 1999. 	
TEACHING	
	Instructor, University of Toronto, Toronto, ON. 
Introductory Electronics, ECE231 1/2003-4/2003 (90-100 students). 
Graduate Teaching Assistant, Johns Hopkins University, Baltimore, MD. 
Digital Signal Processing, 9/97-12/97, 9/98-12/98. 
Electronics Design Laboratory, 1/98-5/98. 
Analog and Digital VLSI Systems and Architecture, 9/99-12/99, 9/2001-12/2001. 
Teaching Assistant, Rochester Institute of Technology, Rochester, NY. 
Digital Systems Design, 2/95-5/95. 
C Programming, 2/96-5/96.	
INVITED PRESENTATIONS	

	“Massively Parallel Mixed-Signal VLSI Kernel Machines,” Seminar Series, Division of Engineering, Brown University, Providence, RI, Feb.25, 2002.
“Massively Parallel Mixed-Signal VLSI Kernel Machines,” Seminar Series, Department of Electrical and Computer Engineering, McGill University, Montreal, QC, Feb.19, 2002.
“Massively Parallel Mixed-Signal VLSI Kernel Machines,” Seminar Series, Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Feb.11, 2002.
“VLSI Array for Massively Parallel Kernel Computation,” Workshop on Neuromorphic Engineering, Telluride, CO, July 2001. 
“Q-Learning: Experiments on Microrobots,” Neural Information Processing Systems (NIPS'1999) workshop “Learning Chips and Neurobots,” Breckenridge, CO, Dec. 1998.	
PROFESSIONAL ACTIVITIES	
	Society Membership: IEEE (Institute of Electrical and Electronic Engineers), Circuits and Systems Society, Solid-State Circuits Society.
Technical Committee Membership: Neural Systems and Applications of the IEEE Circuits and Systems Society.
Conference Program Committees:
Review Committee Member, IEEE Int. Symp. Circuits and Systems (ISCAS’2003).
Technical Program Committee Member, Great Lakes Symposium on VLSI (GLSVLSI’2003).
Program Committee Member, SPIE 2003 Bioengineered and Bioinspired Systems Conference.
Session co-chair: IEEE Int. Symp. Circuits and Systems (ISCAS’2002), “Self-Correcting ADC.”
Journal and Conference Reviews:
IEEE Transactions on Circuits and Systems II (TCAS-II); IEEE Transactions on Neural Networks (TNN); IEEE Int. Symp. on Circuits and Systems (ISCAS); Applied Soft Computing Journal.
High-Technology Entrepreneurship Interactive Program, The Johns Hopkins University, 1999. 
Tau Beta Pi Engineering Future, Leadership and Technical Management Interactive Workshop, 1998.
IEEE Johns Hopkins University Chapter Treasurer, 1997. 	
PUBLICATIONS	
	“Algorithmic Partial Analog-to-Digital Conversion in Mixed-Signal Array Processors,” R. Genov, G. Cauwenberghs, Subm. to IEEE Int. Symp. on Circuits and Systems (ISCAS'2003), Bangkok, Thailand, May 25-28, 2003.
“Kerneltron: Support Vector ‘Machines’ in Silicon,” R. Genov, G. Cauwenberghs, Subm. to IEEE Trans. on Neural Networks, Sept. 2002.
 “A 5.9mW 6.5GMACS CID/DRAM Array Processor,” R. Genov, G. Cauwenberghs, G. Mulliken, and F. Adil, Proc. European Solid-State Circuits Conference (ESSCIRC’2002), Florence, Italy, Sept. 24-26, 2002.
“Kerneltron: Support Vector ‘Machine’ in Silicon,” R. Genov, G. Cauwenberghs, Proc. SVM’2002, Lecture Notes in Computer Science, Niagara Falls, ON, Aug. 10, 2002.
“Delta-Sigma Algorithmic Analog-to-Digital Conversion,” G. Mulliken, F. Adil, G. Cauwenberghs, and  R. Genov, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), Phoenix, AZ, May 26-29, 2002.
“Charge-Based MOS Correlated Double Sampling Comparator and Folding Circuit,” R. Genov and G. Cauwenberghs, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), Phoenix, AZ, May 26-29, 2002.
“Neuromorphic Processor for Real-Time Biosonar Object Detection ,” G. Cauwenberghs, R. T. Edwards, Y. Deng, R. Genov, and D. Lemonds, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’2002), Orlando, FL, May 13-17, 2002.
“Stochastic Mixed-Signal VLSI Architecture for High-Dimensional Kernel Machines,” R. Genov, G. Cauwenberghs, Advances in Neural Information Processing Systems (NIPS'2001), Cambridge, MA: MIT Press, vol. 14, 2002. 
“Charge-Mode Parallel Architecture for Matrix-Vector Multiplication,” R. Genov, G. Cauwenberghs, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, Oct. 2001.
“CID/DRAM Mixed-Signal Parallel Distributed Array Processor,” R. Genov, G. Cauwenberghs, 14th International IEEE ASIC/SOC Conference (ASIC/SOC'2001), Washington, DC, Sept. 12-15, 2001. 
“Embedded Dynamic Memory and Charge-Mode Logic for Parallel Array Processing,” R. Genov, G. Cauwenberghs, Proc. of the 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI'2001), Orlando, FL, July 22-25, 2001. (Best Paper Award.) 
“Massively Parallel Inner-Product Array Processor,” R. Genov, G. Cauwenberghs, Proc. of Int. Joint Conference on Neural Networks (IJCNN'2001), Washington, DC, July 15-19, 2001. 
“Analog Array Processor with Digital Resolution Enhancement and Offset Compensation,” R. Genov, G. Cauwenberghs, Proc. of Conference on Information Sciences and Systems (CISS'2001), Baltimore, MD, March 21-23, 2001. 
“Charge-Mode Parallel Architecture for Matrix-Vector Multiplication,” R. Genov and G. Cauwenberghs, Proc. of 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS'2000), Lansing, MI, Aug. 8-11, 2000. (Best Student Paper Award, 3rd place.) 
“Learning to Navigate from Limited Sensory Input: Experiments with the Khepera Microrobot,” R. Genov, S. Madhavapeddi and G. Cauwenberghs, Proc. of International Joint Conference on Neural Networks (IJCNN'99), Washington, DC, vol. 3, pp. 2061-2064, 1999. (Best Presentation Award.) 
“16-Channel Single-Chip Current-Mode Track-and-Hold Acquisition System with 100 dB Dynamic Range,” R. Genov and G. Cauwenberghs, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'99), Orlando, FL, vol. 6, pp. 350-353, 1999. (Best Student Paper Contest Finalist.)	
MANUSCRIPTS UNDER PREPARATION	
	“Charge-Mode Offset-Compensated Comparator and Folding Circuit for Gray-Code Flash Analog-to-Digital Conversion,” R. Genov and G. Cauwenberghs, to be submitted to Int. J. Analog Integrated Circuits and Signal Processing.
“Algorithmic Delta-Sigma Analog-to-Digital Converters,” G. Mulliken, F. Adil, R. Genov, and G. Cauwenberghs, to be submitted to IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. 
“Stochastic Mixed-Signal VLSI Architecture for High-Dimensional Computational Arrays,” R. Genov, G. Cauwenberghs, to be submitted to IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. 
“16-Channel Single-Chip Current-Mode Track-and-Hold Acquisition System with 100 dB Dynamic Range,” R. Genov and G. Cauwenberghs, to be submitted to IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing.	
PATENTS 	
	“High-Precision Matrix-Vector Multiplication on a Charge-Mode Array with Embedded Dynamic Memory and Stochastic Method Thereof,” R. Genov and G. Cauwenberghs, patent pending, 2002.