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      Roman Genov
%     Curriculum Vitae
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%     Roman Genov
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Department of Electrical and Computer Engineering &
                          	      	Email: roman@jhu.edu \\
The Johns Hopkins University &
                                	URL:  http://bach.ece.jhu.edu/roman \\

Barton Hall 105 &
                                Tel~(410) 243-2832 (H) \\
3400 N.~Charles St., Baltimore, MD 21218 &
                                Fax~(410) 516-5566
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\section{Research Interests}
%VLSI mixed-signal design, analog-to-digital and digital-to-analog
%conversion, implementation of neural systems in silicon, adaptive and
%learning algorithms, intelligent image and signal processing and robot
%navigation using distributed parallel analog and digital signal
%processing.

Analog and digital VLSI circuits, systems and algorithms for parallel
signal processing and neural computation with application to pattern
recognition, sound classification, autonomous systems design and
low-power instrumentation. 

\section{Education}

\begin{description}

\item
Ph.D. Candidate, Electrical and Computer Engineering, {\bf The Johns
Hopkins University}, Baltimore, MD, 2002. \\ 
Dissertation: Massively-Parallel Mixed-Signal VLSI Kernel Machines. \\
% Parallel Mixed-Signal VLSI Systems for Intelligent Kernel Machines
% Kernel Computation on Massively-Parallel VLSI Arrays.
Advisor: Dr. Gert Cauwenberghs

\item
Visiting Student, Center for Biological and Computational Learning,
{\bf Massachusetts Institute of Technology}, Cambridge, MA,
1/99-8/99.

\item
M.S., Electrical and Computer Engineering, {\bf The Johns Hopkins
University}, Baltimore, MD, 1998.\\
GPA 4.00/4.00

\item
B.S. with Highest Honors, Electrical Engineering, {\bf Rochester
Institute of Technology}, Rochester, NY, 1996. \\ 
GPA 4.00/4.00, Rank in class - 1/316

\end{description}


\section{Experience}

\subsection{Academic and Industrial}

\begin{description}

\item
Research Assistant, Adaptive Microsystems Laboratory, Department of
Electrical and Computer Engineering, {\bf The Johns Hopkins
University}, Baltimore, MD, 9/96-present. 

Massively parallel mixed-signal VLSI processor implementing a Support
Vector Machine (SVM) for high-dimensional data classification. Pattern
recognition and acoustic classification systems utilizing SVM parallel
processing chips. Low-power charge-mode parallel A/D converters,
delta-sigma converters, and high-speed, high-resolution, digitally
calibrated pipelined algorithmic A/D converters (with {\bf Northrop
Grumman Corporation}, Baltimore, MD). Reinforcement learning
algorithms for intelligent robot navigation. Low-power analog and
digital VLSI chips for high-performance instrumentation. Xilinx
FPGA-based PCI bus interfaces for video and image processing
microchips. Linux and Win2000 C++ device drivers, and Matlab
interfaces.


\item
Visiting Researcher, Autonomous Systems Laboratory, {\bf Swiss Federal
Institute of Technology}, Lausanne, Switzerland, 6/98-7/98.

Developed Q-learning-based algorithms for mobile micro-robot
navigation. Investigated their mapping onto VLSI architectures.

\item
Design engineer CO-OP, Advanced Development Team of the Color Digital
Imaging Systems Division, {\bf Xerox Corporation}, Webster, NY,
3/96-8/96.

Hardware-software co-design with Verilog, Xilinx tools, PALASM.
Design and development of electrical and computer systems for new
generation color copiers.

\item
Technical Director Assistant, Chesapeake Design Center, {\bf Atmel
Corporation}, Columbia, MD, 6/95-12/95.

Design and simulation of digital cells for ASICs, and design of
layouts for different ASIC implementations. Created a Perl extraction
tool to automate the process of getting data from HSPICE output files
into a condensed and useful state used for creating of Verilog ASIC
models.  Analysis time has been reduced by 10-15 times.

\end{description}

\subsection{Teaching}

\begin{description}

\item
Graduate Teaching Assistant, Johns Hopkins University, Baltimore, MD. \\
``Digital Signal Processing,'' 9/97-12/97, 9/98-12/98.\\
``Electronic Design Laboratory,'' 1/98-5/98.\\
``Analog and Digital VLSI Systems and Architecture,'' 9/99-12/99, 9/2001-12/2001. 

\item
Teaching Assistant, Rochester Institute of Technology, Rochester, NY. \\
``Digital Systems Design,'' 2/95-5/95. \\
``C Programming,'' 2/96-5/96. 

\end{description}



\section{Awards and Honors}

\begin{description}

\item
Best Paper Award, 5th World Multi-Conference on Systemics, Cybernetics
and Informatics (SCI'2001), Roman Genov, with Gert Cauwenberghs, 2001.

\item
Best Student Paper Award, 3rd place, IEEE Midwest Symposium on
Circuits and Systems (MWSCAS'2000), Roman Genov, with Gert
Cauwenberghs, 2000.

\item
Best Presentation Award, IEEE International Joint Conference on Neural
Networks (IJCNN'99), Roman Genov, with Srinadh Madhavapeddi and Gert
Cauwenberghs, 1999.

\item
Best Student Paper Contest Finalist, IEEE International Symposium on
Circuits and Systems (ISCAS'99), Roman Genov, with Gert Cauwenberghs,
1999.

\item
Rochester Institute of Technology Presidential Fellowship, 1995-96.

\item
American Council of Teachers of Russian Fellowship, 1994-95.

\end{description}




%
% should include the following sections:
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% \section{Refereed Journal Publications}
% \section{Journal Papers Under Review}
% \section{Conference Publications}
% \section{Books and Book Chapters}
% \section{Other Publications}
% \section{Patents}


\section{Invited Presentations}

\begin{description}

\item
``VLSI Array for Massively Parallel Kernel Computation,'' R.~Genov,
invited presentation at Workshop on Neuromorphic
Engineering. Telluride, CO, July~2001.

%\item
%``Adaptive Microsystems and Intelligent Machines,'' R.~Genov, Johns
%Hopkins University ECE Department seminar, Baltimore, MD, Apr.~2001.

\item
``Q-Learning: Experiments on Microrobots,'' R.~Genov, with
S.~Madhavapeddi and G.~Cauwenberghs, invited presentation at Neural
Information Processing Systems (NIPS'1999) workshop, Breckenridge, CO,
Dec.~1998.

\end{description}


\section{Activities}

\begin{description}

\item
Society Memberships: IEEE (Institute of Electrical and Electronic
Engineers) Circuits and Systems Society, Computer Society.

\item 
High-Technology Entrepreneurship Interactive Program, 1999.

\item
Tau Beta Pi Engineering Future, Leadership and Technical Management
Interactive Workshop, 1998.

\item 
IEEE JHU Chapter Treasurer, 1997.

\item 
Electrical Engineering Class President, 1991-1994.

\item 
Volleyball, Ping-Pong, Accordion.

\end{description}

%\section{Journal, Conference, Book, Proposal Reviews}
%IEEE Transactions on Circuits and Systems I and II, % (2 papers). \\
%IEEE International Symposium on Circuits and Systems, % (1 paper). \\

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