Firewire on the TM-4
There are two identical Firewire interfaces available to fpga-1.
Each interface consists of a TSB12LV32
chip that on one end is directly connected to fpga-1, and on another end is connected to a Physical-layer
chip that drives two of the four Firewire ports on the TM-4.
Signals
These are the names of all the signals that map to pins on fpga-1 driving
the two TSB12LV32 Link-Layer chips:
------
Chip A
------
output tm4_fir_resetn
output tm4_fir_bclkA
output tm4_fir_maA[0:6]
inout tm4_fir_mdA[0:15]
input tm4_fir_mcanA
output tm4_fir_mcsnA
output tm4_fir_mrwnA
input tm4_fir_teanA
output tm4_fir_coldfireA
output tm4_fir_lendianA
output tm4_fir_m8bitA
output tm4_fir_mcmodeA
output tm4_fir_mdinvA
input tm4_fir_intnA
input tm4_fir_statA[0:2]
input tm4_fir_dmclkA
inout tm4_fir_dmdA[0:15]
input tm4_fir_cystartA
input tm4_fir_dmrwA
input tm4_fir_pktflagA
output tm4_fir_dmreadyA
input tm4_fir_dmpreA
input tm4_fir_dmdoneA
input tm4_fir_dmerrorA
------
Chip B
------
Signal names are the same as Chip A but end with 'B'
instead of 'A' (tm4_fir_bclkB instead of tm4_fir_bclkA, etc)
The only exception is that tm4_fir_resetn becomes tm4_fir_resetB
The functionality of all these signals is described in the TSB12LV32 manual.
A few things to be aware of:
- Bus signals have bit 0 as the MSB
- Driving tm4_fir_bclk directly with a global clock is not recommended since there will be significant
clock skew. The recommended way to do it is through a PLL and adjusting the output phase shift.