datasheet for qsys

pcie

altera_pcie_hard_ip v13.0

sgdma_read	descriptor_read	pcie
	txs
	descriptor_write
	txs
	m_read
	txs

sgdma_write	descriptor_read
	txs
	descriptor_write
	txs
	m_write
	txs
			pcie_core_reset	clk50
			clk_in_reset	clk50

			bar0	sgdma_read
			csr
			rxm_irq
			csr_irq

			bar0	sgdma_write
			csr
			rxm_irq
			csr_irq

Parameters

under_test	0
INTENDED_DEVICE_FAMILY	STRATIXIV
pcie_qsys	1
p_pcie_hip_type	0
lane_mask	240
my_gen2_lane_rate_mode	true
max_link_width	4
p_pcie_txrx_clock	100 MHz
p_pcie_app_clk	0
millisecond_cycle_count	250000
core_clk_freq	2500
p_pcie_test_out_width	None
enable_gen2_core	true
gen2_lane_rate_mode	true
no_soft_reset	false
p_pcie_version	2.0
core_clk_divider	2
enable_ch0_pclk_out	false
core_clk_source	PLL_FIXED_CLK
NUM_PREFETCH_MASTERS	1
CB_P2A_AVALON_ADDR_B0	0x00000000
bar0_size_mask	15
bar0_io_space	false
bar0_64bit_mem_space	false
bar0_prefetchable	false
CB_P2A_AVALON_ADDR_B1	0x00000000
bar1_size_mask	0
bar1_io_space	false
bar1_64bit_mem_space	false
bar1_prefetchable	false
CB_P2A_AVALON_ADDR_B2	0x00000000
bar2_size_mask	0
bar2_io_space	false
bar2_64bit_mem_space	false
bar2_prefetchable	false
CB_P2A_AVALON_ADDR_B3	0x00000000
bar3_size_mask	0
bar3_io_space	false
bar3_64bit_mem_space	false
bar3_prefetchable	false
CB_P2A_AVALON_ADDR_B4	0x00000000
bar4_size_mask	0
bar4_io_space	false
bar4_64bit_mem_space	false
bar4_prefetchable	false
CB_P2A_AVALON_ADDR_B5	0x00000000
bar5_size_mask	0
bar5_io_space	false
bar5_64bit_mem_space	false
bar5_prefetchable	false
fixed_address_mode	0
CB_P2A_FIXED_AVALON_ADDR_B0	0
CB_P2A_FIXED_AVALON_ADDR_B1	0
CB_P2A_FIXED_AVALON_ADDR_B2	0
CB_P2A_FIXED_AVALON_ADDR_B3	0
CB_P2A_FIXED_AVALON_ADDR_B4	0
CB_P2A_FIXED_AVALON_ADDR_B5	0
BAR	0,1,2,3,4,5
BAR Type	32 bit Non-Prefetchable,Not used,Not used,Not used,Not used,Not used
BAR Size	15,0,0,0,0,0
Avalon Base Address	0,0,0,0,0,0
vendor_id	4466
device_id	4919
revision_id	1
class_code	16711680
subsystem_vendor_id	4466
subsystem_device_id	4919
port_link_number	1
msi_function_count	0
enable_msi_64bit_addressing	true
enable_function_msix_support	false
eie_before_nfts_count	4
enable_completion_timeout_disable	false
completion_timeout	NONE
enable_adapter_half_rate_mode	false
msix_pba_bir	0
msix_pba_offset	0
msix_table_bir	0
msix_table_offset	0
msix_table_size	0
use_crc_forwarding	false
surprise_down_error_support	false
dll_active_report_support	false
bar_io_window_size	32BIT
bar_prefetchable	32
hot_plug_support	0
no_command_completed	true
slot_power_limit	0
slot_power_scale	0
slot_number	0
enable_slot_register	false
link_common_clock	1
advanced_errors	false
enable_ecrc_check	false
enable_ecrc_gen	false
my_advanced_errors	false
my_enable_ecrc_check	false
my_enable_ecrc_gen	false
max_payload_size	1
p_pcie_target_performance_preset	Maximum
retry_buffer_last_active_address	2047
credit_buffer_allocation_aux	ABSOLUTE
vc0_rx_flow_ctrl_posted_header	55
vc0_rx_flow_ctrl_posted_data	403
vc0_rx_flow_ctrl_nonposted_header	54
vc0_rx_flow_ctrl_nonposted_data	0
vc0_rx_flow_ctrl_compl_header	48
vc0_rx_flow_ctrl_compl_data	256
RX_BUF	9
RH_NUM	7
G_TAG_NUM0	32
endpoint_l0_latency	0
endpoint_l1_latency	0
enable_l1_aspm	false
l01_entry_latency	31
diffclock_nfts_count	255
sameclock_nfts_count	255
l1_exit_latency_sameclock	7
l1_exit_latency_diffclock	7
l0_exit_latency_sameclock	7
l0_exit_latency_diffclock	7
gen2_diffclock_nfts_count	255
gen2_sameclock_nfts_count	255
CG_COMMON_CLOCK_MODE	1
CB_PCIE_MODE	0
AST_LITE	0
CB_PCIE_RX_LITE	0
CG_RXM_IRQ_NUM	16
CG_AVALON_S_ADDR_WIDTH	20
bypass_tl	false
CG_IMPL_CRA_AV_SLAVE_PORT	1
CG_NO_CPL_REORDERING	0
CG_ENABLE_A2P_INTERRUPT	0
CG_IRQ_BIT_ENA	65535
CB_A2P_ADDR_MAP_IS_FIXED	1
CB_A2P_ADDR_MAP_NUM_ENTRIES	1
CB_A2P_ADDR_MAP_PASS_THRU_BITS	32
CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW	0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH	0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW	0
Address Page	0,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
PCIe Address 63:32	0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000
PCIe Address 31:0	0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000
RXM_DATA_WIDTH	64
RXM_BEN_WIDTH	8
CB_TXS_ADDRESS_WIDTH	7
TL_SELECTION	1
pcie_mode	SHARED_MODE
single_rx_detect	4
enable_coreclk_out_half_rate	false
low_priority_vc	0
SLAVE_ADDRESS_MAP_0	15
SLAVE_ADDRESS_MAP_1	0
SLAVE_ADDRESS_MAP_2	0
SLAVE_ADDRESS_MAP_3	0
SLAVE_ADDRESS_MAP_4	0
SLAVE_ADDRESS_MAP_5	0
SLAVE_ADDRESS_MAP_1_0	0
SLAVE_ADDRESS_MAP_3_2	0
SLAVE_ADDRESS_MAP_5_4	0
deviceFamily	STRATIXIV
wiz_subprotocol	Gen 2-x4
link_width	4
cyclone4	0
AUTO_CAL_BLK_CLK_CLOCK_RATE	0
AUTO_CAL_BLK_CLK_CLOCK_DOMAIN	3
AUTO_CAL_BLK_CLK_RESET_DOMAIN	3
AUTO_DEVICE	EP4SGX530KH40C2
generateLegacySim	false

Software Assignments

(none)

sgdma_read

altera_avalon_sgdma v13.0.1.99.2

clk50	clk	sgdma_read
	clk
	clk_reset
	reset

pcie	bar0
	csr
	rxm_irq
	csr_irq
			descriptor_read	pcie
			txs
			descriptor_write
			txs
			m_read
			txs

Parameters

addressWidth	32
alwaysDoMaxBurst	true
avalonMMByteReorderMode	1
dataTransferFIFODepth	2
enableBurstTransfers	true
enableDescriptorReadMasterBurst	true
enableUnalignedTransfers	false
internalFIFODepth	2
readBlockDataWidth	64
readBurstcountWidth	6
sinkErrorWidth	0
sourceErrorWidth	0
transferMode	MEMORY_TO_STREAM
writeBurstcountWidth	4
deviceFamilyString	STRATIXIV
actualDataTransferFIFODepth	32
commandFIFODataWidth	104
symbolsPerBeat	8
byteEnableWidth	8
emptyWidth	3
hasReadBlock	true
hasWriteBlock	false
deviceFamily	UNKNOWN
generateLegacySim	false

Software Assignments

ADDRESS_WIDTH	32
ALWAYS_DO_MAX_BURST	1
ATLANTIC_CHANNEL_DATA_WIDTH	4
AVALON_MM_BYTE_REORDER_MODE	1
BURST_DATA_WIDTH	8
BURST_TRANSFER	1
BYTES_TO_TRANSFER_DATA_WIDTH	16
CHAIN_WRITEBACK_DATA_WIDTH	32
COMMAND_FIFO_DATA_WIDTH	104
CONTROL_DATA_WIDTH	8
CONTROL_SLAVE_ADDRESS_WIDTH	4
CONTROL_SLAVE_DATA_WIDTH	32
DESCRIPTOR_READ_BURST	1
DESC_DATA_WIDTH	32
HAS_READ_BLOCK	1
HAS_WRITE_BLOCK	0
IN_ERROR_WIDTH	0
OUT_ERROR_WIDTH	0
READ_BLOCK_DATA_WIDTH	64
READ_BURSTCOUNT_WIDTH	6
STATUS_TOKEN_DATA_WIDTH	24
STREAM_DATA_WIDTH	64
SYMBOLS_PER_BEAT	8
UNALIGNED_TRANSFER	0
WRITE_BLOCK_DATA_WIDTH	64
WRITE_BURSTCOUNT_WIDTH	4

sgdma_write

altera_avalon_sgdma v13.0.1.99.2

clk50	clk	sgdma_write
	clk
	clk_reset
	reset

pcie	bar0
	csr
	rxm_irq
	csr_irq
			descriptor_read	pcie
			txs
			descriptor_write
			txs
			m_write
			txs

Parameters

addressWidth	32
alwaysDoMaxBurst	true
avalonMMByteReorderMode	1
dataTransferFIFODepth	2
enableBurstTransfers	true
enableDescriptorReadMasterBurst	true
enableUnalignedTransfers	false
internalFIFODepth	2
readBlockDataWidth	64
readBurstcountWidth	4
sinkErrorWidth	0
sourceErrorWidth	0
transferMode	STREAM_TO_MEMORY
writeBurstcountWidth	6
deviceFamilyString	STRATIXIV
actualDataTransferFIFODepth	32
commandFIFODataWidth	104
symbolsPerBeat	8
byteEnableWidth	8
emptyWidth	3
hasReadBlock	false
hasWriteBlock	true
deviceFamily	UNKNOWN
generateLegacySim	false

Software Assignments

ADDRESS_WIDTH	32
ALWAYS_DO_MAX_BURST	1
ATLANTIC_CHANNEL_DATA_WIDTH	4
AVALON_MM_BYTE_REORDER_MODE	1
BURST_DATA_WIDTH	8
BURST_TRANSFER	1
BYTES_TO_TRANSFER_DATA_WIDTH	16
CHAIN_WRITEBACK_DATA_WIDTH	32
COMMAND_FIFO_DATA_WIDTH	104
CONTROL_DATA_WIDTH	8
CONTROL_SLAVE_ADDRESS_WIDTH	4
CONTROL_SLAVE_DATA_WIDTH	32
DESCRIPTOR_READ_BURST	1
DESC_DATA_WIDTH	32
HAS_READ_BLOCK	0
HAS_WRITE_BLOCK	1
IN_ERROR_WIDTH	0
OUT_ERROR_WIDTH	0
READ_BLOCK_DATA_WIDTH	64
READ_BURSTCOUNT_WIDTH	4
STATUS_TOKEN_DATA_WIDTH	24
STREAM_DATA_WIDTH	64
SYMBOLS_PER_BEAT	8
UNALIGNED_TRANSFER	0
WRITE_BLOCK_DATA_WIDTH	64
WRITE_BURSTCOUNT_WIDTH	6

	pcie	sgdma_read			sgdma_write
	bar0	descriptor_read	descriptor_write	m_read	descriptor_read	descriptor_write	m_write
pcie
txs		0x00000000	0x00000000	0x00000000	0x00000000	0x00000000	0x00000000
cra	0x00000000
sgdma_read
csr	0x00004000
sgdma_write
csr	0x00004040

clk50

Parameters

Software Assignments

pcie

Parameters

Software Assignments

sgdma_read

Parameters

Software Assignments

sgdma_write

Parameters

Software Assignments