---

clk50

clock_source v13.0

Parameters clockFrequency 100000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

sgdma_read

altera_avalon_sgdma v13.0.1.99.2

Parameters addressWidth 32 alwaysDoMaxBurst true avalonMMByteReorderMode 1 dataTransferFIFODepth 2 enableBurstTransfers true enableDescriptorReadMasterBurst true enableUnalignedTransfers false internalFIFODepth 2 readBlockDataWidth 64 readBurstcountWidth 6 sinkErrorWidth 0 sourceErrorWidth 0 transferMode MEMORY_TO_STREAM writeBurstcountWidth 4 deviceFamilyString STRATIXV actualDataTransferFIFODepth 32 commandFIFODataWidth 104 symbolsPerBeat 8 byteEnableWidth 8 emptyWidth 3 hasReadBlock true hasWriteBlock false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ADDRESS_WIDTH 32 ALWAYS_DO_MAX_BURST 1 ATLANTIC_CHANNEL_DATA_WIDTH 4 AVALON_MM_BYTE_REORDER_MODE 1 BURST_DATA_WIDTH 8 BURST_TRANSFER 1 BYTES_TO_TRANSFER_DATA_WIDTH 16 CHAIN_WRITEBACK_DATA_WIDTH 32 COMMAND_FIFO_DATA_WIDTH 104 CONTROL_DATA_WIDTH 8 CONTROL_SLAVE_ADDRESS_WIDTH 4 CONTROL_SLAVE_DATA_WIDTH 32 DESCRIPTOR_READ_BURST 1 DESC_DATA_WIDTH 32 HAS_READ_BLOCK 1 HAS_WRITE_BLOCK 0 IN_ERROR_WIDTH 0 OUT_ERROR_WIDTH 0 READ_BLOCK_DATA_WIDTH 64 READ_BURSTCOUNT_WIDTH 6 STATUS_TOKEN_DATA_WIDTH 24 STREAM_DATA_WIDTH 64 SYMBOLS_PER_BEAT 8 UNALIGNED_TRANSFER 0 WRITE_BLOCK_DATA_WIDTH 64 WRITE_BURSTCOUNT_WIDTH 4

---

sgdma_write

altera_avalon_sgdma v13.0.1.99.2

Parameters addressWidth 32 alwaysDoMaxBurst true avalonMMByteReorderMode 1 dataTransferFIFODepth 2 enableBurstTransfers true enableDescriptorReadMasterBurst true enableUnalignedTransfers false internalFIFODepth 2 readBlockDataWidth 64 readBurstcountWidth 4 sinkErrorWidth 0 sourceErrorWidth 0 transferMode STREAM_TO_MEMORY writeBurstcountWidth 6 deviceFamilyString STRATIXV actualDataTransferFIFODepth 32 commandFIFODataWidth 104 symbolsPerBeat 8 byteEnableWidth 8 emptyWidth 3 hasReadBlock false hasWriteBlock true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ADDRESS_WIDTH 32 ALWAYS_DO_MAX_BURST 1 ATLANTIC_CHANNEL_DATA_WIDTH 4 AVALON_MM_BYTE_REORDER_MODE 1 BURST_DATA_WIDTH 8 BURST_TRANSFER 1 BYTES_TO_TRANSFER_DATA_WIDTH 16 CHAIN_WRITEBACK_DATA_WIDTH 32 COMMAND_FIFO_DATA_WIDTH 104 CONTROL_DATA_WIDTH 8 CONTROL_SLAVE_ADDRESS_WIDTH 4 CONTROL_SLAVE_DATA_WIDTH 32 DESCRIPTOR_READ_BURST 1 DESC_DATA_WIDTH 32 HAS_READ_BLOCK 0 HAS_WRITE_BLOCK 1 IN_ERROR_WIDTH 0 OUT_ERROR_WIDTH 0 READ_BLOCK_DATA_WIDTH 64 READ_BURSTCOUNT_WIDTH 4 STATUS_TOKEN_DATA_WIDTH 24 STREAM_DATA_WIDTH 64 SYMBOLS_PER_BEAT 8 UNALIGNED_TRANSFER 0 WRITE_BLOCK_DATA_WIDTH 64 WRITE_BURSTCOUNT_WIDTH 6

---

pcie_sv_hip_avmm_0

altera_pcie_sv_hip_avmm v13.0

Parameters INTENDED_DEVICE_FAMILY STRATIXV pcie_qsys 1 lane_mask_hwtcl x8 gen123_lane_rate_mode_hwtcl Gen2 (5.0 Gbps) port_type_hwtcl Native endpoint pcie_spec_version_hwtcl 2.1 rxbuffer_rxreq_hwtcl Balanced pll_refclk_freq_hwtcl 100 MHz set_pld_clk_x1_625MHz_hwtcl 0 in_cvp_mode_hwtcl 0 enable_tl_only_sim_hwtcl 0 use_atx_pll_hwtcl 0 SLAVE_ADDRESS_MAP_0 15 CB_P2A_AVALON_ADDR_B0 0x00000000 SLAVE_ADDRESS_MAP_1 0 CB_P2A_AVALON_ADDR_B1 0x00000000 SLAVE_ADDRESS_MAP_2 0 CB_P2A_AVALON_ADDR_B2 0x00000000 SLAVE_ADDRESS_MAP_3 0 CB_P2A_AVALON_ADDR_B3 0x00000000 SLAVE_ADDRESS_MAP_4 0 CB_P2A_AVALON_ADDR_B4 0x00000000 SLAVE_ADDRESS_MAP_5 0 CB_P2A_AVALON_ADDR_B5 0x00000000 NUM_PREFETCH_MASTERS 1 bar0_type_hwtcl 2 bar0_size_mask_hwtcl 15 bar0_io_space_hwtcl Disabled bar0_64bit_mem_space_hwtcl Disabled bar0_prefetchable_hwtcl Disabled bar1_type_hwtcl 0 bar1_size_mask_hwtcl 0 bar1_io_space_hwtcl Disabled bar1_prefetchable_hwtcl Disabled bar2_type_hwtcl 0 bar2_size_mask_hwtcl 0 bar2_io_space_hwtcl Disabled bar2_64bit_mem_space_hwtcl Disabled bar2_prefetchable_hwtcl Disabled bar3_type_hwtcl 0 bar3_size_mask_hwtcl 0 bar3_io_space_hwtcl Disabled bar3_prefetchable_hwtcl Disabled bar4_type_hwtcl 0 bar4_size_mask_hwtcl 0 bar4_io_space_hwtcl Disabled bar4_64bit_mem_space_hwtcl Disabled bar4_prefetchable_hwtcl Disabled bar5_type_hwtcl 0 bar5_size_mask_hwtcl 0 bar5_io_space_hwtcl Disabled bar5_prefetchable_hwtcl Disabled fixed_address_mode 0 CB_P2A_FIXED_AVALON_ADDR_B0 0 CB_P2A_FIXED_AVALON_ADDR_B1 0 CB_P2A_FIXED_AVALON_ADDR_B2 0 CB_P2A_FIXED_AVALON_ADDR_B3 0 CB_P2A_FIXED_AVALON_ADDR_B4 0 CB_P2A_FIXED_AVALON_ADDR_B5 0 vendor_id_hwtcl 4466 device_id_hwtcl 4920 revision_id_hwtcl 2 class_code_hwtcl 16711680 subsystem_vendor_id_hwtcl 4466 subsystem_device_id_hwtcl 4920 max_payload_size_hwtcl 128 extend_tag_field_hwtcl 32 completion_timeout_hwtcl ABCD enable_completion_timeout_disable_hwtcl 1 use_aer_hwtcl 0 ecrc_check_capable_hwtcl 0 ecrc_gen_capable_hwtcl 0 use_crc_forwarding_hwtcl 0 port_link_number_hwtcl 1 dll_active_report_support_hwtcl 0 surprise_down_error_support_hwtcl 0 slotclkcfg_hwtcl 1 msi_multi_message_capable_hwtcl 1 msi_64bit_addressing_capable_hwtcl true msi_masking_capable_hwtcl false msi_support_hwtcl true enable_function_msix_support_hwtcl 0 msix_table_size_hwtcl 0 msix_table_offset_hwtcl 0 msix_table_bir_hwtcl 0 msix_pba_offset_hwtcl 0 msix_pba_bir_hwtcl 0 enable_slot_register_hwtcl 0 slot_power_scale_hwtcl 0 slot_power_limit_hwtcl 0 slot_number_hwtcl 0 endpoint_l0_latency_hwtcl 0 endpoint_l1_latency_hwtcl 0 CG_COMMON_CLOCK_MODE 1 avmm_width_hwtcl 128 AVALON_ADDR_WIDTH 32 avmm_burst_width_hwtcl 6 CB_PCIE_MODE 0 CB_PCIE_RX_LITE 0 CB_RXM_DATA_WIDTH 128 AST_LITE 0 CG_RXM_IRQ_NUM 16 CG_AVALON_S_ADDR_WIDTH 32 bypass_tl false CG_IMPL_CRA_AV_SLAVE_PORT 1 CG_ENABLE_ADVANCED_INTERRUPT 0 CG_ENABLE_A2P_INTERRUPT 0 TX_S_ADDR_WIDTH 32 CB_A2P_ADDR_MAP_IS_FIXED 0 CB_A2P_ADDR_MAP_NUM_ENTRIES 2 CB_A2P_ADDR_MAP_PASS_THRU_BITS 31 BYPASSS_A2P_TRANSLATION 0 CB_RP_S_ADDR_WIDTH 32 CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW 0 Address Page 0\,1\,2\,3\,4\,5\,6\,7\,8\,9\,10\,11\,12\,13\,14\,15 PCIe Address 63:32 0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000 PCIe Address 31:0 0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000 RXM_DATA_WIDTH 64 RXM_BEN_WIDTH 8 ast_width_hwtcl Avalon-ST 128-bit use_rx_st_be_hwtcl 0 use_ast_parity 0 pld_clk_MHz 2500 millisecond_cycle_count_hwtcl 248500 port_width_be_hwtcl 16 port_width_data_hwtcl 128 hip_reconfig_hwtcl 0 vsec_id_hwtcl 40960 vsec_rev_hwtcl 0 expansion_base_address_register_hwtcl 0 io_window_addr_width_hwtcl 0 prefetchable_mem_window_addr_width_hwtcl 0 advanced_default_parameter_override 0 override_rxbuffer_cred_preset 0 bypass_cdc_hwtcl false enable_rx_buffer_checking_hwtcl false disable_link_x2_support_hwtcl false wrong_device_id_hwtcl disable data_pack_rx_hwtcl disable ltssm_1ms_timeout_hwtcl disable ltssm_freqlocked_check_hwtcl disable deskew_comma_hwtcl skp_eieos_deskw device_number_hwtcl 0 pipex1_debug_sel_hwtcl disable pclk_out_sel_hwtcl pclk no_soft_reset_hwtcl false maximum_current_hwtcl 0 d1_support_hwtcl false d2_support_hwtcl false d0_pme_hwtcl false d1_pme_hwtcl false d2_pme_hwtcl false d3_hot_pme_hwtcl false d3_cold_pme_hwtcl false low_priority_vc_hwtcl single_vc disable_snoop_packet_hwtcl false enable_l1_aspm_hwtcl false set_l0s_hwtcl 0 rx_ei_l0s_hwtcl 0 enable_l0s_aspm_hwtcl false aspm_config_management_hwtcl true l1_exit_latency_sameclock_hwtcl 0 l1_exit_latency_diffclock_hwtcl 0 hot_plug_support_hwtcl 0 extended_tag_reset_hwtcl false no_command_completed_hwtcl true interrupt_pin_hwtcl inta bridge_port_vga_enable_hwtcl false bridge_port_ssid_support_hwtcl false ssvid_hwtcl 0 ssid_hwtcl 0 eie_before_nfts_count_hwtcl 4 gen2_diffclock_nfts_count_hwtcl 255 gen2_sameclock_nfts_count_hwtcl 255 l0_exit_latency_sameclock_hwtcl 6 l0_exit_latency_diffclock_hwtcl 6 atomic_op_routing_hwtcl false atomic_op_completer_32bit_hwtcl false atomic_op_completer_64bit_hwtcl false cas_completer_128bit_hwtcl false ltr_mechanism_hwtcl false tph_completer_hwtcl false extended_format_field_hwtcl false atomic_malformed_hwtcl true flr_capability_hwtcl false enable_adapter_half_rate_mode_hwtcl false vc0_clk_enable_hwtcl true register_pipe_signals_hwtcl false skp_os_gen3_count_hwtcl 0 tx_cdc_almost_empty_hwtcl 5 rx_l0s_count_idl_hwtcl 0 cdc_dummy_insert_limit_hwtcl 11 ei_delay_powerdown_count_hwtcl 10 skp_os_schedule_count_hwtcl 0 fc_init_timer_hwtcl 1024 l01_entry_latency_hwtcl 31 flow_control_update_count_hwtcl 30 flow_control_timeout_count_hwtcl 200 retry_buffer_last_active_address_hwtcl 2047 reserved_debug_hwtcl 0 bypass_clk_switch_hwtcl true l2_async_logic_hwtcl disable indicator_hwtcl 0 diffclock_nfts_count_hwtcl 128 sameclock_nfts_count_hwtcl 128 rx_cdc_almost_full_hwtcl 12 tx_cdc_almost_full_hwtcl 11 credit_buffer_allocation_aux_hwtcl absolute vc0_rx_flow_ctrl_posted_header_hwtcl 50 vc0_rx_flow_ctrl_posted_data_hwtcl 358 vc0_rx_flow_ctrl_nonposted_header_hwtcl 56 vc0_rx_flow_ctrl_nonposted_data_hwtcl 0 vc0_rx_flow_ctrl_compl_header_hwtcl 0 vc0_rx_flow_ctrl_compl_data_hwtcl 0 cpl_spc_header_hwtcl 112 cpl_spc_data_hwtcl 448 gen3_rxfreqlock_counter_hwtcl 0 gen3_skip_ph2_ph3_hwtcl 0 g3_bypass_equlz_hwtcl 0 cvp_data_compressed_hwtcl false cvp_data_encrypted_hwtcl false cvp_mode_reset_hwtcl false cvp_clk_reset_hwtcl false cseb_cpl_status_during_cvp_hwtcl config_retry_status core_clk_sel_hwtcl pld_clk cvp_rate_sel_hwtcl full_rate g3_dis_rx_use_prst_hwtcl true g3_dis_rx_use_prst_ep_hwtcl true deemphasis_enable_hwtcl false reconfig_to_xcvr_width 700 reconfig_from_xcvr_width 460 single_rx_detect_hwtcl 0 hip_hard_reset_hwtcl 1 force_hrc 0 force_src 0 serial_sim_hwtcl 1 advanced_default_hwtcl_bypass_cdc false advanced_default_hwtcl_enable_rx_buffer_checking false advanced_default_hwtcl_disable_link_x2_support false advanced_default_hwtcl_wrong_device_id disable advanced_default_hwtcl_data_pack_rx disable advanced_default_hwtcl_ltssm_1ms_timeout disable advanced_default_hwtcl_ltssm_freqlocked_check disable advanced_default_hwtcl_deskew_comma com_deskw advanced_default_hwtcl_device_number 0 advanced_default_hwtcl_pipex1_debug_sel disable advanced_default_hwtcl_pclk_out_sel pclk advanced_default_hwtcl_no_soft_reset false advanced_default_hwtcl_maximum_current 0 advanced_default_hwtcl_d1_support false advanced_default_hwtcl_d2_support false advanced_default_hwtcl_d0_pme false advanced_default_hwtcl_d1_pme false advanced_default_hwtcl_d2_pme false advanced_default_hwtcl_d3_hot_pme false advanced_default_hwtcl_d3_cold_pme false advanced_default_hwtcl_low_priority_vc single_vc advanced_default_hwtcl_disable_snoop_packet false advanced_default_hwtcl_enable_l1_aspm false advanced_default_hwtcl_set_l0s 0 advanced_default_hwtcl_l1_exit_latency_sameclock 0 advanced_default_hwtcl_l1_exit_latency_diffclock 0 advanced_default_hwtcl_hot_plug_support 0 advanced_default_hwtcl_extended_tag_reset false advanced_default_hwtcl_no_command_completed true advanced_default_hwtcl_interrupt_pin inta advanced_default_hwtcl_bridge_port_vga_enable false advanced_default_hwtcl_bridge_port_ssid_support false advanced_default_hwtcl_ssvid 0 advanced_default_hwtcl_ssid 0 advanced_default_hwtcl_eie_before_nfts_count 4 advanced_default_hwtcl_gen2_diffclock_nfts_count 255 advanced_default_hwtcl_gen2_sameclock_nfts_count 255 advanced_default_hwtcl_l0_exit_latency_sameclock 6 advanced_default_hwtcl_l0_exit_latency_diffclock 6 advanced_default_hwtcl_atomic_op_routing false advanced_default_hwtcl_atomic_op_completer_32bit false advanced_default_hwtcl_atomic_op_completer_64bit false advanced_default_hwtcl_cas_completer_128bit false advanced_default_hwtcl_ltr_mechanism false advanced_default_hwtcl_tph_completer false advanced_default_hwtcl_extended_format_field false advanced_default_hwtcl_atomic_malformed true advanced_default_hwtcl_flr_capability false advanced_default_hwtcl_enable_adapter_half_rate_mode false advanced_default_hwtcl_vc0_clk_enable true advanced_default_hwtcl_register_pipe_signals false advanced_default_hwtcl_skp_os_gen3_count 0 advanced_default_hwtcl_tx_cdc_almost_empty 5 advanced_default_hwtcl_rx_l0s_count_idl 0 advanced_default_hwtcl_cdc_dummy_insert_limit 11 advanced_default_hwtcl_ei_delay_powerdown_count 10 advanced_default_hwtcl_skp_os_schedule_count 0 advanced_default_hwtcl_fc_init_timer 1024 advanced_default_hwtcl_l01_entry_latency 31 advanced_default_hwtcl_flow_control_update_count 30 advanced_default_hwtcl_flow_control_timeout_count 200 advanced_default_hwtcl_retry_buffer_last_active_address 2047 advanced_default_hwtcl_reserved_debug 0 hwtcl_override_g2_txvod 1 rpre_emph_a_val_hwtcl 9 rpre_emph_b_val_hwtcl 0 rpre_emph_c_val_hwtcl 16 rpre_emph_d_val_hwtcl 13 rpre_emph_e_val_hwtcl 5 rvod_sel_a_val_hwtcl 42 rvod_sel_b_val_hwtcl 38 rvod_sel_c_val_hwtcl 38 rvod_sel_d_val_hwtcl 43 rvod_sel_e_val_hwtcl 15 AUTO_REFCLK_CLOCK_RATE 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

alt_xcvr_reconfig_0

alt_xcvr_reconfig v13.0

Parameters device_family STRATIXV number_of_reconfig_interfaces 10 gui_split_sizes enable_offset 1 enable_lc 1 enable_dcd 0 enable_dcd_power_up 1 enable_analog 1 enable_eyemon 0 ber_en 0 enable_ber 0 enable_dfe 0 enable_adce 0 enable_mif 0 gui_enable_pll 0 enable_pll 0 gui_cal_status_port false AUTO_MGMT_CLK_CLK_CLOCK_RATE 100000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)